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FEATURES

· JEDEC pinout in a 100-pin, dual in-line memory

module (DIMM)

· 4MB (1 Meg x 32) and 8MB (2 Meg x 32)
· High-performance CMOS silicon-gate process
· Single +3.3V

0.3V power supply

· All inputs, outputs and clocks are TTL-compatible
· Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN

· 1,024-cycle refresh distributed across 16ms
· FAST-PAGE-MODE (FPM) or Extended Data-Out

(EDO) PAGE MODE access cycles

· Serial presence-detect (SPD)

OPTIONS

MARKING

· Package

100-pin DIMM (gold)

· Timing

50ns access

-5*

60ns access

-6

· Access Cycles

FAST PAGE MODE

None

EDO PAGE MODE

*EDO version only

PIN ASSIGNMENT (Front View)

100-Pin DIMM

PIN

FRONT

PIN

FRONT

PIN

BACK

PIN

BACK

DQ0

DNU

DQ8

DNU

DQ1

WE#

DQ9

OE#

DQ2

RAS0#

DQ10

RAS1#

DQ3

RAS2#

DQ11

RAS3#

DQ4

DQ12

DQ5

DQ13

DQ6

DQ14

DQ7

DQ15

CAS0#

CAS1#

CAS2#

CAS3#

DQ16

DQ24

DQ17

DQ25

DQ18

DQ26

DQ19

DQ27

NC (A10)

DQ20

NC (A11)

DQ28

NC (A12)

DQ21

NC (A13)

DQ29

DQ22

DQ30

DQ23

DQ31

DNU

RFU

SDA

DNU

SA0

RFU

SCL

RFU

SA1

DNU

100

SA2

KEY TIMING PARAMETERS

EDO Operating Mode

SPEED

RAC

CAC

CAS

-5

84ns

50ns

20ns

25ns

15ns

8ns

-6

104ns

60ns

25ns

30ns

15ns

10ns

FPM Operating Mode

SPEED

RAC

CAC

-6

110ns

60ns

35ns

30ns

15ns

40ns

NOTE: Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

DRAM
MODULE

MT2LD132U(X), MT4LD232U(X)

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html

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EDO PAGE MODE

EDO PAGE MODE, designated by the "X" option, is an

accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(

CP) to occur without the output data going invalid. This

elimination of CAS# output control provides for pipelined
READs.

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of
CAS#. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid after CAS#
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. (Refer to the 1 Meg x 16 [MT4LC1M16E5]
DRAM data sheet for additional information on EDO
functionality.)

REFRESH

Memory cell data is retained in its correct state by main-

taining power and executing any RAS# cycle (READ,
WRITE) or RAS# REFRESH cycle (RAS#-ONLY, CBR or
HIDDEN) so that all combinations of RAS# addresses are
executed at least every

REF, regardless of sequence. The

CBR REFRESH cycle will invoke the internal refresh counter
for automatic RAS# addressing.

STANDBY

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time.

SERIAL PRESENCE-DETECT OPERATION

This module family incorporates serial presence-detect

(SPD). The SPD function is implemented using a 2,048-bit
EEPROM. This nonvolatile storage device contains 256
bytes. The first 128 bytes can be programmed by Micron to
identify the module type and various DRAM organizations
and timing parameters. The remaining 128 bytes of storage
are available for use by the customer. System READ/
WRITE operations between the master (system logic) and
the slave EEPROM device (DIMM) occur via a standard IIC
bus using the DIMM's SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.

PART NUMBERS

EDO Operating Mode

PART NUMBER

CONFIGURATION

SPEED

MT2LD132UG-5 X

1 Meg x 32

50ns

MT2LD132UG-6 X

1 Meg x 32

60ns

MT4LD232UG-5 X

2 Meg x 32

50ns

MT4LD232UG-6 X

2 Meg x 32

60ns

FPM Operating Mode

PART NUMBER

CONFIGURATION

SPEED

MT2LD132UG-6

1 Meg x 32

60ns

MT4LD232UG-6

2 Meg x 32

60ns

GENERAL DESCRIPTION

The MT2LD132U(X) and MT4LD232U(X) are randomly

accessed 4MB and 8MB memories organized in a x32 con-
figuration. They are specially processed to operate from 3V
to 3.6V for low-voltage memory systems.

During READ or WRITE cycles, each bit is uniquely

addressed through the 20 address bits which are entered
ten bits (A0 -A9) at a time. RAS# is used to latch the first ten
bits and CAS# the latter ten bits.

READ and WRITE cycles are selected with the WE#

input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. If WE# goes LOW prior to
CAS# going LOW, the output pin(s) remain open (High-Z)
until the next CAS# cycle.

FAST PAGE MODE

FAST-PAGE-MODE operations allow faster data opera-

tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.

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SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during SCL

LOW. SDA state changes during SCL HIGH are reserved
for indicating start and stop conditions (Figures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition, which

is a HIGH-to-LOW transition of SDA when SCL is HIGH.
The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any
command until this condition has been met.

SPD STOP CONDITION

All communications are terminated by a stop condition,

which is a LOW-to-HIGH transition of SDA when SCL is
HIGH. The stop condition is also used to place the SPD
device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indicate

successful data transfers. The transmitting device, either
master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the
SDA line LOW to acknowledge that it received the eight bits
of data (Figure 3).

The SPD device will always respond with an acknowl-

edge after recognition of a start condition and its slave
address. If both the device and a WRITE operation have
been selected, the SPD device will respond with an ac-
knowledge after the receipt of each subsequent eight-bit
word. In the read mode the SPD device will transmit eight
bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the slave
will terminate further data transmissions and await the
stop condition to return to standby power mode.

Figure 3

ACKNOWLEDGE RESPONSE FROM RECEIVER

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

Figure 2

DEFINITION OF START AND STOP

SCL

SDA

START
BIT

STOP
BIT

Figure 1

DATA VALIDITY

SCL

SDA

DATA STABLE

DATA
CHANGE

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SERIAL PRESENCE-DETECT MATRIX

BYTE

DESCRIPTION

ENTRY (VERSION)

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

HEX

NUMBER OF BYTES USED BY MICRON

128

TOTAL NUMBER OF SPD MEMORY BYTES

256

MEMORY TYPE

FAST PAGE MODE

EDO PAGE MODE

NUMBER OF ROW ADDRESSES

NUMBER OF COLUMN ADDRESSES

NUMBER OF BANKS

1 (4MB)

2 (8MB)

MODULE DATA WIDTH

x32

MODULE DATA WIDTH (continued)

MODULE VOLTAGE INTERFACE LEVELS

LVTTL

RAS# ACCESS TIME (

RAC)

50ns (-5)

60ns (-6)

CAS# ACCESS TIME (

CAC)

15ns

MODULE CONFIGURATION TYPE

NONPARITY

REFRESH RATE/TYPE 15.6

NORMAL

DRAM WIDTH (PRIMARY DRAM)

x16

ERROR CHECKING DRAM DATA WIDTH

NONE

15-61

RESERVED

SPD REVISION

REV. 0

CHECKSUM FOR BYTES 0-62

4MB -5 (EDO)

4MB -6 (EDO)

4MB -6 (FPM)

8MB -5 (EDO)

8MB -6 (EDO)

8MB -6 (FPM)

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71

MANUFACTURER'S JEDEC CODE (CONT.)

MANUFACTURING LOCATION

73-90

MODULE PART NUMBER (ASCII)

PCB IDENTIFICATION CODE

IDENTIFICATION CODE (CONT.)

YEAR OF MANUFACTURE IN BCD

WEEK OF MANUFACTURE IN BCD

95-98

MODULE SERIAL NUMBER

99-125

MANUFACTURE SPECIFIC DATA (RSVD)

NOTE:

1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.

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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.5

0.8

INPUT LEAKAGE CURRENT:

RAS0#-RAS3#

-2

Any input 0V

+ 0.3V

A0-A9, WE#, OE#

-8

(All other pins not under test = 0V)

CAS0#-CAS3#

-4

OUTPUT LEAKAGE CURRENT:

DQ0-DQ31

-10

DQ is disabled; 0V

OUT

+ 0.3V

OUTPUT LEVELS:

2.4

Output High Voltage (I

OUT

= -2mA)

Output Low Voltage (I

OUT

= 2mA)

0.4

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Supply Relative to V

.......... -1V to +4.6V

Voltage on Inputs or I/O Pins

Relative to V

................................................ -1V to +4.6V

Operating Temperature, T

(ambient) .......... 0

C to +70

Storage Temperature (plastic) .................... -55

C to +125

Power Dissipation ............................................................. 4W

*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

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MAX

CAPACITANCE

PARAMETER

SYMBOL

4MB

8MB

UNITS

NOTES

Input Capacitance: A0-A9

Input Capacitance: WE#, OE#

Input Capacitance: CAS0#-CAS3#

Input Capacitance: RAS0#-RAS3#, SCL, SA0-SA2

Input/Output Capacitance: DQ0-DQ31, SDA

OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 5, 6) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

SIZE

-5*

-6

UNITS

NOTES

STANDBY CURRENT: TTL

4MB

(RAS# = CAS# = V

)

8MB

STANDBY CURRENT: CMOS

4MB

(RAS# = CAS# = V

- 0.2V)

8MB

OPERATING CURRENT: Random READ/WRITE;

4MB

360

340

3, 22

Average power supply current;

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

8MB

362

342

OPERATING CURRENT: FAST PAGE MODE;
Average power supply current;

4MB

180

3, 22

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN];

8MB

182

CP,

ASC = 10ns)

OPERATING CURRENT: EDO PAGE MODE;

4MB

280

260

3, 22

Average power supply current;

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

(X only)

8MB

282

262

REFRESH CURRENT: RAS#-ONLY;

4MB

360

340

Average power supply current;

3, 22

(RAS# cycling, CAS# = V

RC =

RC [MIN])

8MB

362

342

REFRESH CURRENT: CBR;

4MB

360

340

Average power supply current;

3, 4

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

8MB

362

342

* EDO version only

MAX

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FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

-6

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Column address to WE# delay time

AWD

Access time from CAS#

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

CAS# to WE# delay time

CWD

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output disable

Output enable

OE# hold time from WE# during READ-MODIFY-WRITE cycle

OEH

Output buffer turn-off delay

OFF

17, 24

OE# setup prior to RAS# during HIDDEN REFRESH cycle

ORD

FAST-PAGE-MODE READ or WRITE cycle time

PRWC

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width

(

FAST PAGE MODE

)

RASP

125,000

Random READ or WRITE cycle time

110

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FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

-6

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

RAS# to CAS# delay time

RCD

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period (1,024 cycles)

REF

RAS# precharge time

RAS# to CAS# precharge time

RPC

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

READ-WRITE cycle time

RWC

155

RAS# to WE# delay time

RWD

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

WRITE command pulse width

WE# hold time (CBR Refresh)

WRH

WE# setup time (CBR Refresh)

WRP

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EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address setup to CAS# precharge

ACH

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Column address to WE# delay time

AWD

Access time from CAS#

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

Data output hold after next CAS# LOW

COH

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

CAS# to WE# delay time

CWD

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output disable

Output enable

OE# hold time from WE# during

OEH

READ-MODIFY-WRITE cycle

OE# HIGH hold from CAS# HIGH

OEHC

OE# HIGH pulse width

OEP

OE# LOW to CAS# HIGH setup time

OES

Output buffer turn-off delay

OFF

17, 24

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EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

OE# setup prior to RAS#

ORD

during HIDDEN REFRESH cycle

EDO-PAGE-MODE READ or WRITE cycle time

EDO-PAGE-MODE READ-WRITE cycle time

PRWC

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width (EDO PAGE MODE)

RASP

125,000

Random READ or WRITE cycle time

104

RAS# to CAS# delay time

RCD

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period (1,024 cycles)

REF

RAS# precharge time

RAS# to CAS# precharge time

RPC

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

READ-WRITE cycle time

RWC

116

140

RAS# to WE# delay time

RWD

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

Output disable delay from WE#

WHZ

WRITE command pulse width

WE# pulse to disable at CAS# HIGH

WPZ

WE# hold time (CBR Refresh)

WRH

WE# setup time (CBR Refresh)

WRP

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SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

Time the bus must be free before a new transition can start

BUF

4.7

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

Start condition hold time

HD:STA

Clock HIGH period

HIGH

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

SDA and SCL rise time

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

Stop condition setup time

SU:STO

4.7

WRITE cycle time

WRC

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

0.7 V

0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

STANDBY CURRENT:

SCL = SDA = V

- 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT:

SCL clock frequency = 100 KHz

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NOTES

1. All voltages referenced to V

2. This parameter is sampled. V

= +3.3V; f = 1 MHz.

3. I

is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle
time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate

cycle time at which proper operation over the full
temperature range is ensured.

6. An initial pause of 100

s is required after power-up,

followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the

REF refresh

requirement is exceeded.

7. AC characteristics assume

T = 5ns for FPM and

T = 2.5ns for EDO.

8. V

(MIN) and V

(MAX) are reference levels for

measuring timing of input signals. Transition times
are measured between V

and V

(or between V

and V

9. In addition to meeting the transition rate specifica-

tion, all input signals must transit between V

and

(or between V

and V

) in a monotonic manner.

10. If CAS# = V

, data output is High-Z.

11. If CAS# = V

, data output may contain data from the

last valid READ cycle.

12. Measured with a load equivalent to two TTL gates

and 100pF and V

= 0.8V and V

= 2V.

13. If CAS# is LOW at the falling edge of RAS#, Q will be

maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for

CP.

14. The

RCD (MAX) limit is no longer specified.

RCD

(MAX) was specified as a reference point only. If

RCD was greater than the specified

RCD (MAX)

limit, then access time was controlled exclusively by

CAC (

RAC [MIN] no longer applied). With or

without the

RCD (MAX) limit,

AA and

CAC must

always be met.

15. The

RAD (MAX) limit is no longer specified.

RAD

(MAX) was specified as a reference point only. If

RAD was greater than the specified

RAD (MAX)

limit, then access time was controlled exclusively by

AA (

RAC and

CAC no longer applied). With or

without the

RAD (MAX) limit,

AA,

RAC and

CAC

must always be met.

16. Either

RCH or

RRH must be satisfied for a READ

cycle.

17.

OFF (MAX) defines the time at which the output

achieves the open circuit condition and is not
referenced to V

or V

18. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles and WE# leading edge
in LATE WRITE or READ-MODIFY-WRITE cycles.

19. If OE# is tied permanently LOW, LATE WRITE or

READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted. Additionally, with
EDO, WE# must be pulsed during CAS# HIGH time
in order to place I/O buffers in High-Z.

20. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.

21. The 3ns minimum is a parameter guaranteed by

design.

22. Column address changed once each cycle.
23. 4MB module values will be half of those shown.
24. With the FPM option,

OFF is determined by the first

RAS# or CAS# signal to transition HIGH. In compari-
son,

OFF on an EDO option is determined by the

latter of the RAS# and CAS# signals to transition
HIGH.

25. Applies to both FPM and EDO operating modes.
26. All other inputs at 0.2V or V

- 0.2V.

27.

WCS,

RWD,

AWD and

CWD are not restrictive

operating parameters.

WCS applies to EARLY

WRITE cycles.

RWD,

AWD and

CWD apply to

READ-MODIFY-WRITE cycles. If

WCS

(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit throughout
the entire cycle. If

WCS <

WCS (MIN) and

RWD

RWD (MIN),

AWD

AWD (MIN) and

CWD

CWD (MIN), the cycle is a READ-MODIFY-WRITE

and the data output will contain data read from the
selected cell. If neither of the above conditions is met,
the state of data-out is indeterminate. OE# held HIGH
and WE# taken LOW after CAS# goes LOW result in
a LATE WRITE (OE#-controlled) cycle.

WCS,

RWD,

CWD and

AWD are not applicable in a LATE

WRITE cycle.

28. LATE WRITE and READ-MODIFY-WRITE cycles

must have both

OD and

OEH met (OE# HIGH

during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE cycle.
The DQs will provide the previously read data if
CAS# remains LOW and OE# is taken back LOW
after

OEH is met. If CAS# goes HIGH prior to OE#

going back LOW, the DQs will remain open.

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

READ CYCLE

,,,

tRRH

,,,,

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tOFF

tRCH

ROW

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tRSH

tCSH

tRP

tRC

tRAS

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

,,,

t OD

t OE

OE#

V
V

IH
IL

COLUMN

,,,

WE#

CASL#/CASH#

NOTE 1

tACH

DON'T CARE

UNDEFINED

,,,

,,,,

NOTE: 1. For EDO,

OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM,

OFF is referenced from rising edge of RAS# or

CAS#, whichever occurs first.

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAC

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CRP

CSH (EDO)

CSH (FPM)

OD (EDO)

OD (FPM)

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF (EDO)

OFF (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RAS

10,000

RC (EDO)

104

RC (FPM)

110

RCD (EDO)

RCD (FPM)

RCH

RCS

RRH

RSH

*EDO version only

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

EARLY WRITE CYCLE

DON'T CARE

UNDEFINED

,,,

V
V

IH
IL

,,,

VALID DATA

ROW

COLUMN

ROW

tDS

tWP

tWCH

tWCS

tWCR

tRWL

tCWL

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCAS

tRSH

tCSH

tRCD

tCRP

tRAS

tRC

tRP

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

,,,

tDH

WE#

CASL#/CASH#

tACH

,,,

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAD (EDO)

RAH

RAS

10,000

RC (FPM)

110

RC (EDO)

104

RCD (FPM)

RCD (EDO)

RSH

RWL

WCH

WCR

WCS

WP (FPM)

WP (EDO)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAH

CAS (FPM)

10,000

CAS (EDO)

10,000

CRP

CSH (FPM)

CSH (EDO)

CWL (FPM)

CWL (EDO)

RAD (FPM)

*EDO version only

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

FAST PAGE MODE
TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CPA

CRP

CSH

,,,

,,,,

,,,

VALID

DATA

VALID

DATA

VALID

DATA

,,,

COLUMN

ROW

DON'T CARE

UNDEFINED

tRCS

tCAH

tASC

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRCH

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tRAC

tAA

tCLZ

tOE

tOD

tOE

tOD

tOE

tOD

OPEN

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tCAS

WE#

CASL#/CASH#

FAST-PAGE-MODE READ CYCLE

-6

SYMBOL

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

EDO-PAGE-MODE READ CYCLE

WE#

ACH

,,,

VALID

DATA

VALID

DATA

VALID

DATA

,,,

COLUMN

ROW

DON'T CARE

UNDEFINED

tOD

tCAH

tASC

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tRAD

tRAH

tRAD

tASR

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tCAC

tCPA

tAA

tCAC

tRAC

tAA

tCLZ

tOE

tOD

tOE

tOD

OPEN

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

RAS#

OE#

CASL#/CASH#

tCOH

tOEP

tOEHC

tOES

tCAS

ACH

,,,

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

COH

CPA

CRP

CSH

OEHC

OEP

OES

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

FAST/EDO-PAGE-MODE EARLY WRITE CYCLE

,,,

tDS

tDH

tDS

tDH

tDS

tDH

tWCR

VALID DATA

tRWL

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tCAH

tASC

tCAH

tASC

tCAH

tASC

tRAH

tASR

tRAD

tAR

COLUMN

ROW

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

V
V

IH
IL

CASL#/CASH#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

V
V

IH
IL

V
V

IOH
IOL

RAS#

OE#

V
V

IH
IL

,,,

,,,,

,,,

,,,,

,,,

DON'T CARE

UNDEFINED

tACH

tCAS

,,,

ACH

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

PC (FPM)

RAD (EDO)

RAD (FPM)

RAH

RASP

125,000

RCD (EDO)

RCD (FPM)

RSH

RWL

WCH

WCR

WCS

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CRP

CSH (EDO)

CSH (FPM)

CWL (EDO)

CWL (FPM)

PC (EDO)

*EDO version only

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

,,,

VALID D

OUT

VALID D

ROW

,,,

COLUMN

ROW

,,,

,,,,

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OPEN

tOE

tOD

tCAC

tRAC

tAA

tCLZ

tDS

tDH

tAWD

tWP

tRWL

tCWL

tCWD

tRWD

tRCS

tASC

tCAH

tAR

tASR

tRAD

tCRP

tRCD

tCAS

tRSH

tCSH

tRAS

tRWC

tRP

tRAH

OE#

tOEH

,,,

WE#

tACH

CAS#

DON'T CARE

UNDEFINED

,,,,

OD (FPM)

OEH (EDO)

OEH (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RAS

10,000

RCD (EDO)

RCD (FPM)

RCS

RSH

RWC (EDO)

116

140

RWC (FPM)

155

RWD (EDO)

RWD (FPM)

RWL

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

AWD

CAC

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CRP

CSH (EDO)

CSH (FPM)

CWD (EDO)

CWD (FPM)

CWL (EDO)

CWL (FPM)

OD (EDO)

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

*EDO version only

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

FAST/EDO-PAGE-MODE READ-WRITE CYCLE

(LATE WRITE and READ-MODIFY-WRITE cycles)

,,,

DON'T CARE

UNDEFINED

,,,

tOE

tOD

tOE

tOD

tOE

OPEN

D OUT

VALID

D IN

VALID

D OUT

VALID

D IN

VALID

D OUT

VALID

D IN

VALID

OPEN

tDH

tDS

tAA

tCPA

tCLZ

tCAC

tDH

tDS

tAA

tCPA

tCLZ

tCAC

tDH

tDS

tAA

tCLZ

tCAC

tRAC

tWP

tCWL

tRWL

tCWD

tAWD

tWP

tCWL

tCWD

tAWD

tWP

tCWL

tCWD

tAWD

tRCS

tRWD

tASR

tRAH

tASC

tRAD

tAR

tCAH

tASC

tCAH

tASC

tCAH

tCP

tRSH

tCP

tRP

tRASP

tCP

tRCD

tCSH

t PC

tCRP

ROW

COLUMN

ROW

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

V
V

IH
IL

RAS#

OE#

tPRWC

OEH

,,,

tCAS

WE#

CASL#/CASH#

NOTE 1

,,,

NOTE: 1.

PC is for LATE WRITE cycles only.

*EDO version only

OD (FPM)

OEH (EDO)

OEH (FPM)

PC (EDO)

PC (FPM)

PRWC (EDO)

PRWC (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RASP

125,000

RCD (EDO)

RCD (FPM)

RCS

RSH

RWD (EDO)

RWD (FPM)

RWL

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

AWD

CAC

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CPA

CRP

CSH (EDO)

CSH (FPM)

CWD (EDO)

CWD (FPM)

CWL (EDO)

CWL (FPM)

OD (EDO)

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

V
V

IH
IL

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

t RASP

t RP

ROW

COLUMN (A)

COLUMN (N)

ROW

V
V

IH
IL

OE#

V
V

IOH
IOL

tCRP

t CSH

t CAS

t RCD

tASR

t RAH

tRAD

t ASC

tAR

t CAH

t ASC

t CAH

t ASC

t CAH

t CP

t RSH

VALID D

,,,

t RCS

t RCH

t WCS

tOE

VALID

OUT

VALID D

OUT

t WHZ

tCAC

tCPA

tAA

tCAC

tAA

OPEN

tPC

RAC

tCOH

t WCH

t DS

t DH

tPC

COLUMN (B)

t ACH

CASL#/CASH#

t CAS

t CP

DON'T CARE

UNDEFINED

,,,

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RSH

WCH

WCS

WHZ

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

CAH

CAS

10,000

COH

CPA

CRP

CSH

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

ROW

VALID

DATA

VALID DATA

,,,

OPEN

tCRP

tRCD

tCAS

tRSH

tRASP

tRP

tPC

tASC

tCAH

tAR

tASR

tRAD

tRAH

tWCS

tWP

tRWL

tRCS

tDH

tDS

tCAC

t OFF

V
V

IH
IL

CASL#/CASH#

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

V
V

OH
OL

WE#

V
V

IH
IL

,,,

tCSH

,,,

COLUMN

tCP

tASC

tCAH

tCWL

tWCH

t CLZ

tAA

RAC

DON'T CARE

UNDEFINED

NOTE 1

OE#

V
V

IH
IL

ROW

COLUMN

tCAS

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

NOTE: 1. Do not drive data prior to tristate.

-6

SYMBOL

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCS

RSH

RWL

WCH

WCS

FAST PAGE MODE
TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

CWL

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

EDO READ CYCLE

(with WE#-controlled disable)

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAC

RAD

RAH

RCD

RCH

RCS

WHZ

WPZ

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

,,,,

,,,

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tRCH

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tCSH

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

,,,,

,,,

t OD

t OE

OE#

V
V

IH
IL

COLUMN

,,,

,,,,

WE#

tWHZ

tWPZ

tCP

tASC

tRCS

COLUMN

tCLZ

CASL#/CASH#

DON'T CARE

UNDEFINED

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

RC (FPM)

110

RC (EDO)

104

RPC (FPM)

RPC (EDO)

WRH

WRP

RAS#-ONLY REFRESH CYCLE

,,,

,,,,

,,,

ROW

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

tRC

tRAS

tRP

tCRP

tASR

tRAH

ROW

OPEN

V
V

OH
OL

tRPC

WE#

V
V

IH
IL

,,,

,,,,

,,,

,,,,

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASR

CHR

CRP

CSR

RAH

RAS

10,000

*EDO version only

CBR REFRESH CYCLE

(Addresses = DON'T CARE)

tRP

V
V

IH
IL

RAS#

tRAS

OPEN

tCHR

tCSR

V
V

IH
IL

V
V

OH
OL

CAS#

tRP

tRAS

tRPC

tCSR

tRPC

tCHR

tCP

V
V

IH
IL

tWRP

tWRH

,,,

WE#

tWRP

tWRH

DON'T CARE

UNDEFINED

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

HIDDEN REFRESH CYCLE

20, 25

(WE# = HIGH)

,,,

DON'T CARE

UNDEFINED

tCLZ

tOFF

,,,

OPEN

VALID DATA

OPEN

COLUMN

ROW

tCAC

tRAC

tAA

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCRP

tRCD

tRSH

tRAS

tRC

tRP

tCHR

tRAS

DQx

V
V

IOH
IOL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

RAS#

,,,,

V
V

IH
IL

tOE

tOD

OE#

tORD

CASL#/CASH#

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

OFF (EDO)

ORD

RAC

RAD (FPM)

RAD (EDO)

RAH

RAS

10,000

RC (FPM)

110

RC (EDO)

104

RCD (FPM)

RCD (EDO)

RSH

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CHR

CLZ (FPM)

CLZ (EDO)

CRP

OD (FPM)

OD (EDO)

OFF (FPM)

*EDO version only

1, 2 Meg x 32 DRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM81.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2 MEG x 32

DRAM DIMMs

OBSOLETE

.350 (8.89)

MAX

.054 (1.37)
.046 (1.17)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

.079 (2.00) R

(2X)

PIN 1

.250 (6.35) TYP

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.039 (1.00) R(2X)

PIN 50

2.850 (72.39)

1.005 (25.53)

.995 (25.27)

3.557 (90.34)
3.545 (90.04)

.128 (3.25)
.118 (3.00)

(2X)

NOTE:

1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

100-PIN DIMM

DF-1 (4MB)

100-PIN DIMM

DF-2 (8MB)

.200 (5.08)

MAX

.054 (1.37)
.046 (1.17)

1.005 (25.53)

.995 (25.27)

.700 (17.78)

TYP

.118 (3.00)

(2X)

.118 (3.00) TYP

.079 (2.00) R

(2X)

3.557 (90.34)
3.545 (90.04)

PIN 1

.250 (6.35) TYP

.050 (1.27)

TYP

.118 (3.00)

TYP

.039 (1.00)

TYP

.039 (1.00) R(2X)

PIN 50

2.850 (72.39)

.128 (3.25)
.118 (3.00)

(2X)

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