1, 2, 4 Meg x 32 DRAM SODIMMs

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DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

SMALL-OUTLINE
DRAM MODULE

PIN ASSIGNMENT (Front View)

72-Pin Small-Outline DIMM

FEATURES

· JEDEC pinout in a 72-pin, small-outline, dual in-line

memory module (DIMM)

· 4MB (1 Meg x 32), 8MB (2 Meg x 32) and

16MB (4 Meg x 32)

· High-performance CMOS silicon-gate process
· Single +3.3V

0.3V power supply

· All inputs, outputs and clocks are TTL-compatible
· Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

(CBR) and HIDDEN; optional self refresh (S)

· 1,024-cycle refresh distributed across 16ms (4MB and

8MB) or 2,048-cycle refresh distributed across 32ms
(16MB) or self refresh distributed across 128ms

· FAST PAGE MODE (FPM) or Extended Data-Out

(EDO) PAGE MODE access cycles

OPTIONS

MARKING

· Package

72 -pin Small-Outline DIMM (gold)

· Timing

50ns access

-5*

60ns access

-6

· Access Cycles

FAST PAGE MODE

None

EDO PAGE MODE

· Refresh Rates

Standard Refresh

None

Self Refresh (128ms period)

*EDO version only

MT2LDT132H(X)(S), MT4LDT232H(X)(S),
MT8LDT432H(X)(S)

For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/mti/msp/html/datasheet.html

PIN

FRONT

PIN

BACK

PIN

FRONT

PIN

BACK

DQ0

DQ16

DQ17

DQ1

DQ2

CAS0#

DQ3

DQ4

CAS2#

CAS3#

DQ5

DQ6

CAS1#

RAS0#

DQ7

45 NC/RAS1#** 46

NC (A12)

PRD1

WE#

NC (A13)

DQ18

DQ19

DQ20

DQ21

DQ22

DQ23

A10

DQ24

DQ8

DQ9

DQ25

DQ26

DQ10

DQ11

DQ28

DQ27

DQ12

DQ13

DQ29

DQ14

DQ30

DQ31

NC (A11)

PRD2

PRD3

PRD4

33 NC/RAS3#** 34

RAS2#

PRD5

PRD6

DQ15

PRD7

**8MB version only

NOTE: Symbols in parentheses are not used on these modules but may be used

for other modules in this product family. They are for reference only.

KEY TIMING PARAMETERS

EDO Operating Mode (4MB and 8MB DIMMs)

SPEED

RAC

CAC

CAS

-5

84ns

50ns

20ns

25ns

15ns

8ns

-6

104ns

60ns

25ns

30ns

15ns

10ns

EDO Operating Mode (16MB DIMM)

SPEED

RAC

CAC

CAS

-5

84ns

50ns

20ns

25ns

13ns

8ns

-6

104ns

60ns

25ns

30ns

15ns

10ns

FPM Operating Mode

SPEED

RAC

CAC

-6

110ns

60ns

35ns

30ns

15ns

40ns

1, 2, 4 Meg x 32 DRAM SODIMMs

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DRAM SODIMMs

OBSOLETE

EDO PAGE MODE

EDO PAGE MODE, designated by the "X" version, is an

accelerated FAST-PAGE-MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(

CP) to occur without the output data going invalid. This

elimination of CAS# output control provides for pipelined
READs.

FAST-PAGE-MODE modules have traditionally turned

the output buffers off (High-Z) with the rising edge of
CAS#. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid or become
valid after CAS# goes HIGH, as long as RAS# and OE#
are held LOW. (Refer to the 1 Meg x 16 (MT4LC1M16E5)
DRAM data sheet for additional information on EDO
functionality.)

REFRESH

Memory cell data is retained in its correct state by main-

taining power and executing any RAS# cycle (READ,
WRITE) or RAS# refresh cycle (RAS#-ONLY, CBR or HID-
DEN) so that all combinations of RAS# addresses are ex-
ecuted at least every

REF, regardless of sequence. The CBR

REFRESH cycle will invoke the internal refresh counter for
automatic RAS# addressing.

An optional self refresh mode is also available. The "S"

option allows the user the choice of a fully static, low-power
data retention mode or a dynamic refresh mode at the
extended refresh period of 128ms. The optional self refresh
feature is initiated by performing a CBR REFRESH cycle
and holding RAS# LOW for the specified

RASS.

The self refresh mode is terminated by driving RAS#

HIGH for a minimum time of

RPS. This delay allows for the

completion of any internal refresh cycles that may be in
process at the time of the RAS# LOW-to-HIGH transition. If
the DRAM controller uses a distributed refresh sequence, a
burst refresh is not required upon exiting self refresh.
However, if the DRAM controller utilizes a RAS#-ONLY or
burst refresh sequence, all rows must be refreshed within
the average internal refresh rate, prior to the resumption of
normal operation.

STANDBY

Returning RAS# and CAS# HIGH terminates a memory

cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time.

PART NUMBERS

EDO Operating Mode

PART NUMBER

CONFIGURATION

REFRESH

MT2LDT132HG-x X

1 Meg x 32

Standard

MT2LDT132HG-x XS

1 Meg x 32

Self

MT4LDT232HG-x X

2 Meg x 32

Standard

MT4LDT232HG-x XS

2 Meg x 32

Self

MT8LDT432HG-x X

4 Meg x 32

Standard

MT8LDT432HG-x XS

4 Meg x 32

Self

x = speed

FPM Operating Mode

PART NUMBER

CONFIGURATION

REFRESH

MT2LDT132HG-x

1 Meg x 32

Standard

MT2LDT132HG-x S

1 Meg x 32

Self

MT4LDT232HG-x

2 Meg x 32

Standard

MT4LDT232HG-x S

2 Meg x 32

Self

MT8LDT432HG-x

4 Meg x 32

Standard

MT8LDT432HG-x S

4 Meg x 32

Self

x = speed

GENERAL DESCRIPTION

The MT2LDT132H(X)(S), MT4LDT232H(X)(S) and

MT8LDT432H(X)(S) are randomly accessed 4MB, 8MB and
16MB memories organized in a small-outline x32 configu-
ration. They are specially processed to operate from 3V to
3.6V for low-voltage memory systems.

During READ or WRITE cycles, each bit is uniquely

addressed through the address bits, which are entered 10/
11 bits (A0 -A9/A10) at a time. RAS# is used to latch the
first 10/11 bits and CAS# the latter 10/11 bits.

READ and WRITE cycles are selected with the WE#

input. A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. If WE# goes LOW prior to
CAS# going LOW, the output pin(s) remain open (High-Z)
until the next CAS# cycle.

FAST PAGE MODE

FAST-PAGE-MODE operations allow faster data opera-

tions (READ or WRITE) within a row-address-defined
page boundary. The FAST-PAGE-MODE cycle is always
initiated with a row address strobed in by RAS#, followed
by a column address strobed in by CAS#. Additional col-
umns may be accessed by providing valid column
addresses, strobing CAS# and holding RAS# LOW , thus
executing faster memory cycles. Returning RAS# HIGH
terminates the FAST-PAGE-MODE operation.

1, 2, 4 Meg x 32 DRAM SODIMMs

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1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

JEDEC-DEFINED
PRESENCE-DETECT MT2LDT132H (4MB)

SYMBOL

PIN

-5

-6

PRD1

PRD2

PRD3

PRD4

PRD5

PRD6

PRD7

JEDEC-DEFINED
PRESENCE-DETECT MT4LDT232H (8MB)

SYMBOL

PIN

-5

-6

PRD1

PRD2

PRD3

PRD4

PRD5

PRD6

PRD7

JEDEC-DEFINED
PRESENCE-DETECT MT8LDT432H (16MB)

SYMBOL

PIN

-5

-6

PRD1

PRD2

PRD3

PRD4

PRD5

PRD6

PRD7

*NC = Normal Refresh / V

= Self Refresh

1, 2, 4 Meg x 32 DRAM SODIMMs

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DM34.p65 Rev. 6/98

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1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

Supply Relative to V

.......... -1V to +4.6V

Voltage on Inputs or I/O Pins

Relative to V

................................................ -1V to +4.6V

Operating Temperature, T

(ambient) .......... 0

C to +70

Storage Temperature (plastic) .................... -55

C to +125

Power Dissipation ............................................................. 4W

*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the device.
This is a stress rating only, and functional operation of the
device at these or any other conditions above those indi-
cated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions
for extended periods may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V

0.3V)

PARAMETER/CONDITION

SYMBOL

SIZE

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

ALL

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

ALL

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

ALL

-0.5

0.8

INPUT LEAKAGE CURRENT:

4MB

-2

Any input 0V

+ 0.3V

CAS0#-CAS3#

8MB

-4

(All other pins not under test = 0V)

16MB

-4

4MB

-4

A0-A10, WE#

8MB

-8

16MB

-16

4MB

-2

RAS0#-RAS3#

8MB

-2

16MB

-8

OUTPUT LEAKAGE CURRENT:

4MB

-10

DQ is disabled; 0V

OUT

+ 0.3V

DQ0-DQ31

8MB

-20

16MB

-10

OUTPUT LEVELS:

ALL

2.4

Output High Voltage (I

OUT

= -2mA)

Output Low Voltage (I

OUT

= 2mA)

ALL

0.4

1, 2, 4 Meg x 32 DRAM SODIMMs

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DRAM SODIMMs

OBSOLETE

PARAMETER/CONDITION

SYMBOL

SIZE

-5*

-6

UNITS

NOTES

STANDBY CURRENT: TTL

4MB

(RAS# = CAS# = V

)

8MB

16MB

STANDBY CURRENT: CMOS

4MB

(RAS# = CAS# = V

- 0.2V)

8MB

16MB

4MB

(S only)

8MB

16MB

1.2

OPERATING CURRENT: Random READ/WRITE

4MB

360

340

Average power supply current

8MB

362

342

3, 22

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

16MB

880

800

OPERATING CURRENT: FAST PAGE MODE

4MB

340

Average power supply current

8MB

342

3, 22

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

16MB

640

OPERATING CURRENT: EDO PAGE MODE ("X" version only)

4MB

280

260

Average power supply current

(X only)

8MB

282

262

3, 22

(RAS# = V

, CAS#, address cycling:

PC =

PC [MIN])

16MB

880

800

REFRESH CURRENT: RAS#-ONLY

4MB

360

340

Average power supply current

8MB

362

342

3, 22

(RAS# cycling, CAS# = V

RC =

RC [MIN])

16MB

880

800

REFRESH CURRENT: CBR

4MB

360

340

Average power supply current

8MB

362

342

3, 4

(RAS#, CAS#, address cycling:

RC =

RC [MIN])

16MB

880

800

REFRESH CURRENT: SELF ("S" version only)

4MB

Average power supply current: CBR cycling with RAS#

RASS

8MB

1.2

3, 4

(MIN) and CAS# held LOW; WE# = V

- 0.2V; A0-A10,

(S only)

16MB

2.4

OE# and D

= V

- 0.2V or 0.2V (D

may be left open)

* EDO version only

OPERATING CONDITIONS AND MAXIMUM LIMITS

(Notes: 1, 5, 6) (V

= +3.3V

0.3V)

MAX

CAPACITANCE

PARAMETER

SYMBOL

4MB

8MB

16MB

UNITS

NOTES

Input Capacitance: A0-A10

Input Capacitance: WE#

Input Capacitance: RAS0#-RAS3#

Input Capacitance: CAS0#-CAS3#

Input/Output Capacitance: DQ0-DQ31

MAX

1, 2, 4 Meg x 32 DRAM SODIMMs

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1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

-6

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Access time from CAS#

CAC

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# LOW to "Don't Care" during Self Refresh

CHD

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output buffer turn-off delay

OFF

17, 21, 23

FAST-PAGE-MODE READ or WRITE cycle time

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

1, 2, 4 Meg x 32 DRAM SODIMMs

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DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - FAST PAGE MODE OPTION

-6

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

RAS# pulse width

RAS

10,000

RAS# pulse width (FAST PAGE MODE)

RASP

125,000

RAS# pulse width during Self Refresh

RASS

100

Random READ or WRITE cycle time

110

RAS# to CAS# delay time

RCD

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period (1,024 cycles) (4MB and 8MB)

REF

Refresh period (2,048 cycles) (16MB)

REF

Refresh period (1,024 and 2,048 cycles) "S" version

REF

128

RAS# precharge time

RAS# to CAS# precharge time

RPC

RAS# precharge time exiting Self Refresh

RPS

110

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

WRITE command pulse width

WE# hold time (CBR Refresh)

WRH

WE# setup time (CBR Refresh)

WRP

1, 2, 4 Meg x 32 DRAM SODIMMs

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1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from column address

Column-address setup to CAS# precharge

ACH

Column-address hold time (referenced to RAS#)

Column-address setup time

ASC

Row-address setup time

ASR

Access time from CAS#

CAC

13/15*

Column-address hold time

CAH

CAS# pulse width

CAS

10,000

CAS# LOW to "Don't Care" during Self Refresh

CHD

CAS# hold time (CBR Refresh)

CHR

CAS# to output in Low-Z

CLZ

Data output hold after next CAS# LOW

COH

CAS# precharge time

Access time from CAS# precharge

CPA

CAS# to RAS# precharge time

CRP

CAS# hold time

CSH

CAS# setup time (CBR Refresh)

CSR

WRITE command to CAS# lead time

CWL

Data-in hold time

Data-in setup time

Output buffer turn-off delay

OFF

17, 23

EDO-PAGE-MODE READ or WRITE cycle time

Access time from RAS#

RAC

RAS# to column-address delay time

RAD

Row-address hold time

RAH

RAS# pulse width

RAS

10,000

RAS# pulse width (EDO PAGE MODE)

RASP

125,000

RAS# pulse width during Self Refresh

RASS

100

Random READ or WRITE cycle time

104

RAS# to CAS# delay time

RCD

*4MB and 8MB DIMMs

1, 2, 4 Meg x 32 DRAM SODIMMs

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DM34.p65 Rev. 6/98

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1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 12, 19) (V

= +3.3V

0.3V)

AC CHARACTERISTICS - EDO PAGE MODE OPTION

-5

-6

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

READ command hold time (referenced to CAS#)

RCH

READ command setup time

RCS

Refresh period (1,024 cycles) (4MB and 8MB)

REF

Refresh period (2,048 cycles) (16MB)

REF

Refresh period (1,024 and 2,048 cycles) "S" version

REF

128

RAS# precharge time

RAS# to CAS# precharge time

RPC

RAS# precharge time exiting Self Refresh

RPS

105

READ command hold time (referenced to RAS#)

RRH

RAS# hold time

RSH

WRITE command to RAS# lead time

RWL

Transition time (rise or fall)

WRITE command hold time

WCH

WRITE command hold time (referenced to RAS#)

WCR

WE# command setup time

WCS

Output disable delay from WE#

WHZ

WRITE command pulse width

WE# pulse to disable at CAS# HIGH

WPZ

WE# hold time (CBR Refresh)

WRH

WE# setup time (CBR Refresh)

WRP

1, 2, 4 Meg x 32 DRAM SODIMMs

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1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

NOTES

1. All voltages referenced to V

2. This parameter is sampled. V

= +3.3V; f = 1 MHz.

3. I

is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle
time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate

cycle time at which proper operation over the full
temperature range is ensured.

6. An initial pause of 100

s is required after power-up,

followed by eight RAS# REFRESH cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper device
operation is ensured. The eight RAS# cycle wake-ups
should be repeated any time the

REF refresh

requirement is exceeded.

7. AC characteristics assume

T = 5ns for FPM and

T = 2.5ns for EDO.

8. V

(MIN) and V

(MAX) are reference levels for

measuring timing of input signals. Transition times
are measured between V

and V

(or between V

and V

9. In addition to meeting the transition rate specifica-

tion, all input signals must transit between V

and

(or between V

and V

) in a monotonic manner.

10. If CAS# = V

, data output is High-Z.

11. If CAS# = V

, data output may contain data from the

last valid READ cycle.

12. Measured with a load equivalent to two TTL gates

and 100pF, V

= 0.8V and V

= 2V.

13. If CAS# is LOW at the falling edge of RAS#, Q will be

maintained from the previous cycle. To initiate a new
cycle and clear the data-out buffer, CAS# must be
pulsed HIGH for

CP.

14. The

RCD (MAX) limit is no longer specified.

RCD

(MAX) was specified as a reference point only. If

RCD was greater than the specified

RCD (MAX)

limit, then access time was controlled exclusively by

CAC (

RAC [MIN] no longer applied). With or

without the

RCD (MAX) limit,

AA and

CAC must

always be met.

15. The

RAD (MAX) limit is no longer specified.

RAD

(MAX) was specified as a reference point only. If

RAD was greater than the specified

RAD (MAX)

limit, then access time was controlled exclusively by

AA (

RAC and

CAC no longer applied). With or

without the

RAD (MAX) limit,

AA,

RAC and

CAC

must always be met.

16. Either

RCH or

RRH must be satisfied for a READ

cycle.

17.

OFF (MAX) defines the time at which the output

achieves the open circuit condition and is not
referenced to V

or V

18. These parameters are referenced to CAS# leading

edge in EARLY WRITE cycles.

19. OE# is tied permanently LOW; LATE WRITE or

READ-MODIFY-WRITE operations are not permis-
sible and should not be attempted.

20. A HIDDEN REFRESH may also be performed after

a WRITE cycle. In this case, WE# = LOW and OE# =
HIGH.

21. The 3ns minimum is a parameter guaranteed by

design.

22. Column address changed once each cycle.
23. With the FPM option,

OFF is determined by the first

RAS# or CAS# signal to transition HIGH. In compari-
son,

OFF on an EDO option is determined by the

latter of the RAS# and CAS# signals to transition
HIGH.

24. Applies to both FPM and EDO operating modes.
25. All other inputs at 0.2V or V

- 0.2V.

26. "S" version only.
27. V

overshoot: V

(MAX) = V

+ 2V for a pulse

width

10ns, and the pulse width cannot be greater

than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for a pulse width

10ns, and the pulse

width cannot be greater than one third of the cycle
rate.

1, 2, 4 Meg x 32 DRAM SODIMMs

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DRAM SODIMMs

OBSOLETE

OFF (FPM)

RAC

RAD (EDO)

RAD (FPM)

RAH

RAS

10,000

RC (EDO)

104

RC (FPM)

110

RCD (EDO)

RCD (FPM)

RCH

RCS

RRH

RSH

READ CYCLE

,,,

tRRH

,,,

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tOFF

tRCH

ROW

tRCS

tASC

tACH

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tRSH

tCSH

tRP

tRC

tRAS

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

COLUMN

CAS#

WE#

NOTE 1

DON'T CARE

UNDEFINED

,,,

NOTE: 1. For EDO,

OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM,

OFF is referenced from rising edge of RAS# or

CAS#, whichever occurs first.

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAC

13/15**

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CLZ (EDO)

CLZ (FPM)

CRP

CSH (EDO)

CSH (FPM)

OFF (EDO)

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

*EDO version only
**4MB and 8MB DIMMs

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

EARLY WRITE CYCLE

DON'T CARE

UNDEFINED

,,,

V
V

IH
IL

,,,

VALID DATA

ROW

COLUMN

ROW

tDS

tWP

tWCH

tWCS

tWCR

tRWL

tCWL

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCAS

tRSH

tCSH

tRCD

tCRP

tRAS

tRC

tRP

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

IOH
IOL

RAS#

,,,

tDH

WE#

CAS#

tACH

,,,

,,,,

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAD (EDO)

RAH

RAS

10,000

RC (FPM)

110

RC (EDO)

104

RCD (FPM)

RCD (EDO)

RSH

RWL

WCH

WCR

WCS

WP (FPM)

WP (EDO)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAH

CAS (FPM)

10,000

CAS (EDO)

10,000

CRP

CSH (FPM)

CSH (EDO)

CWL (FPM)

CWL (EDO)

RAD (FPM)

*EDO version only

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

FAST PAGE MODE
TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CPA

CRP

CSH

FAST-PAGE-MODE READ CYCLE

,,,

VALID

DATA

VALID

DATA

VALID

DATA

,,,

COLUMN

ROW

tRCS

tCAH

tASC

tCP

tCAS

tRSH

tCP

tCAS

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tASR

tRCS

tRCH

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tCPA

tAA

tCLZ

tOFF

tCAC

tRAC

tAA

tCLZ

OPEN

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

V
V

IH
IL

V
V

IOH
IOL

RAS#

DON'T CARE

UNDEFINED

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

-6

SYMBOL

MIN

MAX

UNITS

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

CSH

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RRH

RSH

EDO-PAGE-MODE READ CYCLE

VALID

DATA

VALID

DATA

VALID

DATA

,,,

COLUMN

ROW

DON'T CARE

UNDEFINED

tCAH

tASC

tCP

tRSH

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

tCAH

tASC

tCAH

tASC

tAR

tRAH

tRAD

tACH

tASR

tRCS

tRRH

tRCH

tOFF

tCAC

tCPA

tAA

tCLZ

tCAC

tCPA

tAA

tCAC

tRAC

tAA

tCLZ

OPEN

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

V
V

OH
OL

RAS#

tCAS

CAS#

WE#

tCOH

,,,

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

13/15*

CAH

CAS

10,000

CLZ

COH

CPA

CRP

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

*4MB and 8MB DIMMs

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

FAST/EDO-PAGE-MODE EARLY WRITE CYCLE

,,,

tDS

tDH

tDS

tDH

tDS

tDH

tWCR

VALID DATA

tRWL

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tWP

tCWL
tWCH

tWCS

tCAH

tASC

tCAH

tASC

tCAH

tASC

tRAH

tASR

tRAD

tAR

COLUMN

ROW

tCP

tCAS

tRSH

tCP

tCAS

tCP

tCAS

tRCD

tCRP

tPC

tCSH

tRASP

tRP

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

V
V

IH
IL

V
V

IOH
IOL

RAS#

DON'T CARE

UNDEFINED

tACH

,,,

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

PC (FPM)

RAD (EDO)

RAD (FPM)

RAH

RASP

125,000

RCD (EDO)

RCD (FPM)

RSH

RWL

WCH

WCR

WCS

WP (EDO)

WP (FPM)

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH (EDO)

ASC

ASR

CAH

CAS (EDO)

10,000

CAS (FPM)

10,000

CRP

CSH (EDO)

CSH (FPM)

CWL (EDO)

CWL (FPM)

PC (EDO)

*EDO version only

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

V
V

IH
IL

V
V

IH
IL

RAS#

V
V

IH
IL

ADDR

V
V

IH
IL

WE#

t RASP

t RP

ROW

COLUMN (A)

COLUMN (N)

ROW

V
V

IOH
IOL

tCRP

t CSH

t CAS

t RCD

tASR

t RAH

tRAD

t ASC

tAR

t CAH

t ASC

t CAH

t ASC

t CAH

t CP

t RSH

VALID DATA

t RCS

t RCH

t WCS

VALID

DATA (B)

VALID DATA (A)

t WHZ

tCAC

tCPA

tAA

tCAC

tAA

OPEN

tPC

RAC

tCOH

t WCH

t DS

t DH

tPC

COLUMN (B)

t ACH

CAS#

t CAS

t CP

DON'T CARE

UNDEFINED

,,,

EDO-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ACH

ASC

ASR

CAC

13/15*

CAH

CAS

10,000

COH

CPA

CRP

CSH

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAC

RAD

RAH

RASP

125,000

RCD

RCH

RCS

RSH

WCH

WCS

WHZ

*4MB and 8MB DIMMs

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

FAST-PAGE-MODE READ EARLY WRITE CYCLE

(Pseudo READ-MODIFY-WRITE)

ROW

VALID

DATA

VALID DATA

,,,

OPEN

tCRP

tRCD

tCAS

tRSH

tRASP

tRP

tPC

tASC

tCAH

tAR

tASR

tRAD

tRAH

tWCS

tWP

tRWL

tRCS

tDH

tDS

tCAC

t OFF

V
V

IH
IL

CAS#

V
V

IH
IL

ADDR

V
V

IH
IL

RAS#

V
V

OH
OL

WE#

V
V

IH
IL

,,,

tCSH

,,,

COLUMN

tCP

tASC

tCAH

tCWL

tWCH

t CLZ

tAA

RAC

DON'T CARE

UNDEFINED

NOTE 1

ROW

COLUMN

tCAS

NOTE: 1. Do not drive data prior to tristate.

FAST PAGE MODE
TIMING PARAMETERS

-6

SYMBOL

MIN

MAX

UNITS

ASC

ASR

CAC

CAH

CAS

10,000

CLZ

CRP

CSH

CWL

-6

SYMBOL

MIN

MAX

UNITS

OFF

RAC

RAD

RAH

RASP

125,000

RCD

RCS

RSH

RWL

WCH

WCS

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

EDO READ CYCLE

(with WE#-controlled disable)

,,,

tCLZ

tCAC

tRAC

tAA

VALID DATA

OPEN

tRCH

tRCS

tASC

tRAH

tRAD

tAR

tCAH

tRCD

tCAS

tCSH

tCRP

tASR

ROW

OPEN

RAS#

V
V

IH
IL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

OH
OL

V
V

IH
IL

COLUMN

CAS#

WE#

tWHZ

tWPZ

tCP

tASC

tRCS

COLUMN

tCLZ

DON'T CARE

UNDEFINED

,,,

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

CSH

RAC

RAD

RAH

RCD

RCH

RCS

WHZ

WPZ

EDO PAGE MODE
TIMING PARAMETERS

-5

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

13/15*

CAH

CAS

10,000

CLZ

CRP

*4MB and 8MB DIMMs

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

RC (EDO)

104

RPC (FPM)

RPC (EDO)

WRH

WRP

RAS#-ONLY REFRESH CYCLE

,,,

,,,,

,,,

ROW

V
V

IH
IL

CAS

V
V

IH
IL

ADDR

V
V

IH
IL

RAS

tRC

tRAS

tRP

tCRP

tASR

tRAH

ROW

OPEN

V
V

OH
OL

tRPC

,,,

V
V

IH
IL

DON'T CARE

UNDEFINED

tWRH

tWRP

tWRH

tWRP

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASR

CRP

CSR

RAH

RAS

10,000

RC (FPM)

110

*EDO version only

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

NOTE: 1. Once

RASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode.

2. Once

RPS is satisfied, a complete burst of all rows should be executed.

SELF REFRESH CYCLE

24, 26

(Addresses = DON'T CARE)

V
V

IH
IL

RAS#

tRASS

OPEN

V
V

IH
IL

V
V

OH
OL

tRPC

tCHD

tRPS

tRPC

tRP

tCP

CAS#

,,,

WE#

V
V

IH
IL

tWRH

tWRP

,,,

,,,,

tWRH

tWRP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NOTE 1

tCSR

,,,,

,,,

tCP

NOTE 2

(

)

(

)

(

)

(

)

CBR REFRESH CYCLE

(Addresses = DON'T CARE)

tRP

V
V

IH
IL

RAS#

tRAS

OPEN

tCHR

tCSR

V
V

IH
IL

V
V

OH
OL

CAS#

tRP

tRAS

tRPC

tCSR

tRPC

tCHR

tCP

V
V

IH
IL

tWRP

tWRH

,,,

WE#

tWRP

tWRH

DON'T CARE

UNDEFINED

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

CHD

CHR

CSR

RAS

10,000

RASS

100

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RPC (FPM)

RPC (EDO)

RPS (FPM)

110

RPS (EDO)

105

WRH

WRP

*EDO version only

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

HIDDEN REFRESH CYCLE

20, 24

(WE# = HIGH)

DON'T CARE

UNDEFINED

tCLZ

tOFF

,,,

OPEN

VALID DATA

OPEN

COLUMN

ROW

tCAC

tRAC

tAA

tCAH

tASC

tRAH

tASR

tRAD

tAR

tCRP

tRCD

tRSH

tRAS

tRC

tRP

tCHR

tRAS

V
V

OH
OL

V
V

IH
IL

ADDR

V
V

IH
IL

V
V

IH
IL

RAS#

CAS#

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

RAC

RAD (FPM)

RAD (EDO)

RAH

RAS

10,000

RC (FPM)

110

RC (EDO)

104

RCD (FPM)

RCD (EDO)

RSH

FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS

-5*

-6

SYMBOL

MIN

MAX

MIN

MAX

UNITS

ASC

ASR

CAC

13/15**

CAH

CHR

CLZ (FPM)

CLZ (EDO)

CRP

OFF (FPM)

OFF (EDO)

*EDO version only
**4MB and 8MB DIMMs

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

NOTE:

1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

72-PIN SODIMM

DG-1 (1 Meg x 32)

72-PIN SODIMM

DG-2 (2 Meg x 32)

.150 (3.80)

MAX

.043 (1.10)
.035 (0.90)

PIN 1

.700 (17.78)

TYP

.071 (1.80)

(2X)

.071 (1.80) TYP

.050 (1.27)

TYP

.197 (5.00)

.040 (1.02)

TYP

.079 (2.00) R

(3X)

PIN 71 (PIN 72 on backside)

FRONT VIEW

.079 (2.00)

.125 (3.18)

1.750 (44.45)

2.034 (51.66)

1.005 (25.53)

.995 (25.27)

2.355 (59.82)
2.345 (59.56)

.100 (2.54)

MAX

.043 (1.10)
.035 (0.90)

1.005 (25.53)

.995 (25.27)

PIN 1

2.355 (59.82)
2.345 (59.56)

.700 (17.78)

TYP

.071 (1.80)

(2X)

.071 (1.80) TYP

1.750 (44.45)

.050 (1.27)

TYP

.197 (5.00)

.040 (1.02)

TYP

.079 (2.00) R

(3X)

PIN 71 (PIN 72 on backside)

FRONT VIEW

.079 (2.00)

.125 (3.18)

2.034 (51.66)

1, 2, 4 Meg x 32 DRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DM34.p65 Rev. 6/98

1998, Micron Technology, Inc.

1, 2, 4 MEG x 32

DRAM SODIMMs

OBSOLETE

NOTE:

1. All dimensions in inches (millimeters)

MAX

or typical where noted.

MIN

72-PIN SODIMM

DG-3 (4 Meg x 32)

.150 (3.80)

MAX

.043 (1.10)
.035 (0.90)

PIN 1

.700 (17.78)

TYP

.071 (1.80)

(2X)

.071 (1.80) TYP

1.750 (44.45)

.050 (1.27)

TYP

.197 (5.00)

.040 (1.02)

TYP

.079 (2.00) R

(3X)

PIN 71 (PIN 72 on backside)

FRONT VIEW

.079 (2.00)

.125 (3.18)

2.034 (51.66)

1.005 (25.53)

.995 (25.27)

2.355 (59.82)
2.345 (59.56)

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT2LDT132H-7X

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT2LDT132H-7X