Document Outline
- Features
- Options
- Key Timing Parameters
- Part Numbers
- Pin Assignment (Front View) 100-Pin DIMM
- General Desciption
- Fast Page Mode
- EDO Page Mode
- Refresh
- Standby
- Serial Presence-Detect Operation
- SDP Clock and Data Conventions
- SPD Start Condition
- SPD Stop Condition
- SPD Acknowledge
- Functional Block Diagrams
- MT2LDT432U (X) (16MB)
- MT4LDT832U (X) (32MB)
- Figure 1 Data Validity
- Figure 2 Definition of Start and Stop
- Figure 3 Acknowledge Response from Receiver
- Serial Presence-Detect Matrix
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- IDD Operating Conditions and Maximum Limits
- Capacitance
- Fast Page mode AC Electrical Characteristics
- Fast Page mode AC Electrical Characteristics
- EDOPage Mode AC Electrical Characteristics
- EDO Page Mode AC Electrical Characteristics
- Serial Presence-Detect EEPROM DC Operating Conditions
- Serial Presence-Detect EEPROM AC Electrical Characteristics
- Notes
- Read Cycle
- Early Write Cycle
- Fast-Page-Mode Read Cycle
- EDO-Page-Mode Read Cycle
- Fast/EDO-Page-Mode Early Write Cycle
- Read-Write Cycle
- Fast/EDO Page Mode Read-Write Cycle
- EDO-Page-Mode Read Early Write Cycle
- Fast-Page-Mode Read Early Write Cycle
- EDO Read Cycle
- RAS#-Only Refresh Cycle
- CBR Refresh Cycle
- Hidden Refresh Cycle
- SPD EEPROM
- 100-Pin DIMM DF-3 (16MB)
- 100-Pin DIMM DF-4 (32MB)
1
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FEATURES
JEDEC pinout in a 100-pin, dual in-line memory
module (DIMM)
16MB (4 Meg x 32) and 32MB (8 Meg x 32)
High-performance CMOS silicon-gate process
Single +3.3V 0.3V power supply
All inputs, outputs and clocks are TTL-compatible
4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
Serial presence-detect (SPD)
OPTIONS
MARKING
Package
100-pin DIMM (gold)
G
Timing
50ns access
-5
60ns access
-6
Access Cycles
FAST PAGE MODE
None
EDO PAGE MODE
X
PIN ASSIGNMENT (Front View)
100-Pin DIMM
(H-1; 16MB)
(H-2; 32MB)
PIN
FRONT
PIN
FRONT
PIN
BACK
PIN
BACK
1
V
SS
26
V
SS
51
V
SS
76
V
SS
2
DQ0
27
DNU
52
DQ8
77
DNU
3
DQ1
28
WE#
53
DQ9
78
OE#
4
DQ2
29
RAS0#
54
DQ10
79
RAS1#
5
DQ3
30
RAS2#
55
DQ11
80
RAS3#
6
V
DD
31
V
DD
56
V
DD
81
V
DD
7
DQ4
32
NC
57
DQ12
82
NC
8
DQ5
33
NC
58
DQ13
83
NC
9
DQ6
34
NC
59
DQ14
84
NC
10
DQ7
35
NC
60
DQ15
85
NC
11
CAS0#
36
V
SS
61
CAS1#
86
V
SS
12
V
SS
37
CAS2#
62
V
SS
87
CAS3#
13
A0
38
DQ16
63
A1
88
DQ24
14
A2
39
DQ17
64
A3
89
DQ25
15
A4
40
DQ18
65
A5
90
DQ26
16
A6
41
DQ19
66
A7
91
DQ27
17
A8
42
V
DD
67
A9
92
V
DD
18
A10
43
DQ20
68
A11
93
DQ28
19
NC (A12)
44
DQ21
69
NC (A13)
94
DQ29
20
NC
45
DQ22
70
NC
95
DQ30
21
V
DD
46
DQ23
71
V
DD
96
DQ31
22
DNU
47
V
SS
72
DNU
97
V
SS
23
RFU
48
SDA
73
DNU
98
SA0
24
RFU
49
SCL
74
RFU
99
SA1
25
DNU
50
V
DD
75
DNU
100
SA2
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-5
84ns
50ns
20ns
25ns
13ns
8ns
-6
104ns
60ns
25ns
30ns
15ns
10ns
FPM Operating Mode
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
-5
90ns
50ns
30ns
25ns
13ns
30ns
-6
110ns
60ns
35ns
30ns
15ns
40ns
NOTE: Symbols in parentheses are not used on these
modules but may be used for other modules in this
product family. They are for reference only.
DRAM
MODULE
MT2LDT432U (X), MT4LDT832U (X)
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/datasheets/datasheet.html
PART NUMBERS
EDO Operating Mode
PART NUMBER
CONFIGURATION
SPEED
MT2LDT432UG-5 X
4 Meg x 32
50ns
MT2LDT432UG-6 X
4 Meg x 32
60ns
MT4LDT832UG-5 X
8 Meg x 32
50ns
MT4LDT832UG-6 X
8 Meg x 32
60ns
FPM Operating Mode
PART NUMBER
CONFIGURATION
SPEED
MT2LDT432UG-5
4 Meg x 32
50ns
MT2LDT432UG-6
4 Meg x 32
60ns
MT4LDT832UG-5
8 Meg x 32
50ns
MT4LDT832UG-6
8 Meg x 32
60ns
2
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO operates as any DRAM READ or
FAST-PAGE-MODE READ, except data will be held
valid after CAS# goes HIGH, as long as RAS# and OE#
are held LOW and WE# is held HIGH. (Refer to the 4
Meg x 16 [MT4LC4M16R6] DRAM data sheet for
additional information on EDO functionality.)
REFRESH
Memory cell data is retained in its correct state by
maintaining power and executing any RAS# cycle
(READ, WRITE) or RAS# REFRESH cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS#
addresses are executed at least every
t
REF, regardless of
sequence. The CBR REFRESH cycle will invoke the
internal refresh counter for automatic RAS# address-
ing.
STANDBY
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM's SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
GENERAL DESCRIPTION
The MT2LDT432U (X) and MT4LDT832U (X) are
randomly accessed 16MB and 32MB memories orga-
nized in a x32 configuration. They are specially pro-
cessed to operate from 3V to 3.6V for low-voltage
memory systems.
During READ or WRITE cycles, each location is
uniquely addressed via the address bits. The row ad-
dress is latched by the RAS# signal, then the column
address is latched by the CAS# signal.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE oc-
curs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data outputs (Q) will remain
High-Z, regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data outputs prior to apply-
ing input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no
WRITE will occur, and the data outputs will drive read
data from the accessed location.
FAST PAGE MODE
FAST-PAGE-MODE operations allow faster data
operations (READ or WRITE) within a row-address-
defined page boundary. The FAST-PAGE-MODE cycle
is always initiated with a row address strobed in by
RAS#, followed by a column address strobed in by
CAS#. Additional columns may be accessed by provid-
ing valid column addresses, strobing CAS# and hold-
ing RAS# LOW, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST-PAGE-
MODE operation.
EDO PAGE MODE
EDO PAGE MODE, designated by the "X" option,
is an accelerated FAST-PAGE-MODE cycle. The pri-
mary advantage of EDO is the availability of data-out
even after CAS# goes back HIGH. EDO provides for
CAS# precharge time (
t
CP) to occur without the out-
put data going invalid. This elimination of CAS#
output control provides for pipelined READs.
3
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT2LDT432U (X) (16MB)
WE#
CASL#
CASH#
RAS#
OE#
A0-A11
U1
WE#
CASL#
CASH#
RAS#
OE#
DQ16-
DQ31
U2
CAS0#
CAS1#
RAS0#
OE#
CAS2#
CAS3#
RAS2#
WE#
A0-A11
12
12
12
16
16
32
DQ0-
DQ15
A0-A11
DQ0-DQ31
V
DD
V
SS
U1-U2
U1-U2
SPD
SCL
SDA
SA0
SA1 SA2
A0
A1
A2
U1-U2 = MT4LC4M16F5 FAST PAGE MODE
U1-U2 = MT4LC4M16R6 EDO PAGE MODE
DQn
Every DRAM DQ pin
10 ohms
4
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT832U (X) (32MB)
V
DD
V
SS
U1-U4
U1-U4
SPD
SCL
SDA
SA0
SA1
SA2
A0
A1
A2
U1-U4 = MT4LC4M16F5 FAST PAGE MODE
U1-U4 = MT4LC4M16R6 EDO PAGE MODE
DQn
Every DRAM DQ pin
10 ohms
A0-A11
U3
DQ16-
DQ31
U4
RAS1#
RAS3#
12
12
16
16
32
DQ0-
DQ15
A0-A11
DQ0-DQ31
WE#
CASL#
CASH#
RAS#
OE#
A0-A11
U1
DQ16-
DQ31
U2
CAS0#
CAS1#
RAS0#
OE#
CAS2#
CAS3#
RAS2#
12
12
16
16
32
DQ0-
DQ15
A0-A11
DQ0-DQ31
A0-A11
12
WE#
WE#
CASL#
CASH#
RAS#
OE#
WE#
CASL#
CASH#
RAS#
OE#
WE#
CASL#
CASH#
RAS#
OE#
5
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and
its slave address. If both the device and a WRITE
operation have been selected, the SPD device will re-
spond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode the SPD
device will transmit eight bits of data, release the SDA
line and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is
generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and
await the stop condition to return to standby power
mode.
Figure 3
Acknowledge Response From Receiver
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 2
Definition of Start and Stop
SCL
SDA
START
BIT
STOP
BIT
Figure 1
Data Validity
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
6
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
ENTRY (VERSION) BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
HEX
0
NUMBER OF BYTES USED BY MICRON
128
1
0
0
0
0
0
0
0
80
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
0
0
0
0
1
0
0
0
08
2
MEMORY TYPE
FAST PAGE MODE
0
0
0
0
0
0
0
1
01
EDO PAGE MODE
0
0
0
0
0
0
1
0
02
3
NUMBER OF ROW ADDRESSES
12
0
0
0
0
1
1
0
0
0C
4
NUMBER OF COLUMN ADDRESSES
10
0
0
0
0
1
0
1
0
0A
5
NUMBER OF BANKS
1 (16MB)
0
0
0
0
0
0
0
1
01
2 (32MB)
0
0
0
0
0
0
1
0
02
6
MODULE DATA WIDTH
x32
0
0
1
0
0
0
0
0
20
7
MODULE DATA WIDTH (continued)
0
0
0
0
0
0
0
0
0
00
8
MODULE VOLTAGE INTERFACE LEVELS
LVTTL
0
0
0
0
0
0
0
1
01
9
RAS# ACCESS TIME (
t
RAC)
50ns (-5)
0
0
1
1
0
0
1
0
32
60ns (-6)
0
0
1
1
1
1
0
0
3C
10
CAS# ACCESS TIME (
t
CAC)
13ns (-5)
0
0
0
0
1
1
0
1
0D
15ns (-6)
0
0
0
0
1
1
1
1
0F
11
MODULE CONFIGURATION TYPE
NONPARITY
0
0
0
0
0
0
0
0
00
12
REFRESH RATE/TYPE 15.6s
NORMAL
0
0
0
0
0
0
0
0
00
13
DRAM WIDTH (PRIMARY DRAM)
x16
0
0
0
1
0
0
0
0
10
14
ERROR CHECKING DRAM DATA WIDTH
NONE
0
0
0
0
0
0
0
0
00
15-61
RESERVED
0
0
0
0
0
0
0
0
00
62
SPD REVISION
REV. 0
0
0
0
0
0
0
0
0
00
63
CHECKSUM FOR BYTES 0-62
16MB -5 (EDO)
0
0
0
1
0
0
0
1
11
16MB -6 (EDO)
0
0
0
1
1
1
0
1
1D
16MB -5 (FPM)
0
0
0
1
0
0
0
0
10
16MB -6 (FPM)
0
0
0
1
1
1
0
0
1C
32MB -5 (EDO)
0
0
0
1
0
0
1
0
12
32MB -6 (EDO)
0
0
0
1
1
1
1
0
1E
32MB -5 (FPM)
0
0
0
1
0
0
0
1
11
32MB -6 (FPM)
0
0
0
1
1
1
0
1
1D
64
MANUFACTURER'S JEDEC ID CODE
MICRON
0
0
1
0
1
1
0
0
2C
65-71
MANUFACTURER'S JEDEC CODE (CONT.)
1
1
1
1
1
1
1
1
FF
72
MANUFACTURING LOCATION
0
0
0
0
0
0
0
1
01
0
0
0
0
0
0
1
0
02
0
0
0
0
0
0
1
1
03
0
0
0
0
0
1
0
0
04
73-90
MODULE PART NUMBER (ASCII)
x
x
x
x
x
x
x
x
xx
91
PCB IDENTIFICATION CODE
1
0
0
0
0
0
0
0
1
01
2
0
0
0
0
0
0
1
0
02
3
0
0
0
0
0
0
1
1
03
4
0
0
0
0
0
1
0
0
04
92
IDENTIFICATION CODE (CONT.)
0
0
0
0
0
0
0
0
0
00
93
YEAR OF MANUFACTURE IN BCD
x
x
x
x
x
x
x
x
xx
94
WEEK OF MANUFACTURE IN BCD
x
x
x
x
x
x
x
x
xx
95-98
MODULE SERIAL NUMBER
x
x
x
x
x
x
x
x
xx
99-125 MANUFACTURE SPECIFIC DATA (RSVD)
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.
7
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2
V
DD
+ 0.3
V
30
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-0.5
0.8
V
30
INPUT LEAKAGE CURRENT:
RAS0#-RAS3#
I
I
1
-2
2
A
Any input 0V V
IN
V
DD
+ 0.3V
A0-A11, WE#, OE#
I
I
2
-8
8
A
23
(All other pins not under test = 0V)
CAS0#-CAS3#
I
I
3
-4
4
A
23
OUTPUT LEAKAGE CURRENT:
DQ0-DQ31
I
OZ
-10
10
A
23
DQ is disabled; 0V V
OUT
V
DD
+ 0.3V
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -2mA)
Output Low Voltage (I
OUT
= 2mA)
V
OL
0.4
V
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
..................................... -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to V
SS
..................................... -1V to +4.6V
Operating Temperature, T
A
(ambient) .. 0C to +70C
Storage Temperature (plastic) ........... -55C to +125C
Power Dissipation ................................................... 4W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
8
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
I
CC
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
SIZE
-5
-6
UNITS NOTES
STANDBY CURRENT: TTL
I
CC
1
16MB
2
2
mA
(RAS# = CAS# = V
IH
)
32MB
4
4
STANDBY CURRENT: CMOS
I
CC
2
16MB
1
1
mA
26
(RAS# = CAS# = V
DD
- 0.2V)
32MB
2
2
OPERATING CURRENT: Random READ/WRITE;
16MB
350
330
mA
3, 22
Average power supply current;
I
CC
3
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
32MB
352
332
OPERATING CURRENT: FAST PAGE MODE;
Average power supply current;
I
CC
4
16MB
210
190
mA
3, 22
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN];
32MB
212
192
t
CP,
t
ASC = 10ns)
OPERATING CURRENT: EDO PAGE MODE;
16MB
310
250
mA
3, 22
Average power supply current;
I
CC
5
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
(X only)
32MB
312
252
REFRESH CURRENT: RAS#-ONLY;
16MB
350
330
Average power supply current;
I
CC
6
mA
3, 22
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
32MB
352
332
REFRESH CURRENT: CBR;
16MB
350
330
Average power supply current;
I
CC
7
mA
3, 4
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
32MB
352
332
MAX
CAPACITANCE
PARAMETER
SYMBOL 16MB
32MB UNITS NOTES
Input Capacitance: A0-A11
C
I
1
14
24
p F
2
Input Capacitance: WE#, OE#
C
I
2
18
32
p F
2
Input Capacitance: CAS0#-CAS3#
C
I
3
10
18
p F
2
Input Capacitance: RAS0#-RAS3#
C
I
4
10
10
p F
2
Input Capacitance: SCL, SA0-SA2
C
I
5
10
10
p F
2
Input/Output Capacitance: DQ0-DQ31, SDA
C
IO
10
18
p F
2
MAX
9
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
t
AA
25
30
ns
Column-address hold time (referenced to RAS#)
t
AR
40
45
ns
Column-address setup time
t
ASC
0
0
ns
Row-address setup time
t
ASR
0
0
ns
Column address to WE# delay time
t
AWD
48
55
ns
27
Access time from CAS#
t
CAC
13
15
ns
Column-address hold time
t
CAH
8
10
ns
CAS# pulse width
t
CAS
13
10,000
15
10,000
ns
CAS# hold time (CBR Refresh)
t
CHR
15
15
ns
4
CAS# to output in Low-Z
t
CLZ
3
3
ns
21
CAS# precharge time
t
CP
8
10
ns
13
Access time from CAS# precharge
t
CPA
30
35
ns
CAS# to RAS# precharge time
t
CRP
5
5
ns
CAS# hold time
t
CSH
50
60
ns
CAS# setup time (CBR Refresh)
t
CSR
5
5
ns
CAS# to WE# delay time
t
CWD
36
40
ns
27
WRITE command to CAS# lead time
t
CWL
13
15
ns
Data-in hold time
t
DH
8
10
ns
18
Data-in setup time
t
DS
0
0
ns
18
Output disable
t
OD
3
13
3
15
ns
Output enable
t
OE
13
15
ns
OE# hold time from WE# during
t
OEH
13
15
ns
28
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
t
OFF
3
13
3
15
ns
17, 24
10
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
OE# setup prior to RAS#
t
ORD
0
0
ns
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
t
PC
30
35
ns
EDO-PAGE-MODE READ-WRITE cycle time
t
PRWC
76
85
ns
Access time from RAS#
t
RAC
50
60
ns
RAS# to column-address delay time
t
RAD
13
15
ns
15
Row-address hold time
t
RAH
8
10
ns
RAS# pulse width
t
RAS
50
10,000
60
10,000
ns
RAS# pulse width (EDO PAGE MODE)
t
RASP
50
125,000
60
125,000
ns
Random READ or WRITE cycle time
t
RC
90
110
ns
RAS# to CAS# delay time
t
RCD
18
20
ns
14
READ command hold time (referenced to CAS#)
t
RCH
0
0
ns
16
READ command setup time
t
RCS
0
0
ns
Refresh period (4,096 cycles)
t
REF
64
64
ms
RAS# precharge time
t
RP
30
40
ns
RAS# to CAS# precharge time
t
RPC
0
0
ns
READ command hold time (referenced to RAS#)
t
RRH
0
0
ns
16
RAS# hold time
t
RSH
13
15
ns
READ-WRITE cycle time
t
RWC
131
155
ns
RAS# to WE# delay time
t
RWD
73
85
ns
27
WRITE command to RAS# lead time
t
RWL
13
15
ns
Transition time (rise or fall)
t
T
2
50
2
50
ns
WRITE command hold time
t
WCH
8
10
ns
WRITE command hold time (referenced to RAS#)
t
WCR
40
45
ns
WE# command setup time
t
WCS
0
0
ns
27
WRITE command pulse width
t
WP
8
10
ns
WE# hold time (CBR Refresh)
t
WRH
10
10
ns
WE# setup time (CBR Refresh)
t
WRP
10
10
ns
11
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
t
AA
25
30
ns
Column-address setup to CAS# precharge
t
ACH
12
15
ns
Column-address hold time (referenced to RAS#)
t
AR
38
45
ns
Column-address setup time
t
ASC
0
0
ns
Row-address setup time
t
ASR
0
0
ns
Column address to WE# delay time
t
AWD
42
49
ns
27
Access time from CAS#
t
CAC
13
15
ns
Column-address hold time
t
CAH
8
10
ns
CAS# pulse width
t
CAS
8
10,000
10
10,000
ns
CAS# hold time (CBR Refresh)
t
CHR
8
10
ns
4
CAS# to output in Low-Z
t
CLZ
0
0
ns
Data output hold after next CAS# LOW
t
COH
3
3
ns
CAS# precharge time
t
CP
8
10
ns
13
Access time from CAS# precharge
t
CPA
28
35
ns
CAS# to RAS# precharge time
t
CRP
5
5
ns
CAS# hold time
t
CSH
38
45
ns
CAS# setup time (CBR Refresh)
t
CSR
5
5
ns
CAS# to WE# delay time
t
CWD
28
35
ns
27
WRITE command to CAS# lead time
t
CWL
8
10
ns
Data-in hold time
t
DH
8
10
ns
18
Data-in setup time
t
DS
0
0
ns
18
Output disable
t
OD
0
12
0
15
ns
Output enable
t
OE
12
15
ns
OE# hold time from WE# during
t
OEH
8
10
ns
28
READ-MODIFY-WRITE cycle
OE# HIGH hold from CAS# HIGH
t
OEHC
5
10
ns
28
OE# HIGH pulse width
t
OEP
5
5
ns
OE# LOW to CAS# HIGH setup time
t
OES
4
5
ns
Output buffer turn-off delay
t
OFF
0
12
0
15
ns
17, 24
12
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 12, 19) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS - EDO PAGE MODE OPTION
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
OE# setup prior to RAS#
t
ORD
0
0
ns
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
t
PC
20
25
ns
EDO-PAGE-MODE READ-WRITE cycle time
t
PRWC
47
56
ns
Access time from RAS#
t
RAC
50
60
ns
RAS# to column-address delay time
t
RAD
9
12
ns
15
Row-address hold time
t
RAH
9
10
ns
RAS# pulse width
t
RAS
50
10,000
60
10,000
ns
RAS# pulse width (EDO PAGE MODE)
t
RASP
50
125,000
60
125,000
ns
Random READ or WRITE cycle time
t
RC
84
104
ns
RAS# to CAS# delay time
t
RCD
11
14
ns
14
READ command hold time (referenced to CAS#)
t
RCH
0
0
ns
16
READ command setup time
t
RCS
0
0
ns
Refresh period (4,096 cycles)
t
REF
64
64
ms
RAS# precharge time
t
RP
30
40
ns
RAS# to CAS# precharge time
t
RPC
5
5
ns
READ command hold time (referenced to RAS#)
t
RRH
0
0
ns
16
RAS# hold time
t
RSH
13
15
ns
READ-WRITE cycle time
t
RWC
116
140
ns
RAS# to WE# delay time
t
RWD
67
79
ns
27
WRITE command to RAS# lead time
t
RWL
13
15
ns
Transition time (rise or fall)
t
T
2
50
2
50
ns
WRITE command hold time
t
WCH
8
10
ns
WRITE command hold time (referenced to RAS#)
t
WCR
38
45
ns
WE# command setup time
t
WCS
0
0
ns
27
Output disable delay from WE#
t
WHZ
12
15
ns
WRITE command pulse width
t
WP
5
5
ns
WE# pulse to disable at CAS# HIGH
t
WPZ
10
10
ns
WE# hold time (CBR Refresh)
t
WRH
8
10
ns
WE# setup time (CBR Refresh)
t
WRP
8
10
ns
13
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.3
3.5
s
Time the bus must be free before a new transition can start
t
BUF
4.7
s
Data-out hold time
t
DH
300
ns
SDA and SCL fall time
t
F
300
ns
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
4
s
Clock HIGH period
t
HIGH
4
s
Noise suppression time constant at SCL, SDA inputs
t
I
100
ns
Clock LOW period
t
LOW
4.7
s
SDA and SCL rise time
t
R
1
s
SCL clock frequency
t
SCL
100
KHz
Data-in setup time
t
SU:DAT
250
ns
Start condition setup time
t
SU:STA
4.7
s
Stop condition setup time
t
SU:STO
4.7
s
WRITE cycle time
t
WRC
10
ms
29
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7 V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
L I
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT:
I
SB
30
A
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
I
CC
2
mA
SCL clock frequency = 100 KHz
14
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
3. I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100s is required after power-
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
REF refresh requirement is exceeded.
7. AC characteristics assume
t
T = 5ns for FPM and
t
T = 2.5ns for EDO.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate
specification, all input signals must transit between
V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-
tonic manner.
10.If CAS# = V
IH
, data output is High-Z.
11.If CAS# = V
IL
, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF and V
OL
= 0.8V and V
OH
= 2V.
13.If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
t
CP.
14.The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively
by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD (MAX) limit,
t
AA and
t
CAC
must always be met.
15.The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively
by
t
AA (
t
RAC and
t
CAC no longer applied). With
or without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC must always be met.
16.Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
18.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
19.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
permissible and should not be attempted.
Additionally, with EDO, WE# must be pulsed
during CAS# HIGH time in order to place I/O
buffers in High-Z.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The 3ns minimum is a parameter guaranteed by
design.
22.Column address changed once each cycle.
23.16MB module values will be half of those shown.
24.With the FPM option,
t
OFF is determined by the
first RAS# or CAS# signal to transition HIGH. In
comparison,
t
OFF on an EDO option is deter-
mined by the latter of the RAS# and CAS# signals
to transition HIGH.
25.Applies to both FPM and EDO operating modes.
26.All other inputs at 0.2V or V
DD
- 0.2V.
27.
t
WCS,
t
RWD,
t
AWD and
t
CWD are not restrictive
operating parameters.
t
WCS applies to EARLY
WRITE cycles.
t
RWD,
t
AWD and
t
CWD apply to
READ-MODIFY-WRITE cycles. If
t
WCS
t
WCS
(MIN), the cycle is an EARLY WRITE cycle and the
data output will remain an open circuit through-
out the entire cycle. If
t
WCS <
t
WCS (MIN) and
t
RWD
t
RWD (MIN),
t
AWD
t
AWD (MIN) and
t
CWD
t
CWD (MIN), the cycle is a READ-
MODIFY-WRITE and the data output will contain
data read from the selected cell. If neither of the
above conditions is met, the state of data-out is
indeterminate. OE# held HIGH and WE# taken
LOW after CAS# goes LOW result in a LATE
WRITE (OE#-controlled) cycle.
t
WCS,
t
RWD,
t
CWD and
t
AWD are not applicable in a LATE
WRITE cycle.
28.LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. The DQs will provide the previously read
data if CAS# remains LOW and OE# is taken back
LOW after
t
OEH is met. If CAS# goes HIGH prior
to OE# going back LOW, the DQs will remain
open.
15
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
NOTES (continued)
29.The SPD EEPROM WRITE cycle time (
t
WRC) is the
time from a valid stop condition of a write sequence
to the end of the EEPROM internal erase/program
cycle. During the WRITE cycle, the EEPROM bus
interface circuit is disabled, SDA remains HIGH due
to pull-up resistor, and the EEPROM does not re-
spond to its slave address.
30.V
IH
overshoot: V
IH
(MAX) = V
DD
+ 2V for a pulse
width 10ns, and the pulse width cannot be greater
than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width 10ns, and the pulse
width cannot be greater than one third of the cycle
rate.
16
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
READ CYCLE
25
tRRH
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tOFF
tRCH
ROW
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tRSH
tCSH
tRP
tRC
tRAS
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
tOD
tOE
OE#
V
V
IH
IL
COLUMN
WE#
CASL#/CASH#
NOTE 1
tACH
DON'T CARE
UNDEFINED
NOTE: 1. For EDO,
t
OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last. For FPM,
t
OFF is referenced from
rising edge of RAS# or CAS#, whichever occurs first.
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
OD (FPM)
3
13
3
15
ns
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE (EDO)
12
15
ns
t
OFF (FPM)
3
13
3
15
ns
t
OFF (EDO)
0
12
0
15
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
17
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
EARLY WRITE CYCLE
25
DON'T CARE
UNDEFINED
V
V
IH
IL
VALID DATA
ROW
COLUMN
ROW
tDS
tWP
tWCH
tWCS
tWCR
tRWL
tCWL
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCAS
tRSH
tCSH
tRCD
tCRP
tRAS
tRC
tRP
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
tDH
WE#
CASL#/CASH#
tACH
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR (FPM)
40
45
ns
t
WCR (EDO)
38
45
ns
t
WCS
0
0
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
18
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
40
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
13
10,000
15
10,000
ns
t
CLZ
3
3
ns
t
CP
8
10
ns
t
CPA
30
35
ns
t
CRP
5
5
ns
t
CSH
50
60
ns
t
OD
3
13
3
15
ns
VALID
DATA
VALID
DATA
VALID
DATA
COLUMN
COLUMN
COLUMN
ROW
ROW
DON'T CARE
UNDEFINED
tRCS
tCAH
tASC
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRCH
tRCH
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tOFF
tCAC
tCPA
tAA
tCLZ
tOFF
tCAC
tRAC
tAA
tCLZ
tOE
tOD
tOE
tOD
tOE
tOD
OPEN
OPEN
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
tCAS
tCAS
WE#
CASL#/CASH#
FAST-PAGE-MODE READ CYCLE
t
OE
13
15
ns
t
OFF
3
13
3
15
ns
t
PC
30
35
ns
t
RAC
50
60
ns
t
RAD
13
15
ns
t
RAH
8
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
18
20
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
19
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
EDO-PAGE-MODE READ CYCLE
WE#
ACH
VALID
DATA
VALID
DATA
VALID
DATA
COLUMN
COLUMN
COLUMN
ROW
ROW
DON'T CARE
UNDEFINED
tOD
tCAH
tASC
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
tCAH
tASC
tCAH
tASC
tRAD
t
AR
tRAH
tRAD
tASR
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tCAC
tCPA
tAA
tCAC
tRAC
tAA
tCLZ
tOE
tOD
tOE
tOD
OPEN
OPEN
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
RAS#
OE#
CASL#/CASH#
tCOH
tOEP
tOEHC
tOES
tOES
tCAS
tCAS
t
ACH
t
ACH
t
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
COH
3
3
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
OEHC
5
10
ns
t
OEP
5
5
ns
t
OES
4
5
ns
t
OFF
0
12
0
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
20
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST/EDO-PAGE-MODE EARLY WRITE CYCLE
25
tDS
tDH
tDS
tDH
tDS
tDH
tWCR
VALID DATA
VALID DATA
VALID DATA
tRWL
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tRAD
tAR
COLUMN
COLUMN
COLUMN
ROW
ROW
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
V
V
IH
IL
CASL#/CASH#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
RAS#
OE#
V
V
IH
IL
DON'T CARE
UNDEFINED
t
tACH
tACH
tCAS
tCAS
ACH
t
PC (EDO)
20
25
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR (FPM)
40
45
ns
t
WCR (EDO)
38
45
ns
t
WCS
0
0
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
PC (FPM)
30
35
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
21
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
READ-WRITE CYCLE
25
(LATE WRITE and READ-MODIFY-WRITE cycles)
VALID D
OUT
VALID D
IN
ROW
COLUMN
ROW
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OPEN
OPEN
tOE
tOD
tCAC
tRAC
tAA
t CLZ
tDS
tDH
tAWD
tWP
tRWL
tCWL
tCWD
tRWD
tRCS
tASC
tCAH
tAR
tASR
tRAD
tCRP
tRCD
tCAS
tRSH
tCSH
tRAS
tRWC
tRP
tRAH
OE#
tOEH
WE#
tACH
CAS#
DON'T CARE
UNDEFINED
t
OD (FPM)
3
13
3
15
ns
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
t
OE (EDO)
12
15
ns
t
OEH (FPM)
13
15
ns
t
OEH (EDO)
8
10
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWC (FPM)
131
155
ns
t
RWC (EDO)
116
140
ns
t
RWD (FPM)
73
85
ns
t
RWD (EDO)
67
79
ns
t
RWL
13
15
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
n
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD (FPM)
48
55
ns
t
AWD (EDO)
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CSR
5
5
ns
t
CWD (FPM)
36
40
ns
t
CWD (EDO)
28
35
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
22
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
FAST/EDO-PAGE-MODE READ-WRITE CYCLE
25
(LATE WRITE and READ-MODIFY-WRITE cycles)
DON'T CARE
UNDEFINED
t
t
OD
tOE
tOD
tOE
tOD
tOE
OPEN
D
OUT
VALID
D
OUT
VALID
D
OUT
VALID
D
IN
VALID
D
IN
VALID
D
IN
VALID
OPEN
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCLZ
tCAC
tRAC
tWP
tCWL
tRWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tRCS
tRWD
tASR
tRAH
tASC
tRAD
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tRSH
tCP
tRP
tRASP
tCP
tRCD
tCSH
tPC
t
CRP
ROW
COLUMN
COLUMN
COLUMN
ROW
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
tPRWC
OEH
tCAS
tCAS
tCAS
WE#
CASL#/CASH#
NOTE 1
NOTE: 1.
t
PC is for LATE WRITE cycles only.
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
t
OE (EDO)
12
15
ns
t
OEH (FPM)
13
15
ns
t
OEH (EDO)
8
10
ns
t
PC (FPM)
30
35
ns
t
PC (EDO)
20
25
ns
t
PRWC (FPM)
76
85
ns
t
PRWC (EDO)
47
56
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWD (FPM)
73
85
ns
t
RWD (EDO)
67
79
ns
t
RWL
13
15
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD (FPM)
48
55
ns
t
AWD (EDO)
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CP
8
10
ns
t
CPA (FPM)
30
35
ns
t
CPA (EDO)
28
35
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWD (FPM)
36
40
ns
t
CWD (EDO)
28
35
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
OD (FPM)
3
13
3
15
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
23
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
V
V
IH
IL
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
tRASP
tRP
ROW
COLUMN (A)
COLUMN (N)
ROW
V
V
IH
IL
OE#
V
V
IOH
IOL
tCRP
tCSH
tCAS
tRCD
tASR
tRAH
tRAD
tASC
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tRSH
VALID D
IN
tRCS
tRCH
tWCS
tOE
VALID
D
OUT
VALID D
OUT
tWHZ
tCAC
tCPA
tAA
tCAC
tAA
OPEN
DQ
tPC
RAC
t
tCOH
tWCH
tDS
tDH
tPC
COLUMN (B)
tACH
CASL#/CASH#
tCAS
tCAS
tCP
tCP
DON'T CARE
UNDEFINED
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
t
OE
12
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
WCH
8
10
ns
t
WCS
0
0
ns
t
WHZ
12
15
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
COH
3
3
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
DH
8
10
ns
t
DS
0
0
ns
24
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
ROW
VALID
DATA
VALID DATA
OPEN
tCRP
tRCD
tCAS
tRSH
tRASP
tRP
tPC
tASC
tCAH
tAR
tASR
tRAD
tRAH
tWCS
tWP
tRWL
tRCS
tDH
tDS
tCAC
tOFF
V
V
IH
IL
CASL#/CASH#
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
Q
V
V
OH
OL
WE#
V
V
IH
IL
tCSH
COLUMN
tCP
tCP
tASC
tCAH
tCWL
tWCH
tCLZ
tAA
RAC
DON'T CARE
UNDEFINED
t
NOTE 1
OE#
V
V
IH
IL
ROW
COLUMN
tCAS
FAST-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
NOTE: 1. Do not drive data prior to tristate.
t
OFF
3
13
3
15
ns
t
PC
30
35
ns
t
RAC
50
60
ns
t
RAD
13
15
ns
t
RAH
8
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
18
20
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCS
0
0
ns
t
WP
8
10
ns
FAST PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
40
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
13
10,000
15
10,000
ns
t
CLZ
3
3
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
50
60
ns
t
CWL
13
15
ns
t
DH
8
10
ns
t
DS
0
0
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
25
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
EDO READ CYCLE
(with WE#-controlled disable)
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
WHZ
12
15
ns
t
WPZ
10
10
ns
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tRCH
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tCSH
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
tOD
tOE
OE#
V
V
IH
IL
COLUMN
WE#
tWHZ
tWPZ
tCP
tASC
tRCS
COLUMN
tCLZ
CASL#/CASH#
DON'T CARE
UNDEFINED
26
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RP
30
40
ns
t
RPC (FPM)
0
0
ns
t
RPC (EDO)
5
5
ns
t
WRH (FPM)
10
10
ns
t
WRH (EDO)
8
10
ns
t
WRP (FPM)
10
10
ns
t
WRP (EDO)
8
10
ns
RAS#-ONLY REFRESH CYCLE
25
ROW
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
tRC
tRAS
tRP
tCRP
tASR
tRAH
ROW
OPEN
DQ
V
V
OH
OL
tRPC
WE#
V
V
IH
IL
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ASR
0
0
ns
t
CHR (FPM)
15
15
ns
t
CHR (EDO)
8
10
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSR
5
5
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
CBR REFRESH CYCLE
25
(Addresses = DON'T CARE)
tRP
V
V
IH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
V
IH
IL
V
V
OH
OL
CAS#
DQ
tRP
tRAS
tRPC
tCSR
tRPC
tCHR
tCP
V
V
IH
IL
tWRP
tWRH
WE#
tWRP
tWRH
DON'T CARE
UNDEFINED
27
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
HIDDEN REFRESH CYCLE
20, 25
(WE# = HIGH)
DON'T CARE
UNDEFINED
tCLZ
tOFF
OPEN
VALID DATA
OPEN
COLUMN
ROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP
tRCD
tRSH
tRAS
tRC
tRP
tCHR
tRAS
DQx
V
V
IOH
IOL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
RAS#
V
V
IH
IL
tOE
tOD
OE#
tORD
CASL#/CASH#
t
OFF (FPM)
3
13
3
15
ns
t
OFF (EDO)
0
12
0
15
ns
t
ORD
0
0
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CHR (FPM)
15
15
ns
t
CHR (EDO)
8
10
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CRP
5
5
ns
t
OD (FPM)
3
13
3
15
ns
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
t
OE (EDO)
12
15
ns
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
28
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
SPD EEPROM
SYMBOL
MIN
MAX
UNITS
t
HIGH
4
s
t
LOW
4.7
s
t
R
1
s
t
SU:DAT
250
ns
t
SU:STA
4.7
s
t
SU:STO
4.7
s
SERIAL PRESENCE-DETECT EEPROM
TIMING PARAMETERS
SYMBOL
MIN
MAX
UNITS
t
AA
0.3
3.5
s
t
BUF
4.7
s
t
DH
300
ns
t
F
300
ns
t
HD:DAT
0
s
t
HD:STA
4
s
29
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
.125 (3.18)
MAX
.054 (1.37)
.046 (1.17)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.079 (2.00) R
(2X)
PIN 1
.250 (6.35) TYP
.050 (1.27)
TYP
.118 (3.00)
TYP
.039 (1.00)
TYP
.039 (1.00) R(2X)
PIN 50
2.850 (72.39)
1.005 (25.53)
0.995 (25.27)
3.557 (90.34)
3.545 (90.04)
.128 (3.25)
.118 (3.00)
(2X)
100-PIN DIMM
DF-3 (16MB)
100-PIN DIMM
DF-4 (32MB)
.157 (4.00)
MAX
.054 (1.37)
.046 (1.17)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
.079 (2.00) R
(2X)
PIN 1
.250 (6.35) TYP
.050 (1.27)
TYP
.118 (3.00)
TYP
.039 (1.00)
TYP
.039 (1.00) R(2X)
PIN 50
2.850 (72.39)
1.005 (25.53)
0.995 (25.27)
3.557 (90.34)
3.545 (90.04)
.128 (3.25)
.118 (3.00)
(2X)
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
30
4, 8 Meg x 32 DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM85.p65 Rev. 2/99
1999, Micron Technology, Inc.
4, 8 MEG x 32
DRAM DIMMs
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
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