09005aef80948ad4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD2_4C4_8_16_32x32UDG_A.fm - Rev. A 2/03 EN
1
2003, Micron Technology Inc.
16MB, 32MB, 64MB, 128MB (x32)
100-PIN SDRAM DIMM
SYNCHRONOUS
DRAM MODULE
MT2LSDT432U 16MB, MT4LSDT832UD 32MB,
MT4LSDT1632UD 64MB, MT4LSDT3232UD 128MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/moduleds
Features
JEDEC-standard, 100-pin, dual in-line memory
module (DIMM)
16MB (4 Meg x 32), 32MB (8 Meg x 32), 64MB (16
Meg x 32), or 128MB (32 Meg x 32)
Utilizes 100 MHz and 125 MHz SDRAM components
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge and Auto Refresh Modes
64ms, 4,096-cycle (16MB, 32MB, and 64MB)and
8,192-cycle (128MB) refresh
LVTTL-compatible inputs and outputs
Serial presence-detect (SPD)
Figure 1: 100-Pin DIMM (MO161)
OPTIONS
MARKING
Package
100-pin DIMM (Gold)
G
100-pin DIMM (Lead-Free)
Y
Timing (Cycle Timing)
7.5ns (133 MHz)
-75
8ns (125 MHz)
-8
10ns (100 MHz)
-10
Table 1:
Timing Parameters
CL = CAS (READ) Latency
SPEED
GRADE
CLOCK
FREQUENCY
ACCESS TIME
SETUP
TIME
HOLD
TIME
CL = 2 CL = 3
-75
133 MHz
5.4ns
5.4ns
1.5ns
0.8ns
-8
125 MHz
6ns
6ns
2ns
1ns
-10
100 MHz
9ns
7.5ns
2ns
1ns
Table 2:
Address Table
MODULE DENSITY
16MB
32MB
64MB
128MB
Refresh Count
4K
4K
4K
8K
Device Banks
4 (BA0BA1)
4 (BA0BA1)
4 (BA0BA1)
4 (BA0BA1)
Device Configuration
4 Meg x 16
8 Meg x 16
16 Meg x 16
32 Meg x 16
Device Row Addressing
4K (A0A11)
4K (A0A11)
4K (A0A11)
8K (A0A12))
Device Column Addressing
256 (A0A7)
256 (A0A7)
512 (A0A8)
512 (A0A8)
Module Ranks
1 (S0#, S2#)
2 (S0#, S2#, S1#, S3#) 2 (S0#, S2#, S1#, S3#) 2 (S0#, S2#, S1#, S3#)
16MB, 32MB, 64MB, 128MB (x32)
100-PIN SDRAM DIMM
09005aef80948ad4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD2_4C4_8_16_32x32UDG_A.fm - Rev. A 2/03 EN
2
2003, Micron Technology Inc.
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions. Con-
sult factory for current revision codes. Example:
MT2LSDT432UG-8B1.
Figure 2: Module Layout
Table 3:
Part Numbers
PART NUMBER
CONFIGURATION
DEVICE
PACKAGE
MT2LSDT432UG-75__
4 Meg x 32
TSOP
MT2LSDT432UY-75__
4 Meg x 32
TSOP
MT2LSDT432UG-8__
4 Meg x 32
TSOP
MT2LSDT432UY-8__
4 Meg x 32
TSOP
MT2LSDT432UG-10__
4 Meg x 32
TSOP
MT2LSDT432UY-10__
4 Meg x 32
TSOP
MT4LSDT832UDG-75__
8 Meg x 32
TSOP
MT4LSDT832UDY-75__
8 Meg x 32
TSOP
MT4LSDT832UDG-8__
8 Meg x 32
TSOP
MT4LSDT832UDY-8__
8 Meg x 32
TSOP
MT4LSDT832UDG-10__
8 Meg x 32
TSOP
MT4LSDT832UDY-10__
8 Meg x 32
TSOP
MT4LSDT1632UDG-75__
16 Meg x 32
TSOP
MT4LSDT1632UDY-75__
16 Meg x 32
TSOP
MT4LSDT1632UDG-8__
16 Meg x 32
TSOP
MT4LSDT1632UDY-8__
16 Meg x 32
TSOP
MT4LSDT1632UDG-10__
16 Meg x 32
TSOP
MT4LSDT1632UDY-10__
16 Meg x 32
TSOP
MT4LSDT3232UDG-75__
32 Meg x 32
TSOP
MT4LSDT3232UDY-75__
32 Meg x 32
TSOP
MT4LSDT3232UDG-8__
32 Meg x 32
TSOP
MT4LSDT3232UDY-8__
32 Meg x 32
TSOP
MT4LSDT3232UDG-10__
32 Meg x 32
TSOP
MT4LSDT3232UDY-10__
32 Meg x 32
TSOP
Table 4:
Pin Assignment
(100-Pin DIMM Front)
PIN SYMBOL PIN
SYMBOL
PIN
SYMBOL
PIN SYMBOL
1
Vss
13
A0
26
Vss
38
DQ16
2
DQ0
14
A2
27
CKE0
39
DQ17
3
DQ1
15
A4
28
WE#
40
DQ18
4
DQ2
16
A6
29
S0#
41
DQ19
5
DQ3
17
A8
30
S2#
42
V
DD
6
V
DD
18
A10
31
V
DD
43
DQ20
7
DQ4
19
BA1
32
NC
44
DQ21
8
DQ5
20
A12
33
NC
45
DQ22
9
DQ6
21
V
DD
34
NC
46
DQ23
10
DQ7
22
DNU
35
NC
47
Vss
11
DQMB0
23
RFU
36
Vss
48
SDA
12
Vss
24
RFU
37
DQMB2
49
SCL
25
CK0
50
V
DD
Table 5:
Pin Assignment
(100-Pin DIMM Back)
PIN SYMBOL PIN
SYMBOL
PIN
SYMBOL
PIN SYMBOL
51
Vss
63
A1
76
Vss
88
DQ24
52
DQ8
64
A3
77
CKE1
89
DQ25
53
DQ9
65
A5
78
DNU
90
DQ26
54
DQ10
66
A7
79
S1#
91
DQ27
55
DQ11
67
A9
80
S3#
92
V
DD
56
V
DD
68
BA0
81
V
DD
93
DQ28
57
DQ12
69
A11
82
NC
94
DQ29
58
DQ13
70
NC
83
NC
95
DQ30
59
DQ14
71
V
DD
84
NC
96
DQ31
60
DQ15
72
RAS#
85
NC
97
Vss
61
DQMB1
73
CAS#
86
Vss
98
SA0
62
Vss
74
RFU
87
DQMB3
99
SA1
75
CK1
100
SA2
Indicates a V
DD
pin
Indicates a V
SS
pin
PIN100
PIN 51
PIN 73
Back View
(Not populated for the 4MB module)
U3
U4
PIN 50
PIN 23
PIN 1
Front View
U1
U2
U5
16MB, 32MB, 64MB, 128MB (x32)
100-PIN SDRAM DIMM
09005aef80948ad4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD2_4C4_8_16_32x32UDG_A.fm - Rev. A 2/03 EN
3
2003, Micron Technology Inc.
Table 6:
Pin Descriptions
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
28, 72, 73
RAS#, CAS#, WE#
Input
Command Inputs: RAS#, CAS# and WE# (along with S#) define the
command being entered.
25, 75
CK0, CK1
Input
Clock: CK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. CK also increments the
internal burst counter and controls the output registers.
27, 77
CKE0, CKE1
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides POWER-DOWN and SELF
REFRESH operation (all banks idle), or CLOCK SUSPEND operation
(burst access in progress). CKE is synchronous except after the
device enters power-down and self refresh modes, where CKE
becomes asynchronous until after exiting the same mode. The
input buffers, including CK is disabled during power-down and self
refresh modes, providing low standby power.
29, 30, 79, 80
S0#-S3#
Input
Chip Select: S# enables (registered LOW) and disablse (registered
HIGH) the command decoder. All commands are masked when S#
is registered HIGH. S# is considered part of the command code.
11, 37, 61, 87
DQMB0-DQMB3
Input
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input data
is masked when DQMB is sampled HIGH during a WRITE cycle. The
output buffers are placed in a High-Z state (after a two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
19, 68
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied.
13-18, 63-67, 6970
A0-A12
Input
Address Inputs: A0-A12 are sampled during the ACTIVE command
(row-address A0-A12) and READ/WRITE command (column-address
A0-A8, with A10 defining AUTO PRECHARGE) to select one
location out of the memory array in the respective bank. A10 is
sampled during a PRE-CHARGE command to determine if both
banks are to be precharged (A10 HIGH). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.
2-5, 7-10, 38-41, 43-46,
52-55, 57-60, 88-91,
93-96
DQ0-DQ31
Input/
Output
Data I/Os: Data bus.
6, 21, 31, 42, 50,
56, 71, 81, 92
V
DD
Supply
Power Supply: +3.3V 0.3V.
1, 12, 26, 36, 47,
51, 62, 76, 86, 97
V
SS
Supply
Ground.
48
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and data out of the presence-
detect portion of the module.
49
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
98-100
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to configure
the presence-detect device.
23, 24, 74
RFU
Reserved for Future Use: These pins should be left unconnected.
22, 78
DNU
Do Not Use: These pins are not connected on this module but are
assigned pins on the compatible DRAM version.
3235, 70, 8285
NC
Not connected.
16MB, 32MB, 64MB, 128MB (x32)
100-PIN SDRAM DIMM
09005aef80948ad4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD2_4C4_8_16_32x32UDG_A.fm - Rev. A 2/03 EN
4
2003, Micron Technology Inc.
Figure 3: Functional Block Diagram (16MB)
A0
SPD
SCL
SDA
A1
A2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMH
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S0#
RAS#
CAS#
CKE0
WE#
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs
WE#: SDRAMs
A0-A11: SDRAMs
BA0: SDRAMs
BA1: SDRAMs
A0-A11
BA0
BA1
V
DD
V
SS
SDRAMs
SDRAMs
CK0
U1
U2
6.8pF
10pF
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQML CS#
DQMB1
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMH
U2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
S2#
DQML CS#
DQMB3
CK1
SA0 SA1 SA2
WP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
SDRAM = MT48LC4M16A2TG for 16MB module
NOTE:
1.
All resistor values are 10
W..
2.
Per industry standard, Micron utilizes various component speed grades as refer-
enced in the Module Part Numbering Guide at
www.micron.com/numberguide
.
16MB, 32MB, 64MB, 128MB (x32)
100-PIN SDRAM DIMM
09005aef80948ad4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD2_4C4_8_16_32x32UDG_A.fm - Rev. A 2/03 EN
5
2003, Micron Technology Inc.
Figure 4: Functional Block Diagram
(32MB, 64MB, 128MB)
A0
SPD
SCL
SDA
A1
A2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMH
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S0#
RAS#
CAS#
CKE0
CKE1
WE#
RAS#: SDRAMs
CAS#: SDRAMs
CKE: SDRAMs U1-U2
CKE: SDRAMs U3-U4
WE#: SDRAMs
A0-A11: SDRAMs
A0-A12: SDRAMs
BA0: SDRAMs
BA1: SDRAMs
A0-A11 (32MB, 64MB)
A0-A12 (128MB)
BA0
BA1
V
DD
V
SS
SDRAMs
SDRAMs
CK0
U1
U2
6.8pF
6.8pF
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQML CS#
DQMB1
DQMH
U3
DQML CS#
S1#
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMH
U2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
S2#
DQML CS#
DQMB3
DQMH
U4
DQML CS#
S3#
CK1
U3
U4
SA0 SA1 SA2
WP
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U5
SDRAMs = MT48LC4M16A2TG for 32MB module
SDRAMs = MT48LC8M16A2TG for 64MB module
SDRAMs = MT48LC16M16A2TG for 128MB module
NOTE:
1.
All resistor values are 10
W..
2.
Per industry standard, Micron utilizes various component speed grades as refer-
enced in the Module Part Numbering Guide at
www.micron.com/numberguide
.
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