PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef80b18348
SD36C128_256x72G_C.fm - Rev. C 5/03 EN

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

SYNCHRONOUS
DRAM MODULE

MT36LSDT12872 1GB
MT36LSDT25672 2GB

For the latest data sheet, please refer to the Micron

Web

site: www.micron.com/datasheets

Features

· JEDEC-standard, 168-pin, dual in-line memory

module (DIMM)

· PC100 and PC133 compliant
· Stacked TSOP SDRAM components
· Registered inputs with one-clock delay
· Phase-lock loop (PLL) clock driver to reduce loading
· Utilizes 100 MHz and 133 MHz SDRAM

components

· ECC-optimized pinout
· Single +3.3V ±0.3V power supply
· Fully synchronous; all signals registered on positive

edge of PLL clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal SDRAM banks for hiding row access/

precharge

· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge and Auto Refresh Modes
· Self Refresh Mode: 64ms, 8,192 cycle refresh
· LVTTL-compatible inputs and outputs
· Serial presence-detect (SPD)
· Gold edge contacts

NOTE:

1. CL = CAS (READ) Latency. Registered mode adds

one clock cycle to CL.

Figure 1: 168-Pin DIMM (MO-161)

OPTIONS

MARKING

· Package

168-pin DIMM (Standard)

168-pin DIMM (Lead-free)

· Standard or Low-Profile PCB

See note on page 2

· Frequency/CAS Latency

133 MHz/CL = 2

-13E

133 MHz/CL = 3

-133

100 MHz/CL = 2

-10E

Table 1:

Device Timing

MODULE

MARKINGS

PC100

CL -

RCD -

PC133

CL -

RCD -

-13E

2 - 2 - 2

-133

2 - 2 - 2

3 - 3 - 3

-10E

2 - 2 - 2

Table 2:

Address Table

1GB

2GB

Refresh Count

Device Banks

4 (BA0, BA1)

Device Configuration

64 Meg x 4

128 Meg x 4

Row Addressing

8K (A0A12)

Column Addressing

2K (A0A9, A11) 4K (A0A9, A11, A12)

Module Ranks

2 (S0, S2; S1, S3)

Standard PCB

1.70in. (43.18mm)

Low-Profile PCB

1.20in. (30.48mm)

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

NOTE:

The designators for component and PCB revision are the last two characters of each part number. Consult factory for
current revision codes. Example: MT36LSDT12872G-133B1.

Table 3:

Part Numbers

PART NUMBER

MODULE DENSITY

CONFIGURATION

SYSTEM BUS SPEED

MT36LSDT12872G-13E__

1GB

128 Meg x 72

133 MHz

MT36LSDT12872Y-13E__

1GB

128 Meg x 72

133 MHz

MT36LSDT12872G-133__

1GB

128 Meg x 72

133 MHz

MT36LSDT12872Y-133__

1GB

128 Meg x 72

133 MHz

MT36LSDT12872G-10E__

1GB

128 Meg x 72

100 MHz

MT36LSDT12872Y-10E__

1GB

128 Meg x 72

100 MHz

MT36LSDT25672G-13E__

2GB

256 Meg x 72

133 MHz

MT36LSDT25672Y-13E__

2GB

256 Meg x 72

133 MHz

MT36LSDT25672G-133__

2GB

256 Meg x 72

133 MHz

MT36LSDT25672Y-133__

2GB

256 Meg x 72

133 MHz

MT36LSDT25672G-10E__

2GB

256 Meg x 72

100 MHz

MT36LSDT25672Y-10E__

2GB

256 Meg x 72

100 MHz

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

Figure 2: 168-Pin DIMM Pin Assignment

Table 4:

PIN Assignment
(168-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

CB1

DQ0

DQ21

DQ1

S2#

DQ22

DQ2

DQMB2

DQ23

DQ3

DQMB3

WE#

DQ24

DQ4

DQMB0

DQ25

DQ5

DQMB1

DQ26

DQ6

S0#

DQ27

DQ7

CB2

DQ8

CB3

DQ28

DQ29

DQ9

DQ16

DQ30

DQ10

DQ17

DQ31

DQ11

DQ18

DQ12

DQ19

CK2

DQ13

A10

BA1

DQ20

DQ14

SDA

DQ15

SCL

CB0

CK0

Table 5:

PIN Assignment
(168-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

106

CB5

127

148

DQ32

107

128

CKE0

149

DQ53

DQ33

108

129

S3#

150

DQ54

DQ34

109

130 DQMB6

151

DQ55

DQ35

110

131 DQMB7 152

111

CAS#

132

153

DQ56

DQ36

112 DQMB4 133

154

DQ57

DQ37

113 DQMB5 134

155

DQ58

DQ38

114

S1#

135

156

DQ59

DQ39

115

RAS#

136

CB6

157

DQ40

116

137

CB7

158

DQ60

117

138

159

DQ61

DQ41

118

139

DQ48

160

DQ62

DQ42

119

140

DQ49

161

DQ63

DQ43

120

141

DQ50

162

100

DQ44

121

142

DQ51

163

CK3

101

DQ45

122

BA0

143

164

102

123

A11

144

DQ52

165

SA0

103

DQ46

124

145

166

SA1

104

DQ47

125

CK1

146

167

SA2

105

CB4

126

A12

147

REGE

168

U10

U11

U12

U15

U16

U17

U18

U19

U20

U24

U21

U22

U23

U14

Front View

Back View

U12

U11

U10

U14

U15

U16

U17

U18

U24

U19

U20

U21

U22

U23

Front View

Back View

Standard PCB

Low Profile PCB

PIN 1

PIN 41

PIN 84

PIN 85

PIN125

PIN 168

PIN 1

PIN 41

PIN 84

PIN 85

PIN125

PIN 168

Indicates a V

or V

DDQ

Indicates a V

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

Table 6:

Pin Descriptions

Pin numbers may not correlate with symbol order. Refer to Pin Assignment tables on page 3 fore more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

27, 111, 115

RAS#, CAS#, WE#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.

42, 79, 125, 163

CK0CK3

Input

Clock: CK0 is distributed through an on-board PLL to all
devices. CK1-CK3 are terminated.

128

CKE0

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW)
the CK0 signal. Deactivating the clock provides POWER-
DOWN and SELF REFRESH operation (all device banks idle) or
CLOCK SUSPEND operation (burst access in progress). CKE is
synchronous except after the device enters power-down and
self refresh modes, where CKE becomes asynchronous until
after exiting the same mode. The input buffers, including CK,
are disabled during power-down and self refresh modes,
providing low standby power.

30, 45, 114, 129

S0#S3#

Input

Chip Select: S# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S# are registered HIGH. S# are considered part
of the command code.

28, 29, 46, 47, 112, 113, 130,

131

DQMB0DQMB7

Input

Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.

39, 122

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

33-38, 117-121, 123, 126

A0A12

Input

Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto prcharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory arrary in the respective device bank. A10
sampled during a PRECHARGE command determines
whether the PRECHARGE applies to one device bank (A10
LOW, device bank selected by BA0, BA1) or all device banks
(A10 HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.

165-167

SA0SA2

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

147

REGE

Input

2-5, 7-11, 13-17, 19-20, 55-58,

60, 65-67, 69-72, 74-77, 86-89,

91-95, 97-101, 103-104, 139-

142, 144, 149-151, 153-156,

158-161

DQ0DQ63

Input/

Output

Data I/Os: Data bus.

21, 22, 52, 53, 105, 106, 136,

137

CB0CB7

Input/

Output

Check Bits.

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used
to transfer addresses and data into and data out of the
presence-detect portion of the module.

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

Figure 3: Functional Block Diagram

SA0

SPD

SCL

SDA

SA1

SA2

RS1#

SDRAMs

12pF

CK1-CK3

PLL

SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
SDRAM x 4
REGISTER x 3

CK0

12pF

DQM CS#

U1t

DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3

RDQMB0

DQM CS#

U1b

DQ
DQ
DQ
DQ

DQM CS#

U2t

DQ
DQ
DQ
DQ

DQ4
DQ5
DQ6
DQ7

DQM CS#

U2b

DQ
DQ
DQ
DQ

DQM CS#

U3t

DQ
DQ
DQ
DQ

DQ8
DQ9
DQ10
DQ11

RDQMB1

DQM CS#

U3b

DQ
DQ
DQ
DQ

DQM CS#

U5t

DQ
DQ
DQ
DQ

CB0
CB1
CB2
CB3

DQM CS#

U5b

DQ
DQ
DQ
DQ

RS3#

RDQMB6

DQM CS#

U6t

DQ
DQ
DQ
DQ

DQ16
DQ17
DQ18
DQ19

RDQMB2

DQM CS#

U18t

DQ
DQ
DQ
DQ

DQ48
DQ49
DQ50
DQ51

DQM CS#

U7t

DQ
DQ
DQ
DQ

DQ20
DQ21
DQ22
DQ23

DQM CS#

U17t

DQ
DQ
DQ
DQ

DQ52
DQ53
DQ54
DQ55

RDQMB7

DQM CS#

U8t

DQ
DQ
DQ
DQ

DQ24
DQ25
DQ26
DQ27

RDQMB3

DQM CS#

U16t

DQ
DQ
DQ
DQ

DQ56
DQ57
DQ58
DQ59

DQM CS#

U9t

DQ
DQ
DQ
DQ

DQ28
DQ29
DQ30
DQ31

DQM CS#

U15t

DQ
DQ
DQ
DQ

DQ60
DQ61
DQ62
DQ63

RAS#

CAS#

WE#

CKE0

RRAS#: SDRAMs

RCAS#: SDRAMs

RWE#: SDRAMs

RCKE: SDRAMs

RA0-RA12: SDRAMs

RBA0: SDRAMs

RBA1: SDRAMs

RS0#, RS2#: Module Rank0

RS1#, RS3#: Module Rank1

RDQMB0 - RDQMB7: SDRAMs

A0-A12

BA0

BA1

S0#, S2#

S1#, S3#

DQMB0 - DQMB7

REGE

10K

DQM CS#

U4t

DQ
DQ
DQ
DQ

DQ12
DQ13
DQ14
DQ15

DQM CS#

U4b

DQ
DQ
DQ
DQ

DQM CS#

U23t

DQ
DQ
DQ
DQ

DQ32
DQ33
DQ34
DQ35

RDQMB4

DQM CS#

U23b

DQ
DQ
DQ
DQ

DQM CS#

U22t

DQ
DQ
DQ
DQ

DQ36
DQ37
DQ38
DQ39

DQM CS#

U22b

DQ
DQ
DQ
DQ

DQM CS#

U21t

DQ
DQ
DQ
DQ

DQ40
DQ41
DQ42
DQ43

RDQMB5

DQM CS#

U21b

DQ
DQ
DQ
DQ

DQM

U19t

DQ
DQ
DQ
DQ

CB4
CB5
CB6
CB7

DQM

U19b

DQ
DQ
DQ
DQ

DQM CS#

U20t

DQ
DQ
DQ
DQ

DQ44
DQ45
DQ46
DQ47

DQM CS#

U20b

DQ
DQ
DQ
DQ

RS0#

DQM CS#

U6b

DQ
DQ
DQ
DQ

DQM CS#

U7b

DQ
DQ
DQ
DQ

DQM CS#

U8b

DQ
DQ
DQ
DQ

DQM CS#

U9b

DQ
DQ
DQ
DQ

DQM CS#

U18b

DQ
DQ
DQ
DQ

DQM CS#

U17b

DQ
DQ
DQ
DQ

DQM CS#

U16b

DQ
DQ
DQ
DQ

DQM CS#

U15b

DQ
DQ
DQ
DQ

RS2#

R
E

S
T
E

U12

U41

U14

U10, U11, U24

CS#

CK0

NOTE:

1. All resistor values are 10

W unless otherwise specified.

2. 't' indicates top portion of stacked SDRAM. 'b' indicates bottom portion of stacked SDRAM.
3. Per industry standard, Micron modules utilize various component speed grades, as referenced

in the module part number guide at

www.micron.com/numberguide.

1GB Modules = MT48LC64M4A2TG SDRAMs
2GB Modules = MT48LC128M4A2TG SDRAMs

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

General Description

The MT36LSDT12872 and MT36LSDT25672 are

high-speed CMOS, dynamic random-access, 1GB and
2GB memory modules organized in x72 (ECC) configu-
rations. SDRAM modules use internally configured
quad-bank SDRAM devices with a synchronous inter-
face (all signals are registered on the positive edge of
clock signal CK).

Read and write accesses to SDRAM modules are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank; A0A12,
select the device row). The address bits registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.

SDRAM modules provide for programmable read or

write burst lengths of 1, 2, 4, or 8 locations, or full page,
with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.

SDRAM modules use an internal pipelined architec-

ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the PRECHARGE cycles and provide
seamless, high-speed, random-access operation.

SDRAM modules are designed to operate in 3.3V,

low-power memory systems. An auto refresh mode is
provided, along with a power-saving, power-down
mode. All inputs and outputs are LVTTL-compatible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between device banks in order to hide precharge
time, and the capability to randomly change column
addresses on each clock cycle during a burst access.
For more information regarding SDRAM operation,
refer to the 256Mb and 512Mb SDRAM component
data sheets.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, command descriptions and device opera-
tion.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V

and V

Q (simul-

taneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a
COMMAND INHIBIT or NOP. Starting at some point
during this 100µs period and continuing at least
through the end of this period, Command Inhibit or
NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All device banks must then be precharged, thereby
placing the device in the all device banks idle state.

Once in the idle state, two auto refresh cycles must

be performed. After the auto refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.

PLL and Register Operation

These modules can be operated in either registered

mode (REGE pin HIGH), where the control/address
input signals are latched in the register on one rising
clock edge and sent to the SDRAM devices on the fol-
lowing rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin LOW) where the
input signals pass through the register/buffer to the
SDRAM devices on the same clock.

A phase-lock loop (PLL) on the modules is used to

redrive the clock to the SDRAM devices to minimize
system clock loading. (CK0 is connected to the PLL,
and CK1, CK2, and CK3 are terminated.)

Serial Presence-Detect Operation

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 4, Mode Register Definition
Diagram. The mode register is programmed via the
LOAD MODE REGISTER command and will retain the
stored information until it is programmed again or the
device loses power.

Mode register bits M0M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. Address A12 (M12) is undefined but should be
driven LOW during loading of the mode register.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or
8 locations are available for both the sequential and
the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the

block if a boundary is reached, as shown in the Burst
Definition Table The block is uniquely selected by A1
A9, A11 (1GB), or A1A9, A11, A12 (2GB) when the
burst length is set to two; A2A9, A11 (1GB), or A2A9,
A11, A12 (2GB) when the burst length is set to four; and
by A3A9, A11 (1GB) or A3A9, A11, A12 (2GB) when
the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts
wrap within the page if the boundary is reached, as
shown in Table 7, Burst Definition Table, on page 9.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

A11

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = "0, 0, 0"

to ensure compatibility

with future devices.

A12

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

NOTE:

1. For full-page accesses: y = 2,048 (1GB); y= 4,096 (2GB).
2. For a burst length of two, i will select the block of two

burst; A0 selects the starting column within the block.

3. For a burst length of four, i will select the block of four

burst; A0A1 select the starting column within the
block.

4. For a burst length of eight, i will select the block of

eight burst; A0A2 select the starting column within the
block.

5. For a full-page burst, the full row is selected and i will

select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

7. For a burst length of one, i will select the unique col-

umn to be accessed, and Mode Register bit M3 is
ignored.

8. Ai = A0A9, A11 for 1GB;

Ai = A0A9, A11, A12 for 2GB.

Figure 5: CAS Latency Diagram

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table.

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

Table 7:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page

(y)

n = i

(location 0-

Cn, Cn+1,

Cn+2, Cn+3,

Cn+4..., ...Cn-1,

Cn...

Not supported

Table 8:

CAS Latency Table

Input register adds one clock in registered mode

SPEED

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

CAS LATENCY = 2

CAS LATENCY = 3

-13E

£ 133

£ 143

-133

£ 100

£ 133

-10E

£ 100

N/A

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

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If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a read command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQ will start driving after T1 and the data
will be valid by T2, as shown in the Figure 5, CAS
Latency Diagram, on page 9. Table 8, CAS Latency
Table, on page 9, indicates the operating frequencies at
which each CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
read and write bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with
future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via
M0-M2 applies to both read and write bursts; when

M9 = 1, the programmed burst length applies to

read bursts, but write accesses are single-location

(nonburst) accesses.

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Commands

The Truth Table provides a quick reference of avail-

able commands. This is followed by a written descrip-
tion of each command. For a more detailed

description of commands and operations refer to the
256Mb or 512Mb SDRAM component datasheets.

NOTE:

1. A0A12 provide device row address. BA0, BA1 determine which device bank is made active.
2. A0A9, A11 (1GB) or 0A9, A11, A12(2GB) provide device column address; A10 HIGH enables the auto precharge feature

(nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being
read from or written to.

3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged and

BA0, BA1 are "Don't Care."

4. This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
6. A0A12 define the op-code written to the Mode Register, and should be driven low.
7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

Table 9:

SDRAM Command and DQMB Operation Truth Table

CKE is HIGH for all commands shown except Self Refresh

NAME (FUNCTION)

CS#

RAS# CAS# WE# DQMB

ADDR

DQS NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

4, 5

LOAD MODE REGISTER

Op-Code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

Supply

Relative to Vss . . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to Vss . . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature

(ambient) . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C

Storage Temperature (plastic) . . . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 36W

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 1, 5, 6; notes appear on page 16; V

= V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

, V

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT: Any input: 0V

£ V

(All other pins not under test = 0V)

A0A11, A12,
BA0, BA1, RAS#,
CAS#, and WE#

-10

µA

INPUT LEAKAGE CURRENT: Any input: 0V

£ V

(All other pins not under test = 0V)

DQMB, S#

-5

µA

INPUT LEAKAGE CURRENT: Any input: 0V

£ V

(All other pins not under test = 0V) For inputs:

CKE

-20

µA

OUTPUT LEAKAGE CURRENT: DQs are disabled; 0V

£ V

-10

µA

OUTPUT LEVELS: Output High Voltage (I

OUT

= -4mA)

2.4

Output Low Voltage (I

OUT

= 4mA)

0.4

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Table 11: I

Specifications and Conditions 1GB

SDRAM components only; Notes: 1, 5, 6, 11, 13; notes appear on page 16; V

= V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYM

MAX

UNITS

NOTES

-13E

-133

-10E

OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;

RC =

RC (MIN)

2,466

2,286

3, 18, 19,

STANDBY CURRENT: Power-Down Mode; All device banks idle;
CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device

banks active after

RCD met; No accesses in progress

756

3, 12, 19,

OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE;
All device banks active

2,466

3, 18, 19,

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

10,260

9,720

3, 12,

CS# = HIGH; CKE = HIGH

RFC = 7.8125µs

126

18, 19,

30, 31

SELF REFRESH CURRENT: CKE

£ 0.2V

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in power-down mode.
b - Value calculated reflects all module ranks in this operating condition.

Table 12: I

Specifications and Conditions 2GB

SDRAM components only; Notes: 1, 5, 6, 11, 13; notes appear on page 16; V

= V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYM

MAX

UNITS

NOTES

-13E

-133

-10E

OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;

RC =

RC (MIN)

3,906

3,636

3, 18, 19,

STANDBY CURRENT: Power-Down Mode; All device banks idle;
CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device

banks active after

RCD met; No accesses in progress

1,476

3, 12, 19,

OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE;
All device banks active

3,276

3, 18, 19,

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

14,400 13,320 13,320

3, 12,

CS# = HIGH; CKE = HIGH

RFC = 7.8125µs

360

18, 19,

30, 31

SELF REFRESH CURRENT: CKE

£ 0.2V

216

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in power-down mode.
b - Value calculated reflects all module ranks in this operating condition.

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Table 13: Capacitance

Note: 2; notes appear on page 16

PARAMETER

SYMBOL

MIN

TYP

MAX

UNITS

Input Capacitance:

A0-A12, BA0, BA1, RAS#, CAS#, WE#

Input Capacitance:

CKE0

Input Capacitance:

CK0

Input Capacitance:

CK1-CK3

Input Capacitance:

S#, DQMB

Input Capacitance:

REGE

Input Capacitance:

SCL, SA0-SA2

Input/Output Capacitance: DQ, CB, SDA

Table 14: SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions

Notes: 5, 6, 8, 9, 11; notes appear on page 16

AC CHARACTERISTICS

-13E

-133

-10E

UNITS NOTES

PARAMETER

SYM

MIN

MAX

MIN

MAX

MIN

MAX

Access time from CLK (pos. edge)

CL= 3

AC(3)

5.4

CL= 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL= 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setupt ime

CMS

1.5

Data-in hold time

0.8

Data-ins etup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period

REF

AUTO REFRESH period

RFC

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PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK +

7ns

1 CLK +

7.5ns

1 CLK +

7ns

Exit SELF REFRESH to ACTIVE command

XSR

Table 14: SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (Continued)

Notes: 5, 6, 8, 9, 11; notes appear on page 16

AC CHARACTERISTICS

-13E

-133

-10E

UNITS NOTES

PARAMETER

SYM

MIN

MAX

MIN

MAX

MIN

MAX

Table 15: AC Functional Characteristics

Notes: 5, 6, 7, 8, 9, 11; notes appear on page 16

PARAMETER

SYMBOL

-13E

-133

-10E

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

14, 32

CKE to clock enable or power-down exit setup mode

PED

14, 32

DQM to input data delay

DQD

17, 32

DQM to data mask during WRITEs

DQM

17, 32

DQM to data high-impedance during READs

DQZ

17, 32

WRITE command to input data delay

DWD

17, 32

Data-in to ACTIVE command

DAL

15, 21,

Data-in to PRECHARGE command

DPL

16, 21,

Last data-in to burst STOP command

BDL

17, 32

Last data-in to new READ/WRITE command

CDL

17, 32

Last data-in to PRECHARGE command

RDL

16, 21,

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE
command

CL=3

ROH(3)

17, 32

CL = 2

ROH(2)

17, 32

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Notes

1. All voltages referenced to V

2. This parameter is sampled. V

= V

Q = +3.3V

±0.3V; f = 1 MHz, T

= 25°C; pin under test biased

at 1.4V.

3. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to

indicate cycle time at which proper operation
over the full temperature range is ensured; (0°C

£ +70°C).

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

Vss and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be

repeated any time the

REF refresh requirement is

exceeded.

7. AC characteristics assume

T = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V,

using a measurement reference level of 1.5V. If the
input transition time is longer than 1ns, then the
timing is measured from V

(MAX) and V

(MIN)

and no longer at the 1.5V midpoint. CLK should
always be referenced to crossover. Refer to Micron
Technical Note TN-48-09.

12. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

13. I

specifications are tested after the device is

properly initialized.

14. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by

WR +

RP; clock(s)

specified as a reference only at minimum cycle
rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 10ns for -10E, and

CK = 7.5ns for -

133 and -13E.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

£ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

£ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7ns for -13E; 7.5ns for -133

and 7ns for -10E after the first clock delay, after
the last WRITE is executed.

25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.

AC for -133/-13E at CL = 3 with no load is 4.6ns

and is guaranteed by design.

28. Parameter guaranteed by design.
29. The value for

RAS used in -13E speed grade mod-

ules is calculated from

RC -

RP.

30. For -10E, CL= 2 and

CK = 10ns; for -133, CL = 3

and

CK = 7.5ns; for -13E, CL = 2 and

CK = 7.5ns.

31. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

32. This AC timing function will show an extra clock

cycle when in registered mode.

33. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

34. For operating frequencies

£ 45 MHz,

CKS = 3.0ns.

50pF

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NOTE:

1. SSC = Spread Spectrum Clock. the use of SSC synthesizers on the system motherboard will reduce EMI.
2. Skew is defined as the total clock skew between any two outputs and is therefore specified as a maximum only.

Table 16: Register Timing Requirements and Switching Characteristics

SYMBOL

PARAMETER

CONDITION

0°C

£ T

£ 70ºC

= +3.3V ±0.3V

UNITS

MIN

MAX

SSTL

bit pattern by

JESD82-2

clock

Clock Frequency

150

240

MHz

pd1

Propagation Delay, Single Rank

(CK to Output)

50pF to GND and

50 Ohms to Vtt

1.4

3.5

pd2

Propagation Delay, DualRank

(CK to Output)

30pF to GND and

W to V

0.7

2.4

Pulse Duration

CK, HIGH or LOW

3.3

Setup Time

Data Before CK HIGH

.75

Hold Time

Data After CK HIGH

.75

Table 17: PLL Clock Driver Timing Requirements And Switching Characteristics

PARAMETER

SYMBOL

0°C

£ T

£ 70ºC

= +3.3V ±0.3V

UNITS

NOTES

MIN

MAX

Operating Clock Frequency

140

MHz

Inupt Duty Cycle

Cycle to Cycle Jitter

JIT

-75

Static Phase Offeset

-150

150

SSC Induced Skew

SSC

150

1, 2

Output to Output Skew

150

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Figure 6: Component Case Temperature vs. Airflow

NOTE:

1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the MT36LSDT12872G and

MT36LSDT25672G modules when installed in a system.

2. The component case temperature measurements shown above are obtained experimentally. The system used for exper-

imental purposes is a dual-processor 600 MHz work station, fully loaded with four MT36LSDT12872G modules. Case tem-
peratures charted represent worst-case component locations on modules installed in the internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard
for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test
chamber.

4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

max

- memory stress software

ave

- 3D gaming software

ave

- memory stress software

Minimum Air Flow

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SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 7, Data Validity, and Figure 8, Defini-
tion of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 9, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 7: Data Validity

Figure 8: Definition of Start and Stop

Figure 9: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

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Table 18: EEPROM Device Select Code

The most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 19: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

VIH or VIL

Start, Device Select, RW = 1

RandomAddressRead

VIH or VIL

Start, Device Select, RW= 0, Address

VIH or VIL

RESTART, Device Select, RW= 1

Sequential Read

VIH or VIL

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

£ 16

START, Device Select, RW = 0

Table 20: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V

; V

= +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

-10

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

-10

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V; All other inputs = V

or V

CCS

µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz

Write

Read

3
1

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SD36C128_256x72G_C.fm - Rev. C 5/03 EN

Figure 10: SPD EEPROM Timing Diagram

NOTE:

1. To aviod spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising

edge of SDA.

2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

Table 21: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

= +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.2

0.9

µs

Time the bus must be free before a new transition can start

BUF

1.3

µs

Data-out hold time

200

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

0.6

µs

Clock HIGH period

HIGH

0.6

µs

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

LOW

1.3

µs

SDA and SCL rise time

0.3

µs

SCL clock frequency

SCL

400

KHz

Data-in setup time

SU:DAT

100

Start condition setup time

SU:STA

0.6

µs

Stop condition setup time

SU:STO

0.6

µs

WRITE cycle time

WRC

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

Table 22: Serial Presence-Detect Matrix

"1"/"0": Serial data, "driven to HIGH"/"driven to LOW"; V

= +3.3V ±0.3V

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT36LSDT12872

MT36LSDT25672

Number of Bytes Used by Micron

128

Total Number of SPD Memory Bytes

256

Memory Type

SDRAM

Number of Row Addresses

Number of Column Addresses

11 or 12

Number of Module Ranks

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

LVTTL

SDRAM Cycle Time,

CK (CAS Latency = 3)

7ns (-13E)

7.5ns (-133)

8ns (-10E)

70
75
80

SDRAM Access from CLK,

AC (CAS Latency = 3)

5.4ns (-13E/-133)

6ns (-10E)

54
60

Module Configuration Type

ECC

Refresh Rate/Type

7.81µs/SELF

SDRAM Width (Primary SDRAM)

Error-checking SDRAM Data Width

Minimum Clock Delay from Back-to-Back Random

Column Addresses,

CCD

Burst Lengths Supported

1, 2, 4, 8, PAGE

Number of Banks on SDRAM Device

CAS Latencies Supported

2, 3

CS Latency

WE Latency

SDRAM Module Attributes

-13E/-133/-10E

SDRAM Device Attributes: General

SDRAM Cycle Time,

(CAS Latency = 2) 10 (-133/-10E) A0

7.5ns (-13E)

10ns (-133/-10E)

SDRAM Access from CLK,

(CAS Latency = 2)

5.4ns (-13E)

6ns (-10E)

54
60

SDRAM Cycle Time,

(CAS Latency = 1)

SDRAM Access from CLK,

(CAS Latency = 1)

Minimum Row Precharge Time,

15ns (-13E)

20ns (-133/-10E)

0F
14

Minimum Row Active to Row Active,

RRD

14ns (-13E)
15ns (-133)
20ns (-10E)

0E
0F
14

Minimum RAS# to CAS# Delay,

RCD

15ns (-13E)

20ns (-133/-10E)

0F
14

Minimum RAS# Pulse Width,

RAS (See note 1)

45ns (-13E)
44ns (-133)
50ns (-10E)

2C
32

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

NOTE:

1. The value of

RAS used for the -13E module is calculated from

RC -

RP. Actual device spec. value is 37ns.

Module Rank Density

512MB / 1GB

Command and Address Setup Time,

AS,

CMS

1.5ns (-13E/-133)

2ns (-10E)

15
20

Command and Address Hold Time,

AH,

CMH

0.8ns (-13E/-133)

1ns (-10E)

08
10

Data Signal Input Setup Time,

1.5ns (-13E/-133)

2ns (-10E)

15
20

Data Signal Input Hold Time,

0.8ns (-13E/-133)

1ns (-10E)

08
10

36-61

Reserved

SPD Revision

REV. 1.2

Checksum For Bytes 0-62

-13E
-133
-10E

3C
84

78
BE
06

Manufacturer's JEDEC ID Code

MICRON

65-71

Manufacturer's JEDEC ID Code (Cont.)

Manufacturing Location

0109

73-90

Module Part Number (ASCII)

Variable Data

PCB Identification Code

111

010B

Identification Code (Cont.)

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98

Module Serial Number

Variable Data

99-125

Manufacturer-specific Data (RSVD)

126

System Frequency

100/133 MHz

127

SDRAM Component & Clock Detail

Table 22: Serial Presence-Detect Matrix (Continued)

"1"/"0": Serial data, "driven to HIGH"/"driven to LOW"; V

= +3.3V ±0.3V

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT36LSDT12872

MT36LSDT25672

1GB, 2GB (x72, ECC)

168-PIN REGISTERED SDRAM DIMM

09005aef80b18348

Micron Technology, Inc., reserves the right to change products or specifications without notice..

SD36C128_256x72G_C.fm - Rev. C 5/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 12: Low-Profile 168-Pin DIMM Dimensions

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete
power supply and temperature range for production

devices. Although considered final, these specifica-
tions are subject to change, as further product devel-
opment and data characterization sometimes occur.

FRONT VIEW

BACK VIEW

5.256 (133.50)
5.244 (133.20)

0.320 (8.13)

MAX

0.700 (17.78)

1.206 (30.63)
1.194 (30.33)

PIN 1

0.250 (6.35)

4.550 (115.57)

0.050 (1.27)

0.040 (1.02)

0.039 (1.00) R(2X)

PIN 84

0.118 (3.00)

0.079 (2.00) R

(2X)

0.118 (3.00)

(2X)

PIN 168

PIN 85

2.625 (66.68)

1.661 (42.18)

0.128 (3.25)

0.118 (3.00)

(2X)

0.054 (1.37)
0.046 (1.17)

U12

U11

U10

U14

U15

U16

U17

U18

U24

U19

U20

U21

U22

U23

MAX

MIN

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