PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef8075ebf6
DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

REGISTERED DDR
SDRAM DIMM

MT36VDDF12872 1GB
MT36VDDF25672 2GB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· 184-pin, dual in-line memory module (DIMM)
· Fast data transfer rates PC1600, PC2100, or PC 2700
· Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR

SDRAM components

· Registered Inputs with one-clock delay
· Phase-lock loop (PLL) clock driver to reduce loading
· ECC, 1-bit error detection and correction
· 1GB (128 Meg x 72), 2GB, (256 Meg x 72)
· V

= V

Q = +2.5V

· V

DDSPD

= +2.3V to +3.6V

· 2.5V I/O (SSTL_2 compatible)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs;

centeraligned with data for WRITEs

· Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

· Bidirectional data strobe (DQS) transmitted/

received with data--i.e., source-synchronous data
capture

· Differential clock inputs CK and CK#
· Four internal device banks for concurrent operation
· Programmable burst lengths: 2, 4, or 8
· Auto precharge option
· Auto Refresh and Self Refresh Modes
· 7.8125µs maximum average periodic refresh

interval

· Serial Presence Detect (SPD) with EEPROM
· Programmable READ CAS latency
· Gold edge contacts

Figure 1: 184-Pin DIMM (MO-206)

NOTE:

1. Contact Micron for availability of lead-free prod-

ucts.

2. CL = CAS (READ) Latency. Registered Mode will

add one clock cycle to CL.

Table 1:

Address Table

1GB

2GB

Refresh Count

Row Addressing

8K (A0A12)

Device Bank Addressing

4 (BA0, BA1)

Device Configuration

64 Meg x 4

128 Meg x 4

Column Addressing

2K (A0A9,

A11)

4K (A0A9,

A11, A12)

Module Rank Addressing

2 (S0#, S1#)

OPTIONS

MARKING

· Package

184-pin DIMM (Standard)

184-pin DIMM (Lead-free)1

· Frequency/CAS Latency

6ns/166MHz (333MT/s)/CL = 3

-335

7.5ns/133 MHz (266 MT/s)/CL = 2

-262

7.5ns/133 MHz (266 MT/s)/CL = 2

-26A

7.5ns/133 MHz (266 MT/s)/CL = 2.5

-265

10ns/100 MHz (200 MT/s)/CL = 2

-202

· PCB

Standard 1.7in. (43.18mm)

See page 2 note

Low-Profile 1.2in. (30.48mm)

See page 2 note

Low Profile (1GB) 1.2in. (30.48mm)

Standard 1.7in. (43.18mm)

Low-Profile (2GB) 1.2in. (30.48mm)

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Table 2:

Part Numbers and Timing Parameters

PART NUMBER

MODULE
DENSITY

CONFIGURATION

MODULE

BANDWIDTH

MEMORY CLOCK/

DATA BIT RATE

LATENCY

(CL -

RCD -

RP)

MT36VDDF12872G-335__

1GB

128 Meg x 72

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT36VDDF12872Y-335__

1GB

128 Meg x 72

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT36VDDF12872G-262__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDF12872Y-262__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDF12872G-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDF12872Y-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDF12872G-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDF12872Y-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDF12872G-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDF12872Y-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDF25672G-335__

2GB

256 Meg x 72

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT36VDDF25672Y-335__

2GB

256 Meg x 72

2.7 GB/s

6ns/333 MT/s

2.5-3-3

MT36VDDF25672G-262__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDF25672Y-262__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDF25672G-26A__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDF25672Y-26A__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDF25672G-265__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDF25672Y-265__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDF25672G-202__

2GB

256 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDF25672Y-202__

2GB

256 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT36VDDF12872G-265B1.

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 2: Pin Locations (Standard PCB)

Table 3:

Pin Assignment
(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

DQ17

DQS8

DQ0

DQS2

CB2

DQ48

DQ1

DQ49

DQS0

DQ18

CB3

DQ2

BA1

DNU

DDQ

DQ32

DNU

DQ3

DQ19

DDQ

DQ33

DQS6

RESET#

DQ24

DQS4

DQ50

DQ34

DQ51

DQ8

DQ25

DQ9

DQS3

BA0

DQS1

DQ35

DQ56

DDQ

DQ40

DQ57

DNU

DQ26

DDQ

DNU

DQ27

WE#

DQS7

DQ41

DQ58

DQ10

CAS#

DQ59

DQ11

CKE0

CB0

DQS5

DNU

DDQ

CB1

DQ42

SDA

DQ16

DQ43

SCL

Table 4:

Pin Assignment
(184-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

116

139

162

DQ47

DQ4

117

DQ21

140

DQS17

163

DQ5

118

A11

141

A10

164

DDQ

119

DQS11

142

CB6

165

DQ52

DQS9

120

143

DDQ

166

DQ53

DQ6

121

DQ22

144

CB7

167

DQ7

122

145

168

100

123

DQ23

146

DQ36

169

DQS15

101

124

147

DQ37

170

DQ54

102

125

148

171

DQ55

103

126

DQ28

149

DQS13

172

DDQ

104

DDQ

127

DQ29

150

DQ38

173

105

DQ12

128

DDQ

151

DQ39

174

DQ60

106

DQ13

129

DQS12

152

175

DQ61

107

DQS10

130

153

DQ44

176

108

131

DQ30

154

RAS#

177

DQS16

109

DQ14

132

155

DQ45

178

DQ62

110

DQ15

133

DQ31

156

DDQ

179

DQ63

111

CKE1

134

CB4

157

S0#

180

DDQ

112

DDQ

135

CB5

158

S1#

181

SA0

113

136

DDQ

159

DQS14

182

SA1

114

DQ20

137

CK0

160

183

SA2

115

A12

138

CK0#

161

DQ46

184

DDSPD

U10

U39

U11

U12

U13

U14

U37

U38

U15

U16

U17

U18

U19

U20

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

U31

U32

U40

U33

U34

U35

U36

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1

PIN 52

PIN 53

PIN 92

Front View

Back View

Indicates a V

or V

DDQ

Indicates a V

Standard PCB 1.7in. (43.18mm)

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 3: Pin Locations (Low-Profile PCB)

Table 5:

Pin Assignment
(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

DQ17

DQS8

DQ0

DQS2

CB2

DQ48

DQ1

DQ49

DQS0

DQ18

CB3

DQ2

BA1

DNU

DDQ

DQ32

DNU

DQ3

DQ19

DDQ

DQ33

DQS6

RESET#

DQ24

DQS4

DQ50

DQ34

DQ51

DQ8

DQ25

DQ9

DQS3

BA0

DQS1

DQ35

DQ56

DDQ

DQ40

DQ57

DNU

DQ26

DDQ

DNU

DQ27

WE#

DQS7

DQ41

DQ58

DQ10

CAS#

DQ59

DQ11

CKE0

CB0

DQS5

DNU

DDQ

CB1

DQ42

SDA

DQ16

DQ43

SCL

Table 6:

Pin Assignment
(184-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

116

139

162

DQ47

DQ4

117

DQ21

140

DQS17

163

DQ5

118

A11

141

A10

164

DDQ

119

DQS11

142

CB6

165

DQ52

DQS9

120

143

DDQ

166

DQ53

DQ6

121

DQ22

144

CB7

167

DQ7

122

145

168

100

123

DQ23

146

DQ36

169

DQS15

101

124

147

DQ37

170

DQ54

102

125

148

171

DQ55

103

126

DQ28

149

DQS13

172

DDQ

104

DDQ

127

DQ29

150

DQ38

173

105

DQ12

128

DDQ

151

DQ39

174

DQ60

106

DQ13

129

DQS12

152

175

DQ61

107

DQS10

130

153

DQ44

176

108

131

DQ30

154

RAS#

177

DQS16

109

DQ14

132

155

DQ45

178

DQ62

110

DQ15

133

DQ31

156

DDQ

179

DQ63

111

CKE1

134

CB4

157

S0#

180

DDQ

112

DDQ

135

CB5

158

S1#

181

SA0

113

136

DDQ

159

DQS14

182

SA1

114

DQ20

137

CK0

160

183

SA2

115

A12

138

CK0#

161

DQ46

184

DDSPD

U19

U10

U11

U10

U20

U18

U17

U16

U15

U14

U13

U21

U22

U23

U24

U25

U26

U27

U37

U28

U29

U30

U31

U32

U33

U40

U39

U38

U36

U35

U34

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1

PIN 52

PIN 53

PIN 92

Indicates a V

or V

Q pin

Indicates a V

U10

U20

U19

U18

U17

U16

U15

U14

U13

U12

U11

U21

U22

U23

U24

U25

U26

U27

U28

U29

U30

U31

U40

U39

U38

U37

U36

U35

U34

U33

U32

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1

PIN 52

PIN 53

PIN 92

Front View

Back View

Low-Profile PCBs 1.2in. (30.48mm)

Front View

Back View

1GB

2GB

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Table 7:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

ESET

Input

Asynchronously forces all registered ouputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure CKE
is LOW and DQs are High-Z.

63, 65, 154

WE#, CAS#, RAS#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.

137, 138

CK0, CK0#

Input

Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK,and negative edge of CK#. Output data (DQ and
DQS) is referenced to the crossings of CK and CK#.

21, 111

CKE0, CKE1

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE
LOW provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all device banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any device bank). CKE is synchronous for
POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE
is asynchronous for SELF REFRESH exit and for disabling the
outputs. CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE) are
disabled during POWER-DOWN. CKE is an SSTL_2 input but will
detect an LVCMOS LOW level after V

is applied and until CKE

is first brought HIGH. After CKE is brought HIGH, it becomes an
SSTL_2 input only.

157, 158

S0#, S1#

Input

Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of the
command code.

52, 59

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

27, 29, 32, 37, 41, 43, 48,

115, 118, 122, 125, 130,

141

A0A12

Input

Address Inputs: Provide the row address for ACTIVE commands,
and the column address and auto precharge bit (A10) for READ/
WRITE commands, to select one location out of the memory
array in the respective device bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE
applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET
command. BA0 and BA1 define which mode register (mode
register or extended mode register) is loaded during the LOAD
MODE REGISTER command.

5, 14, 25, 36, 47, 56, 67,

78, 86, 97, 107, 119, 129,

140, 149, 159, 169, 177

DQS0DQS17

Input/

Output

Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.

44, 45, 49, 51, 134, 135,

142, 144

CB0CB7

Input/

Output

Check Bits: ECC, 1-bit error detection and correction.

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

2, 4, 6, 8, 12,13, 19, 20,

23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,

105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,

175, 178, 179

DQ0-DQ63

Input/

Output

Data I/Os: Data bus.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.

181, 182, 183

SA0-SA2

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.

REF

Input

SSTL_2 reference voltage.

15, 22, 30, 54, 62, 77, 96,

104, 112, 128, 136, 143,

156, 164, 172, 180

DDQ

Supply

DQ Power Supply: +2.5V ±0.2V.

7, 38, 46, 70, 85, 108, 120,

148, 168

Supply

Power Supply: +2.5V ±0.2V.

3, 11, 18, 26, 34, 42, 50,

58, 66, 74, 81, 89, 93, 100,

116, 124, 132, 139, 145,

152, 160, 176

Supply

Ground.

184

DDSPD

Supply

Serial EEPROM positive power supply: +2.3V to +3.6V.

16, 17, 75, 76, 90

DNU

Do Not Use: Thes pins are not connected on these modules, but
are assigned pins on other modules in this product family

9, 71, 82, 101, 102, 103,

113, 163, 167, 173

No Connect: These pins should be left unconnected.

Table 7:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 4: Standard PCB Functional Block Diagram

SA0

SPD

SCL

SDA

SA1

SA2

S0#

PLL

DDR SDRAM x 4

CK0

DQS CS#

U11

DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3

DQS0

DQS CS#

U36

DQS CS#

DQ4
DQ5
DQ6
DQ7

DQS CS#

U28

DQS CS#

U12

DQ8
DQ9
DQ10
DQ11

DQS1

DQS CS#

U35

DQS CS#

CB0
CB1
CB2
CB3

DQS CS#

U24

DQS6

DQS CS#

U13

DQ16
DQ17
DQ18
DQ19

DQS2

DQS CS#

U17

DQ48
DQ49
DQ50
DQ51

DQS CS#

DQ20
DQ21
DQ22
DQ23

DQS CS#

DQ52
DQ53
DQ54
DQ55

DQS7

DQS CS#

U14

DQ24
DQ25
DQ26
DQ27

DQS3

DQS CS#

U18

DQ56
DQ57
DQ58
DQ59

DQS CS#

DQ28
DQ29
DQ30
DQ31

DQS CS#

U10

DQ60
DQ61
DQ62
DQ63

RAS#

CAS#

CKE0

CKE1

WE#

A0-A12

BA0

BA1

S0#

S1#

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs, Rank 0

CKE1: DDR SDRAMs, Rank 1

WE#: DDR SDRAMs

A0-A12: DDR SDRAMs

BA0: DDR SDRAMs

BA1: DDR SDRAMs

S0#: DDR SDRAMs, Rank 0

S1#: DDR SDRAMs, Rank1

Reset

DQS CS#

DQ12
DQ13
DQ14
DQ15

DQS CS#

U27

DQS CS#

U15

DQ32
DQ33
DQ34
DQ35

DQS4

DQS CS#

U32

DQS CS#

DQ36
DQ37
DQ38
DQ39

DQS CS#

U22

DQS CS#

U16

DQ40
DQ41
DQ42
DQ43

DQS5

DQS CS#

U31

DQS CS#

CB4
CB5
CB6
CB7

DQS CS#

U23

DQS CS#

DQ44
DQ45
DQ46
DQ47

DQS CS#

U21

S1#

DQS CS#

U34

DQS CS#

U26

DQS CS#

U33

DQS CS#

U25

DQS CS#

U30

DQS CS#

U20

DQS CS#

U29

DQS CS#

U19

R
E

S
T
E

U40

U39

U37, U38

DQS9

DQS17

DQS15

DQS16

DQS12

DQS11

DQS8

DQS10

DQS14

DQS13

REF

DDR SDRAMs

DDQ

DDR SDRAMs

CK0#

DQ
DQ
DQ
DQ

CK0

120

CK0#

DDSPD

SPD EEPROM

MT46V64M4FJ = DDR SDRAM

for MT36VDDF12872

MT46V128M4F = DDR SDRAM for MT36VDDF25672

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as refer-

enced in the Module Part Numbering Guide at

www.micron.com/numberguide

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 5: Low-Profile PCB Functional Block Diagram (1GB)

SA0

SPD

SCL

SDA

SA1

SA2

S0#

PLL

DDR SDRAM x 4

CK0

DQS CS#

DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3

DQS0

DQS CS#

U31

DQS CS#

U11

DQ4
DQ5
DQ6
DQ7

DQS CS#

U40

DQS CS#

DQ8
DQ9
DQ10
DQ11

DQS1

DQS CS#

U30

DQS CS#

U35

CB0
CB1
CB2
CB3

DQS CS#

U16

DQS6

DQS CS#

DQ16
DQ17
DQ18
DQ19

DQS2

DQS CS#

U22

DQ48
DQ49
DQ50
DQ51

DQS CS#

U13

DQ20
DQ21
DQ22
DQ23

DQS CS#

U33

DQ52
DQ53
DQ54
DQ55

DQS7

DQS CS#

DQ24
DQ25
DQ26
DQ27

DQS3

DQS CS#

U21

DQ56
DQ57
DQ58
DQ59

DQS CS#

U14

DQ28
DQ29
DQ30
DQ31

DQS CS#

U32

DQ60
DQ61
DQ62
DQ63

RAS#

CAS#

CKE0

CKE1

WE#

A0-A12

BA0

BA1

S0#

S1#

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs, Rank 0

CKE1: DDR SDRAMs, Rank 1

WE#: DDR SDRAMs

A0-A12: DDR SDRAMs

BA0: DDR SDRAMs

BA1: DDR SDRAMs

S0#: DDR SDRAMs, Rank 0

S1#: DDR SDRAMs, Rank1

Reset

DQS CS#

U12

DQ12
DQ13
DQ14
DQ15

DQS CS#

U39

DQS CS#

U25

DQ32
DQ33
DQ34
DQ35

DQS4

DQS CS#

U24

DQ36
DQ37
DQ38
DQ39

DQS CS#

U34

DQ40
DQ41
DQ42
DQ43

DQS5

DQS CS#

U17

DQS CS#

CB4
CB5
CB6
CB7

DQS CS#

U17

DQS CS#

U23

DQ44
DQ45
DQ46
DQ47

DQS CS#

S1#

DQS CS#

U29

DQS CS#

U38

DQS CS#

U28

DQS CS#

U37

DQS CS#

U18

DQS CS#

U10

DQS CS#

U20

R
E

S
T
E

U26

U19

U15, U36

DQS9

DQS17

DQS15

DQS16

DQS12

DQS11

DQS8

DQS10

DQS14

DQS13

REF

DDR SDRAMs

DDQ

DDR SDRAMs

CK0#

DQ
DQ
DQ
DQ

CK0

120

CK0#

DDSPD

SPD EEPROM

MT46V64M4FJ = DDR SDRAM

for MT36VDDF12872

MT46V128M4F = DDR SDRAM for MT36VDDF25672

NOTE:

1. All resistor values are 18

W unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as ref-

erenced in the Module Part Numbering Guide at

www.micron.com/number-

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 6: Low-Profile PCB Functional Block Diagram (2GB)

SA0

SPD

SCL

SDA

SA1

SA2

S0#

PLL

DDR SDRAM x 4

CK0

DQS CS#

DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3

DQS0

DQS CS#

U33

DQS CS#

DQ4
DQ5
DQ6
DQ7

DQS CS#

U32

DQS CS#

U13

DQ8
DQ9
DQ10
DQ11

DQS1

DQS CS#

U40

DQS CS#

U26

CB0
CB1
CB2
CB3

DQS CS#

DQS6

DQS CS#

DQ16
DQ17
DQ18
DQ19

DQS2

DQS CS#

U34

DQ48
DQ49
DQ50
DQ51

DQS CS#

U14

DQ20
DQ21
DQ22
DQ23

DQS CS#

U23

DQ52
DQ53
DQ54
DQ55

DQS7

DQS CS#

DQ24
DQ25
DQ26
DQ27

DQS3

DQS CS#

U21

DQ56
DQ57
DQ58
DQ59

DQS CS#

U15

DQ28
DQ29
DQ30
DQ31

DQS CS#

U22

DQ60
DQ61
DQ62
DQ63

RAS#

CAS#

CKE0

CKE1

WE#

A0-A12

BA0

BA1

S0#

S1#

RAS#: DDR SDRAMs

CAS#: DDR SDRAMs

CKE0: DDR SDRAMs, Bank 0

CKE1: DDR SDRAMs, Bank 1

WE#: DDR SDRAMs

A0-A12: DDR SDRAMs

BA0: DDR SDRAMs

BA1: DDR SDRAMs

S0#: DDR SDRAMs, Bank 0

S1#: DDR SDRAMs, Bank1

Reset

DQS CS#

DQ12
DQ13
DQ14
DQ15

DQS CS#

U31

DQS CS#

U25

DQ32
DQ33
DQ34
DQ35

DQS4

DQS CS#

U36

DQ36
DQ37
DQ38
DQ39

DQS CS#

U17

DQS CS#

U24

DQ40
DQ41
DQ42
DQ43

DQS5

DQS CS#

CB4
CB5
CB6
CB7

DQS CS#

U28

DQS CS#

U35

DQ44
DQ45
DQ46
DQ47

DQS CS#

U18

S1#

DQS CS#

U30

DQS CS#

U39

DQS CS#

U29

DQS CS#

U38

DQS CS#

U20

DQS CS#

U10

DQS CS#

U12

DQS CS#

U11

R
E

S
T
E

U27

U19

U16, U37

DQS9

DQS17

DQS15

DQS16

DQS12

DQS11

DQS8

DQS10

DQS14

DQS13

REF

DDR SDRAMs

DDQ

DDR SDRAMs

CK0#

DQ
DQ
DQ
DQ

CK0

120

CK0#

DDSPD

SPD EEPROM

NOTE:

1. All resistor values are 18

W unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as refer-

enced in the Module Part Numbering Guide at

www.micron.com/numberguide

MT46V64M4FJ = DDR SDRAM

for MT36VDDF12872

MT46V128M4F = DDR SDRAM for MT36VDDF25672

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

General Description

MT36VDDF12872 and MT36VDDF25672 are high-

speed CMOS, dynamic random-access, 1GB and 2GB
memory module organized in x72 (ECC) configuration.
DDR SDRAM modules use internally configured quad-
bank DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for DDR SDRAM modules effectively con-
sists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.

DDR SDRAM modules operate from differential

clock inputs (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0A12 select
device row). The address bits registered coincident
with the READ or WRITE command are used to select
the device bank and starting device column location
for the burst access.

DDR SDRAM modules provide for programmable

read or write burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 256Mb or 512Mb DDR SDRAM component data
sheet.

PLL and Register Operation

DDR SDRAM modules operate in registered mode,

where the command/address input signals are latched
in the registers on the rising clock edge and sent to the
DDR SDRAM devices on the following rising clock
edge (data access is delayed by one clock cycle). A
phase-lock loop (PLL), on the module, receives and
redrives the differential clock signals (CK, CK#) to the
DDR SDRAM devices. The registers and PLL minimize
system and clock loading.

Serial Presence-Detect Operation

These DDR SDRAM modules incorporate serial

presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile
storage device contains 256 bytes. The first 128 bytes
can be programmed by Micron to identify the module
type and various SDRAM organizations and timing
parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/
WRITE operations between the master (system logic)
and the slave EEPROM device (DIMM) occur via a
standard I

C bus using the DIMM's SCL (clock) and

SDA (data) signals, together with SA (2:0), which pro-
vide eight unique DIMM/EEPROM addresses. Write
protect (WP) is tied to ground on the module, perma-
nently disabling hardware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM device. This
definition includes the selection of a burst length, a
burst type, a CAS latency and an operating mode, as
shown in Figure 7, Mode Register Definition Diagram,
on page 11. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Mode register bits A0A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A12
specify the operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Figure 7, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1Ai when the burst length is set to two,
by A2Ai when the burst length is set to four and by
A3Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see Note 5, of Table 8, Burst Definition
Table, on page 12). The remaining (least significant)
address

The remaining (least significant) address bit(s) is

(are) used to select the starting location within the
block. The programmed burst length applies to both
READ and WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Figure 8, Burst
Definition Table, on page 12.

Figure 7: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA1 and BA0)

must be 0, 0 to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. For a burst length of two, A1Ai select the two-data-

element block; A0 selects the first access within the
block.

2. For a burst length of four, A2Ai select the four-data-

element block; A0A1 select the first access within the
block.

3. For a burst length of eight, A3Ai select the eight-data-

element block; A0A2 select the first access within the
block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

5. i = 9, 11 (1GB)

i = 9, 11, 12 (2GB)

Figure 8: CAS Latency Diagram

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 8, CAS
Latency Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Figure 9,
CAS Latency (CL) Table, indicates the operating fre-
quencies at which each CAS latency setting can be
used.

Reserved states should not be used as unknown oper-

ation or incompatibility with future versions may result.

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7A12
each set to zero, and bits A0A6 set to the desired val-
ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9A12 each set
to zero, bit A8 set to one, and bits A0A6 set to the
desired values. Although not required by the Micron
device, JEDEC specifications recommend when a
LOAD MODE REGISTER command is issued to reset
the DLL, it should always be followed by a LOAD
MODE REGISTER command to select normal operat-
ing mode.

Table 8:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES

WITHIN A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 9:

CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED

CL = 2

CL = 2.5

-335

£ f £ 133

£ f £ 167

-262

£ f £ 133

-26A

£ f £ 133

-265

£ f £ 100

£ f £ 133

-202

£ f £ 100

£ f £ 125

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

All other combinations of values for A7A12 are

reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 9, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having

disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.

Figure 9: Extended Mode Register

Definition Diagram

NOTE:

1. BA1 and BA0 (E14 and E13) must be "0, 1" to select the

Extended Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

Operating Mode

Reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

E1,

Operating Mode

A10

A11

A12

BA1 BA0

E6 E5

E10

E11

E12

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Commands

The Truth Tables below provides a general reference

of available commands. For a more detailed descrip-

tion of commands and operations, refer to the 256Mb
or 512Mb DDR SDRAM component data sheet.

NOTE:

1. DESELECT and NOP are functionally interchangeable.
2. BA0BA1 provide device bank address and A0A12 provide row address.
3. BA0BA1 provide device bank address; A0A9, A11 (1GB) or A0A9, A11, A12 (2GB) provide column address; A10 HIGH

enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ

bursts with auto precharge enabled and for WRITE bursts.

5. A10 LOW: BA0BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0

BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0BA1 are reserved). A0A12 provide the op-code
to be written to the selected mode register.

Table 10: Commands Truth Table

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Table 11: DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION)

DQS

WRITE Enable

Valid

WRITE Inhibit

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on V

REF

and Inputs

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +3.6V

Voltage on I/O Pins

Relative to V

. . . . . . . . . . . . . -0.5V to V

Q +0.5V

Operating Temperature,

(ambient) . . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 36W
Short Circuit Output Current. . . . . . . . . . . . . . . 50mA

Table 12: DC Electrical Characteristics and Operating Conditions

Notes: 15, 14; notes appear following parameter tables; 0°C

£ T

£ +70°C

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

32, 36

I/O Supply Voltage

DDQ

2.3

2.7

32, 36, 39

I/O Reference Voltage

REF

0.49

Q 0.51

6, 39

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 39

Input High (Logic 1) Voltage

(DC)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(DC)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any input 0V

£ V

, V

REF

pin 0V

£ V

1.35V (All other pins not under test = 0V)

Command/
Address, RAS#,
CAS#, WE#, S0#,
CKE0

-5

µA

CK, CK#

-10

DQS

-4

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ V

OUT

£ V

-10

µA

OUTPUT LEVELS

High Current (V

OUT

= V

Q - 0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 34

16.8

Table 13: AC Input Operating Conditions

Notes: 15, 14; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

12, 25, 35

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

12, 25, 35

I/O Reference Voltage

REF

(

)

0.49

0.51

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

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DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Table 14: I

Specifications and Conditions 1GB

DDR SDRAM components only
Notes: 15, 14, 42; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-335

-262

-26A/

-265

-202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-
Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ and DQS inputs

changing once per clock cyle; Address and control
inputs changing once every two clock cycles

DD0

2,430

2,160

20, 44

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN);

OUT

= 0mA; Address and control inputs changing once

per clock cycle

DD1

2,970

2,682

20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;

CK =

CK (MIN);

CKE = (LOW)

DD2P

180

144

21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle;

CK =

CK MIN; CKE = HIGH; Address and other

control inputs changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

1,620

ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;

CK =

CK (MIN); CKE =

LOW

DD3P

1,260

1,080

21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM andDQS inputs changing

twice per clock cycle; Address and other control inputs
changing once per clock cycle

DD3N

1,620

1,080

OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle;

CK =

CK (MIN); I

OUT

0mA

DD4R

3,060

3,222

20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle;

CK =

CK (MIN);

DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

2,880

3,492

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

10,440

10,080

20, 46

RFC = 7.8125µs

DD5A

360

24, 46

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

180

OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and control inputs change

only during Active READ, or WRITE commands

DD7

7,380

7,290

6,390

20, 45

a - Value calculated as one module rank in this operating condition, and all other module ranks in Power-Down mode (I

DD2P).

b - Value calculated reflects all module ranks in this operating condition.

1GB, 2GB (x72, ECC)

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Table 15: I

Specifications and Conditions 2GB

DDR SDRAM components only
Notes: 15, 14, 42; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-335

-262

-26A/

-265

-202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-
Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ and DQS inputs

changing once per clock cyle; Address and control
inputs changing once every two clock cycles

DD0

2,430

2,160

20, 44

OPERATING CURRENT: One device bank; Active -Read
Precharge; Burst = 2;

RC =

RC (MIN);

CK =

CK (MIN);

OUT

= 0mA; Address and control inputs changing once

per clock cycle

DD1

2,970

2,700

20, 44

PRECHARGE POWER-DOWN STANDBY CURRENT: All
device banks idle; Power-down mode;

CK =

CK (MIN);

CKE = (LOW)

DD2P

180

21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks
idle;

CK =

CK MIN; CKE = HIGH; Address and other

control inputs changing once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

1,620

1,440

ACTIVE POWER-DOWN STANDBY CURRENT: One device
bank active; Power-down mode;

CK =

CK (MIN); CKE =

LOW

DD3P

1,260

1,080

21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One device bank; Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM andDQS inputs changing

twice per clock cycle; Address and other control inputs
changing once per clock cycle

DD3N

1,620

1,440

OPERATING CURRENT: Burst = 2; Reads; Continuous
burst; One bank active; Address and control inputs
changing once per clock cycle;

CK =

CK (MIN); I

OUT

0mA

DD4R

3,060

2,700

20, 44

OPERATING CURRENT: Burst = 2; Writes; Continuous
burst; One device bank active; Address and control
inputs changing once per clock cycle;

CK =

CK (MIN);

DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

2,880

2,520

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

10,440

10,080

20, 46

RFC = 7.8125µs

DD5A

360

24, 46

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

180

OPERATING CURRENT: Four device bank interleaving
READs (BL = 4) with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and control inputs change

only during Active READ, or WRITE commands

DD7

7,380

7,290

6,390

20, 45

a - Value calculated as one module rank in this operating condition, and all other module ranks in Power-Down mode (I

DD2P).

b - Value calculated reflects all module ranks in this operating condition.

1GB, 2GB (x72, ECC)

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Table 16: Capacitance

Note: 11; notes appear following parameter tables

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input/Output Capacitance: DQ, DQS

Input Capacitance: Command and Address, S#, CKE

2.5

3.5

Input Capacitance: CK, CK#

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335 and -262 Speed Grades)

Notes: 15, 14; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-335

-262

UNITS

NOTES

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Access window of DQs from CK/CK#

-0.7

+0.7

-0.75

+0.75

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

CK (2.5)

7.5

40,47

CL=2

CK (2)

7.5

40, 47

DQ and DM input hold time relative to DQS

0.45

0.5

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.60

+0.60

-0.75

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.35

0.5

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

+0.75

16, 37

Data-out low-impedance window from CK/CK#

-0.70

-0.75

16, 38

Address and control input hold time (fast slew rate)

0.75

0.90

Address and control input setup time (fast slew rate)

0.75

0.90

Address and control input hold time (slow slew rate)

0.80

Address and control input setup time (slow slew rate)

0.80

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.50

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

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DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 17: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-335 and -262 Speed Grades) (Continued)

Notes: 15, 14; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-335

-262

UNITS

NOTES

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Table 18: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, and -202 Speed Grades)

Notes: 15, 14; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-26A/-265

-202

UNITS

NOTES

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

Access window of DQs from CK/CK#

-0.75

+0.75

-0.8

+0.8

CK high-level width

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

Clock cycle time

CL=2.5

CK (2.5)

7.5

40,47

CL=2

CK (2)

7.5/10

40, 47

DQ and DM input hold time relative to DQS

0.5

0.6

23, 27

DQ and DM input setup time relative to DQS

0.5

0.6

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.75

+0.75

-0.8

+0.8

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.5

0.6

22, 23

Write command to first DQS latching transition

DQSS

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.75

+0.8

16, 37

Data-out low-impedance window from CK/CK#

-0.75

-0.8

16, 38

Address and control input hold time (fast slew rate)

0.90

1.1

Address and control input setup time (fast slew rate)

0.90

1.1

1GB, 2GB (x72, ECC)

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Address and control input hold time (slow slew rate)

1.1

Address and control input setup time (slow slew rate)

1.1

Address and Control input pulse width (for each input)

IPW

2.2

LOAD MODE REGISTER command cycle time

MRD

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

HP -

QHS

22, 23

Data hold skew factor

QHS

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

µs

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 18: DDR SDRAM Component Electrical Characteristics and Recommended AC

Operating Conditions (-26A, -265, and -202 Speed Grades) (Continued)

Notes: 15, 14; notes appear following parameter tables; 0°C

£ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

AC CHARACTERISTICS

-26A/-265

-202

UNITS

NOTES

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

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DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to V

REF

(or to the

crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(AC)

and V

(AC).

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

by-pass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time at CL = 2 for -262, -26A, and -202,
CL = 2.5 for -335 and -265 with the outputs open.

9. Enables on-chip refresh and address counters.

10. I

specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V,

Q = +2.5V ±0.2V, V

REF

= V

, f = 100 MHz,

= 25°C, V

OUT

(DC) = V

Q/2, V

OUT

(peak to

peak) = 0.2V. DM input is grouped with I/O pins,
reflecting the fact that they are matched in load-
ing.

12. Command/Address input slew rate = 0.5V/ns. For

-335, -262, -26A, and -265, with slew rates 1V/ns
and faster,

IS and

IH are reduced to 900ps. If the

slew rate is less than 0.5V/ ns, timing must be der-
ated:

IS has an additional 50ps per each 100mV/

ns reduction in slew rate from the 500mV/ns,
while

IH remains constant. If the slew rate

exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V

REF

14. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE

£ 0.3 x V

Q is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is
V

16.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

17. The intent of the Don't Care state after completion

of the postamble is that the DQS-driven signal
should either be high, low, or high-Z and that any
signal transition within the input switching region
must follow valid input requirements. If DQS tran-
sitions to HIGH above V

(DC) MIN, then it must

not transition to LOW below V

(DC) MIN prior

DQSH (MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

20. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

(MAX) for I

measurements is the largest multi-

ple of

CK that meets the maximum absolute

value for

RAS.

Output
(V

OUT

)

Reference

Point

30pF

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DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.

22. The valid data window is derived by achieving

other specifications:

HP (

CK/2),

DQSQ, and

(

QH =

HP -

QHS). The data valid window derates

directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 10, Derating Data Valid Window,
shows derating curves for duty cycles ranging
between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, V

(AC)

or V

(AC).

b. Reach at least the target AC level.
c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(DC)

or V

(DC).

26. JEDEC specifies CK and CK# input slew rate must

1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to

DS and

DH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncer-
tain.

28. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

Figure 10: Derating Data Valid Window

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

3.400

3.350

3.300

3.250

3.200

3.150

3.100

3.050

3.000

2.950

2.900

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

-335
-262/-26A/-265 @

CK = 10ns

-202 @

CK = 10ns

-262/-26A/-265 @

CK = 7.5ns

-202 @

CK = 8ns

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DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

30.

HP min is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK# inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS (MIN) can be satis-

fied prior to the internal precharge command
being issued.

32. Any positive glitch to nominal must be less than

1/3 of the clock and not more than +400mV or
2.9V maximum, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.2V minimum,
whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 11,
Pull-Down Characteristics.

b. The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I
curve of Figure 11, Pull-Down Characteristics.

c. The full variation in driver pull-up current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 12,
Pull-Up Characteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
12, Pull-Up Characteristics.

e. The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

34. The voltage levels used are derived from a mini-

mum V

level and the referenced test load. In

practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.

35. V

overshoot: V

(MAX) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

undershoot:

(MIN) = -1.5V for a pulse width

£ 3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

36. V

and V

DDQ

must track each other.

37. This maximum value is derived from the refer-

enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for

HZ (MAX) and the last DVW.

(MAX) will prevail over

DQSCK (MAX) +

RPST

(MAX) condition.

LZ (MIN) will prevail over

DQSCK (MIN) +

RPRE (MAX) condition.

38. For slew rates greater than 1V/ns the (LZ) transi-

tion will start about 310ps earlier.

39. During initialization, V

DDQ

, V

, and V

REF

must be

equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if
V

DDQ

are 0V, provided a minimum of 42

W of

series resistance is used between the V

supply

and the input pin.

Figure 11: Pull-Down Characteristics

Figure 12: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

-20

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

41.

RAP

RCD.

42. When an input signal is HIGH or LOW, it is

defined as a steady state logic HIGH or LOW.

43. For -335, -262, -26A, and -265, I

3N is specified

to be 35mA at 100 MHz.

44. Random address changing and 50 percent of data

changing at every transfer.

45. Random address changing and 100 percent of

data changing at every transfer.

46. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,

CKE must be active at each rising clock edge, until

REF later.

47. I

2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. I

2Q is

similar to I

2F except I

2Q specifies the

address and control inputs to remain stable.
Although I

2F, I

2N, and I

2Q are similar,

2F is "worst case."

48. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles (before READ
commands).

49. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. The timing and switching specifications for the register listed above are critical for proper operation of the DDR SDRAM

Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module.
Detailed information for this register is available in JEDEC Standard JESD82-4.

2. Data inputs must be low a minimum time of t

act

max, after RESET# is taken HIGH.

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of t

inact

max, after RESET# is taken LOW.

4. For data signal input slew rate

³ 1 V/ns.

5. For data signal input slew rate

³ 0.5 V/ns and

1V/ns.

6. CK, CK# signals input slew rate

³ 1V/ns.30

Table 19: Register Timing Requirements and Switching Characteristics

Note 1

SYMBOL PARAMERTER

CONDITION

0°C

£ T

+70°C

= 2.5V ± 0.2V

UNITS

NOTES

MIN

MAX

SSTL

(bit pattern

by JESD82-3

or JESD82-4)

clock

Clock Frequency

200

MHz

Clock to Output Time

30pF to GND and

50 Ohms to V

1.1

2.8

PHL

Reset To Output Time

Pulse Duration

CK, CK# HIGH or

LOW

2.5

act

Differential Inputs Active Time

inact

Differential Inputs Inactive Time

Setup Time, Fast Slew Rate

Data Before CK

HIGH, CK# LOW

0.75

4, 6

Setup Time, Slow Slew Rate

0.9

5, 6

Hold Time, Fast Slew Rate

Data After CK

HIGH, CK# LOW

0.75

4, 6

Hold Time, Slow Slew Rate

0.9

5, 6

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Reg-

istered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed
information for this PLL is available in JEDEC Standard JESD82.

2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to

meet the other timing parameters. (Used for low speed system debug.)

4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its ref-

erence signal after power up.

5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each

other.

7. The Output Slew Rate is determined from the IBIS model;

Table 20: PLL Clock Driver Timing Requirements and Switching Characteristics

Note 1

PARAMETER

SYMBOL

0°C

£ T

+70°C

= 2.5V ± 0.2V

UNITS

NOTES

MIN

NOMINAL

MAX

Operating Clock Frequency

170

MHz

2, 3

Input Duty Cycle

Stabilization Time

STAB

100

Cycle to Cycle Jitter

JIT

-75

Static Phase Offset

-50

Output Clock Skew

100

Period Jitter

JIT

PER

-75

Half-Period Jitter

JIT

HPER

-100

100

Input Clock Slew Rate

1.0

V/ns

Output Clock Slew Rate

1.0

V/ns

GND

CDCV857

R=60

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 13: Component Case Temperature vs. Air Flow

NOTE:

1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across the module.
2. The component case temperature measurements shown above were obtained experimentally. The typical system to be

used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered
memory modules. Case temperatures charted represent worst-case component locations on modules installed in the
internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard
for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test
chamber.

4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

max

- memory stress software

ave

- 3D gaming software

ave

- memory stress software

Minimum Air Flow

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ure 14, Data Validity, and Figure 15, Definition of Start
and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 16,
Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 14: Data Validity

Figure 15: Definition of Start and Stop

Figure 16: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 17: SPD EEPROM Timing Diagram

Table 21: EEPROM Device Select Code

The most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 22: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = `1'

Random Address Read

or V

START, Device Select, RW = `0', Address

or V

reSTART, Device Select, RW = `1'

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

£ 16

START, Device Select, RW = `0'

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. To avOId spurious START and STOP conditions, a minimum delay is placed between SCL= 1 and the falling or rising

edge of SDA.

2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of

the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Serial Presence-Detect EEPROM DC Operating Conditions

To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling/rising edge of SDA
All voltages referenced to V

DDSPD

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

Supply Voltage

DDSPD

2.3

3.6

Input High Voltage: Logic 1; All inputs

DDSPD

0.7

DDSPD

+ 0.5

Input Low Voltage: Logic 0; All inputs

-0.6

DDSPD

x 0.3

Output Low Voltage: I

OUT

= 3mA

0.4

Input Leakage Current: V

= GND to V

0.10

µA

Output Leakage Current: V

OUT

= GND to V

0.05

µA

Standby Current:

1.6

µA

Power Supply Current, READ:
SCL clock frequency = 100 KHz

0.4

Powr Supply Current, WRITE:
SCL clock frequency = 100 KHz

Table 23: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.2

0.9

µs

Time the bus must be free before a new transition can start

BUF

1.3

µs

Data-out hold time

200

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

0.6

µs

Clock HIGH period

HIGH

0.6

µs

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

LOW

1.3

µs

SDA and SCL rise time

0.3

µs

SCL clock frequency

SCL

400

KHz

Data-in setup time

SU:DAT

100

Start condition setup time

SU:STA

0.6

µs

Stop condition setup time

SU:STO

0.6

µs

WRITE cycle time

WRC

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Table 24: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT36VDDF12872 MT36VDDF25672

Number of SPD Bytes Used by Micrpn

128

Tptal Number pf Bytes in SPD Device

256

Fundamental Mempry Type

SDRAM DDR

Number of Row Addresses on Assembly

Number of Column Addresses on Assembly

11, 12

Number of Physical Ranks on DIMM

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

SSTL 2.5V

SDRAM Cycle Time,

CK (CAS Latency = 2.5)

(See note 1)

6ns (-335)

7ns (-262/-26A)

7.5ns (-265)

8ns (-202)

60
70
75
80

SDRAM Access from Clock,

(CAS Latency = 2.5)

0.7ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

70
75
80

Module Configuration Type

ECC

Refresh Rate/Type

7.81µs/SELF

SDRAM Device Width (Primary Sdram)

Error-checking Sdram Data Width

Minimum Clock Delay, Back-to-Back
Random Column Access

1 clock

Burst Lengths Supported

2, 4, 8

Number of Banks on SDRAM Device

CAS Latencies Supported

2, 2.5

CS Latency

WE Latency

SDRAM Module Attributes

Registered, PLL/Diff. Clock

SDRAM Device Attributes: General

Fast/Concurrent AP

SDRAM Cycle Time,

CK (CAS Latency = 2)

7.5ns (-335/-262/-26A)

10ns (-265/-202)

SDRAM Access from CK ,

(CAS Latency = 2)

0.70ns (-335)

0.75ns (-262/-26A/-265)

0.8ns (-202)

70
75
80

SDRAM Cycle Time,

CK (CAS Latency = 1.5)

N/A

SDRAM Access from CK,

AC (CAS Latency =

1.5)

N/A

Minimum Row Precharge Time,

18ns (-335)
15ns (-262)

20ns (-202/-265/-26A)

48
3C
50

Minimum Row Active to Row Active,

RRD

12ns (-335)

15ns (-202/-265/-26A/-262)

30
3C

Minimum RAS# to CAS# Delay,

RCD

18ns (-335)
15ns (-262)

20ns (-202/-265/-26A)

48
3C
50

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Minimum RAS# Pulse Width,

RAS

(See note 2)

42ns (-335)

45ns (-262/-26A/-265)

40ns (-202)

2A
2D

Module Bank Density

512MB, 1GB

Address and Command Setup Time,

(See note 3)

0.80ns (-335)

1ns (-262/-26A/-265)

1.1ns (-202)

Address and Command Hold Time,

(See note 3)

0.80ns (-335)

1ns (-262-26A/-265)

1.1ns (-202)

Data/Data Mask Input Setup Time,

0.45ns (-335)

0.50ns (-262/-26A/-265)

0.60ns (-202)

45
50
60

Data/Data Mask Input Hold Time,

0.45ns (-335)

0.50ns (-262/-26A/-265)

0.60ns. (-202)

45
50
60

36-40 Reserved

Min Active Auto Refresh Time,

60ns (-335/-262)

65ns (-26A/-265)

70ns (-202)

3C
41
46

Minimum Auto Refresh to Active/
Auto Refresh Command Period,

RFC

72ns (-335)

75ns (-262/-26A/-265)

80ns (-202)

48
4B
50

SDRAM Device Max Cycle Time,

MAX

12ns (-335)

13ns (-202/-265/-26A/-262)

30
34

SDRAM Device Max DQS-DQ Skew Time,

DQSQ

0.40ns (-335)

0.50ns (-262/-26A/-265)

0.6ns (-202)

28
32
3C

SDRAM Device Max Read Data Hold Skew
Factor,

QHS

0.50ns (-335)

0.75ns (-262/-26A/-265)

1.0ns (-202)

50
75

Reserved

DIMM Height

Standard/Low Profile

10/01

4861 Reserved

SPD Revision

Release 1.0

Checksum For Bytes 0-62

-335
-262

-26A

-265
-202

7E/6F

E4/0C
48/39
78/69

DC/04

10/F1

9D/8E

CA/BB

FA/EB

95/86

Manufacturer's JEDEC ID Code

MICRON

65-71 Manufacturer's JEDEC ID Code

(Continued)

Manufacturing Location

0112

010C

73-90 Module Part Number (ASCII)

Variable Data

PCB Identification Code

1-9

01-09

Identification Code (Continued)

Table 24: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT36VDDF12872 MT36VDDF25672

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

NOTE:

1. Value for -26A

CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of

RAS used for -262/-26A/-265 modules is calculated from

RC -

RP. Actual device spec value is 40 ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

repesented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum
slew rate is met.

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98 Module Serial Number

Variable Data

99-127 Manufacturer-specific Data (RSVD)

Table 24: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY (VERSION)

MT36VDDF12872 MT36VDDF25672

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR DIMM

09005aef8075ebf6

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDF36C128_256x72G_C.fm - Rev. C 8/03 EN

Figure 19: Low-Profile (1GB) 184-Pin DDR DIMM DImensions

Figure 20: Low-Profile (2GB) 184-Pin DDR DIMM DImensions

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

U10

U20

U19

U18

U17

U16

U15

U14

U13

U12

U11

U21

U22

U23

U24

U25

U27

U28

U29

U30

U31

U40

U39

U38

U37

U36

U35

U34

U33

U32

1.205 (30.61)
1.195 (30.35)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)
5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

0.394 (10.00)

TYP.

BACK VIEW

PIN 184

PIN 93

0.054 (1.37)
0.046 (1.17)

0.157 (3.99)

MAX

U26

U19

U10

U11

U10

U20

U18

U17

U16

U15

U14

U13

U21

U22

U23

U24

U25

U26

U27

U37

U28

U29

U30

U31

U32

U33

U40

U39

U38

U36

U35

U34

1.205 (30.61)
1.195 (30.35)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)
5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

0.394 (10.00)

TYP.

BACK VIEW

PIN 184

PIN 93

0.054 (1.37)
0.046 (1.17)

0.157 (3.99)

MAX

MIN

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