PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM
DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

REGISTERED QUAD-RANK
DDR SDRAM DIMM

MT36VDDS12872D 1GB (ADVANCE

MT36VDDT12872D 1GB, MT36VDDS25672D 2GB
(ADVANCE

), MT36VDDT25672D 2GB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· 184-pin, dual in-line memory modules (DIMM),

organized as four module ranks

· Fast data transfer rates: PC1600 and PC2100
· Utilizes 200 MT/s and 266 MT/s TwinDie

Ô DDR or

Stacked TSOP DDR SDRAM components

· ECC, 1-bit error detection and correction
· Low-Profile PCB design
· Registered inputs with one-clock delay
· Phase-lock loop (PLL) clock driver to minimize

· 1GB (128 Meg x 72) and 2GB (256 Meg x 72)
· 2.5V I/O (SSTL_2 compatible)
· V

= V

Q= +2.5V

· V

DDSPD

= +2.3V to +3.6V

· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

· Bidirectional data strobe (DQS) transmitted/

received with data, i.e., source-synchronous data
capture

· Differential clock inputs (CK and CK#)
· Four internal device banks for concurrent operation
· Selectable burst lengths: 2, 4, or 8
· Auto precharge option
· Auto Refresh and Self Refresh Modes
· 7.8125µs maximum average periodic refresh

interval

· Serial Presence Detect (SPD) with EEPROM
· Selectable READ CAS latency
· Gold edge connectors

Figure 1: 184-Pin Low Profile DIMM

(MO-206)

NOTE:

1. CL = Device CAS (READ) Latency; registered

mode adds one clock cycle to CL due to the input
register.

2. Contact factory for availability.

OPTIONS

MARKING

· Package

184-Pin DIMM (Standard)

184-Pin DIMM (Lead-free)

· Memory Clock/Data Frequency, CAS Latency

7.5ns (133 MHz)/266 MT/s, CL = 2

-262

7.5ns (133 MHz)/266 MT/s, CL = 2

-26A

7.5ns (133 MHz)/266 MT/s, CL = 2.5

-265

8ns (100 MHz)/200 MT/s, CL = 2

-202

Table 1:

Address Table

MT36VDDS12872D

MT36VDDT12872D

MT36VDDS25672D

MT36VDDT25672D

Refresh Count

Row Addressing

8K (A0A12)

Device Bank Addressing

4 (BA0, BA1)

Base Device Configuration

32 Meg x 8

64 Meg x 8

Column Addressing

1K (A0A9)

2K (A0A9, A11)

Module Rank Addressing

4 (S0#-S3#)

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT36VDDT12872DY-265A1.

Table 2:

Part Numbers and Timing Parameters

PART NUMBER

MODULE

DENSITY

CONFIGURATION

MODULE

BANDWIDTH

MEMORYCLOCK/

DATA RATE

LATENCY

(CL -

RCD -

RP)

MT36VDDS12872DG-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDS12872DY-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDS12872DG-262__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDS12872DY-262__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDS12872DG-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDS12872DY-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDS12872DG-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDS12872DY-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDT12872DG-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDT12872DY-26A__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDT12872DG-262__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDT12872DY-262__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDT12872DG-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDT12872DY-265__

1GB

128 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDT12872DG-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDT12872DY-202__

1GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDS25672DG-26A__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDS25672DY-26A__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDS25672DG-262__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDS25672DY-262__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDS25672DG-265__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDS25672DY-265__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDS25672DG-202__

2GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDS25672DY-202__

2GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDT25672DG-26A__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDT25672DY-26A__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-3-3

MT36VDDT25672DG-262__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDT25672DY-262__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2-2-2

MT36VDDT25672DG-265__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDT25672DG-265__

2GB

256 Meg x 72

2.1 GB/s

7.5ns/266 MT/s

2.5-3-3

MT36VDDT25672DG-202__

2GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

MT36VDDT25672DY-202__

2GB

128 Meg x 72

1.6 GB/s

10ns/200 MT/s

2-2-2

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Figure 2: 184-Pin DIMM Pin Locations

Table 3:

Pin Assignment
(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

DQ17

DQS8

DQ0

DQS2

S2#

CB2

DQ48

DQ1

DQ49

DQS0

DQ18

CB3

DQ2

BA1

DNU

DQ32

DNU

DQ3

DQ19

DQ33

DQS6

RESET#

DQ24

DQS4

DQ50

DQ34

DQ51

DQ8

DQ25

DQ9

DQS3

BA0

DQS1

DQ35

DQ56

DQ40

DQ57

DNU

DQ26

DNU

DQ27

WE#

DQS7

DQ41

DQ58

DQ10

CAS#

DQ59

DQ11

CKE0

CB0

DQS5

CB1

DQ42

SDA

DQ16

DQ43

SCL

Table 4:

Pin Assignment
(184-Pin DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

116

139

162

DQ47

DQ4

117

DQ21

140

DQS17/DM8

163

S3#

DQ5

118

A11

141

A10

164

119

DQS11/DM2

142

CB6

165

DQ52

DQS9/DM0

120

143

166

DQ53

DQ6

121

DQ22

144

CB7

167

DNU

DQ7

122

145

168

100

123

DQ23

146

DQ36

169

DQS15/DM6

101

124

147

DQ37

170

DQ54

102

125

148

171

DQ55

103

126

DQ28

149

DQS13/DM4

172

104

127

DQ29

150

DQ38

173

105

DQ12

128

151

DQ39

174

DQ60

106

DQ13

129

DQS12/DM3

152

175

DQ61

107

DQS10/DM1

130

153

DQ44

176

108

131

DQ30

154

RAS#

177

DQS16/DM7

109

DQ14

132

155

DQ45

178

DQ62

110

DQ15

133

DQ31

156

179

DQ63

111

CKE1

134

CB4

157

S0#

180

112

135

CB5

158

S1#

181

SA0

113

136

159

DQS14/DM5

182

SA1

114

DQ20

137

CK0

160

183

SA2

115

A12

138

CK0#

161

DQ46

184

DDSPD

PIN 1

PIN 52

PIN 53

PIN 92

PIN 93

PIN 144

PIN 145

PIN 184

U20

U22

U10

U11

U13

U14

U12

U15

U16

U17

U18

Indicates a V

or V

Q pin

Indicates a V

FRONT VIEW

BACK VIEW

Low Profile Quad-Rank

U19

U21

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

REF

Input

SSTL_2 reference voltage.

63, 65, 154

WE#, CAS#, RAS#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.

71, 157, 158, 163

CS0CS4

Input

Chip Select.

137, 138

CK0, CK0#

Input

Clock: CK and CK# are differential clock inputs. All address
and control input signals are sampled on the crossing of the
positive edge of CK and negative edge of CK#. Output data
(DQs and DQS) is referenced to the crossings of CK and CK#.

21, 111

CKE0 - CKE1

Input

Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank). CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH
entry. CKE is asynchronous for SELF REFRESH exit and for
disabling the outputs. CKE must be maintained HIGH
throughout read and write accesses. Input buffers (excluding
CK, CK# and CKE) are disabled during POWER-DOWN. Input
buffers (excluding CKE) are disabled during SELF REFRESH.
CKE is an SSTL_2 input but will detect an LVCMOS LOW level
after V

is applied.

52, 59

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

27, 29, 32, 37, 41, 43, 48,

115, 118, 122, 125, 130,

141

A0-A12

Input

Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which register
(mode register or extended mode register) is loaded during
the LOAD MODE REGISTER command.

SDA

Input/Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.

181, 182, 183

SA0-SA2

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

RESET#

Input

Asynchronously forces all register outputs LOW when RESET#
is LOW. This signal can be used during power-up to ensure
CKE is LOW and SDRAM DQs are High-Z.

44, 45, 49, 51, 134, 135,

142, 144

CB0-CB7

Input/Output

Data I/Os: Check bits. ECC 1-bit error detection and correction.

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

5, 14, 25, 36, 47, 56, 67,

78, 86, 97, 107, 119,

129, 140, 149, 159,

169, 177

DQS0-DQS17

Input/Output

Data Strobe: DQS0-DQS8, Output with READ data, input with
WRITE data. DQS is edge-aligned with READ data, centered in
WRITE data. Used to capture data. Data Mask: DQS9-DQS17
function as DM0-DM8 to mask WRITE data when when HIGH.

2, 4, 6, 8, 12, 13, 19, 20,

23, 24, 28, 31, 33, 35, 39,
40, 53, 55, 57, 60, 61, 64,
68, 69, 72, 73, 79, 80, 83,
84, 87, 88, 94, 95, 98, 99,

105, 106, 109, 110, 114,
117, 121, 123, 126, 127,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,

175, 178, 179

DQ0-DQ63

Input/

Output

Data I/Os: Data bus.

7, 15, 22, 30, 38, 46, 54,

62, 70, 77, 85, 96,104,

108, 112, 120, 128, 136,
143, 148, 156, 164, 168,

172, 180

Supply

Power Supply: +2.5V ±0.2V.

3, 11, 18, 26, 34, 42, 50,

58, 66, 74, 81, 89, 93,

100, 116, 124, 132, 139,

145, 152, 160, 176

Supply

Ground.

184

DDSPD

Supply

Serial EEPROM positive power supply: +2.3V to +3.6V.

9, 82, 90, 101, 102, 103,

113, 173

No Connect: These pins should be left unconnected.

16, 17, 75, 76, 167

DNU

Do Not Use: These pins are not connected on this module but
are assigned pins on other modules in this product family.

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols; refer to Pin Assignment Tables on page 3 for more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Figure 3: Functional Block Diagram

SA0

SERIAL PD

SDA

SA1

SA2

S2#

S3#

BA0, BA1

A0-A12

RAS#

RS2#, Bank 2

RS3#, Bank 3

RBA0, RBA1: DDR SDRAMs

RA0-RA12: DDR SDRAMs

RRAS#: DDR SDRAMs

RCAS#: DDR SDRAMs

RWE#: DDR SDRAMs

RCKE0: DDR SDRAMs x2 Ranks (U1

-U9

, U10

-U18

)

RCKE1: DDR SDRAMs x2 Ranks (U1

-U9

, U10

-U18

)

RESET#

CAS#

WE#

CKE0

CKE1

CK#

DQ24
DQ25
DQ28
DQ29
DQ30
DQ31
DQ26
DQ27

U15b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ16
DQ17
DQ20
DQ21
DQ22
DQ23
DQ18
DQ19

U17b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ8
DQ9
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11

U18b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ4
DQ5
DQ6
DQ7
DQ2
DQ3

U5b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ27
DQ26
DQ31
DQ30
DQ29
DQ28
DQ25
DQ24

U4b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ19
DQ18
DQ23
DQ22
DQ21
DQ20
DQ17
DQ16

U2b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ11
DQ10
DQ15
DQ14
DQ13
DQ12
DQ9
DQ8

DM CS# DQS

U1b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ3
DQ2
DQ7
DQ6
DQ5
DQ4
DQ1
DQ0

DQS9/DM0

RS0#

U3b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

R
E

S
T
E

PLL

DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
DDR SDRAM X 4
REGISTER X 2

SCL

U1t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U2t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U3t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U18t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

RS1#

DM CS# DQS

DQS0

DQS10/DM1

DQS1

U17t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

DQS11/DM2

DQS2

DM CS# DQS

U16b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U16t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

DQS12/DM3

DQS3

U4t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

U15t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

DQS17/DM8

DQS8

U5t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

CB3
CB2
CB7
CB6
CB5
CB4
CB1
CB0

CK0

CK0#

120

U19, U21

U22

U20

SPD

DDSPD

U14b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ59
DQ58
DQ63
DQ62
DQ61
DQ60
DQ57
DQ56

U9b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ51
DQ50
DQ55
DQ54
DQ53
DQ52
DQ49
DQ48

U7b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ43
DQ42
DQ47
DQ46
DQ45
DQ44
DQ41
DQ40

DM CS# DQS

U6b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ35
DQ34
DQ39
DQ38
DQ37
DQ36
DQ33
DQ32

DQS13/DM4

RS2#

U8b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U6t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U7t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U8t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

RS3#

DM CS# DQS

DQS4

DQS14/DM5

DQS5

DQS15/DM6

DQS6

DM CS# DQS

DQS16/DM7

DQS7

U9t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

U14t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

CB0
CB1
CB4
CB5
CB6
CB7
CB2
CB3

DQ56
DQ57
DQ60
DQ61
DQ62
DQ63
DQ58
DQ59

U10b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ48
DQ49
DQ52
DQ53
DQ54
DQ55
DQ50
DQ51

U12b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ40
DQ41
DQ44
DQ45
DQ46
DQ47
DQ42
DQ43

U13b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ32
DQ33
DQ36
DQ37
DQ38
DQ39
DQ34
DQ35

U13t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

U12t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

U11b

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

U11t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

U10t

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

REF

DDR SDRAMS

DQS9/DM0

DQS0

DQS10/DM1

DQS1

DQS11/DM2

DQS2

DQS12/DM3

DQS3

DQS17/DM8

DQS8

DQS13/DM4

DQS4

DQS14/DM5

DQS5

DQS15/DM6

DQS6

DQS16/DM7

DQS7

S0#

S1#

RS0#, Bank 0 (U1

-U9

)

RS1#, Bank 1 (U1

-U9

)

(U10

-U18

)

(U10

-U18

)

120

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron modules utilize various component speed

grades, as referenced in the Module Part Numbering Guide at

www.micron.com/numberguide

MT46V32M8S2 DDR SDRAMs for MT36VDDS12872D
MT46V64M8S2 DDR SDRAMs for MT36VDDT12872D
MT46V32M8TG DDR SDRAMs for MT36VDDS25672D
MT46V64M8TG DDR SDRAMs for MT36VDDT25672D

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

General Description

The Micron MT36VDDS12872D, MT36VDDT12872D,

MT36VDDS25672D, and MT36VDDT25672D are high-
speed CMOS, dynamic random-access, 1GB and 2GB
quad-rank registered memory modules, organized in a
x72 (ECC) configuration using internally configured
quad-bank DDR SDRAM devices.

These DDR SDRAM modules use a double data rate

architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-
prefetch architecture with an interface designed to
transfer two data words per clock cycle at the I/O pins.
A single read or write access for the DDR SDRAM mod-
ule effectively consists of a single 2n-bit wide, one-
clock-cycle data transfer at the internal DRAM core
and two corresponding n-bit wide, one-half-clock-
cycle data transfers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.

These DDR SDRAM modules operates from differ-

ential clock inputs (CK and CK#); the crossing of CK
going HIGH and CK# going LOW will be referred to as
the positive edge of CK. Commands (address and con-
trol signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.

Read and write accesses to the DDR SDRAM mod-

ules are burst oriented; accesses start at a selected
location and continue for a programmed number of
locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is
then followed by a READ or WRITE command. The
address bits registered coincident with the ACTIVE
command are used to select the device bank and row
to be accessed (BA0, BA1 select devices bank; A0A12
select device row). The address bits registered coinci-
dent with the READ or WRITE command are used to
select the device bank and the starting device column
location for the burst access.

These DDR SDRAM modules provide for program-

mable READ or WRITE burst lengths of 2, 4, or 8 loca-
tions. An auto precharge function may be enabled to
provide a self-timed row precharge that is initiated at
the end of the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,

thereby providing high effective bandwidth by hiding
row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 256Mb, 512Mb, DDR SDRAM and 512Mb and 1Gb
TwinDie DDR SDRAM component data sheets.

PLL and Register Operation

These DDR SDRAM modules operate in registered

mode, where the control/address input signals are
latched in the register on one rising clock edge and
sent to the DDR SDRAM devices on the following ris-
ing clock edge (data access is delayed by one clock). A
phase-lock loop (PLL) on the module is used to redrive
the differential clock signals CK and CK# to the DDR
SDRAM devices to minimize system clock loading.

Serial Presence-Detect Operation

These DDR SDRAM modules incorporate serial

presence-detect (SPD). The SPD function is imple-
mented using a 2,048-bit EEPROM. This nonvolatile
storage device contains 256 bytes. The first 128 bytes
can be programmed by Micron to identify the module
type and various SDRAM organizations and timing
parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/
WRITE operations between the master (system logic)
and the slave EEPROM device (DIMM) occur via a
standard I

C bus using the DIMM's SCL (clock) and

SDA (data) signals, together with SA (2:0), which pro-
vide eight unique DIMM/EEPROM addresses. Write
protect (WP) is tied to ground on the module, perma-
nently disabling hardware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 4, Mode Register Definition Diagram, on page 8.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Mode register bits A0A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A12
specify the operating mode.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1A12 when the burst length is set to two,
by A2A12 when the burst length is set to four and by
A3A12 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. The
programmed burst length applies to both READ and
WRITE bursts.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 9.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 2 or 2.5 clocks, as shown in Figure 5, CAS
Latency Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table
Table 7:, CAS Latency (CL) Table, indicates the operat-
ing frequencies at which each CAS latency setting can
be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA1 and BA0)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

1GB and 2GB Modules

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

NOTE:

1. For a burst length of two, A1A12 select the two-data-

element block; A0 selects the first access within the
block.

2. For a burst length of four, A2A12 select the four-data-

element block; A0A1 select the first access within the
block.

3. For a burst length of eight, A3A12 select the eight-

data-element block; A0A2 select the first access within
the block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

Figure 5: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7

A12

each set to zero, and bits A0

A6 set to the desired val-

ues. A DLL reset is initiated by issuing a MODE REGIS-
TER SET command with bits A7 and A9

A12 each set to

zero, bit A8 set to one, and bits A0

A6 set to the desired

values. Although not required by the Micron device,
JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL,
it should always be followed by a LOAD MODE REGIS-
TER command to select normal operating mode.

All other combinations of values A7

A12 are

reserved for future use and/or test modes. Test modes
and reserved states should not be used because
unknown operation or incompatibility with future ver-
sions may result.

Table 6:

Burst Definition Table

BURST
LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES

WITHIN A BURST

SEQUENTIAL INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7:

CAS Latency (CL) Table

Registered mode will add one clock cycle to each CL

SPEED

ALLOWABLE OPERATING CLOCK

FREQUENCY (MHz)

CL = 2

CL = 2.5

-262

£ f £ 133

£ f £133

-26A

£ f £ 133

£ f £133

-265

£ f £ 100

£ f £133

-202

£ f £ 100

£ f £125

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Digram. The extended mode register is pro-
grammed via the LOAD MODE REGISTER command
to the mode register (with BA0 = 1 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both LOW) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is
enabled, 200 clock cycles must occur before a READ
command can be issued.

Figure 6: Extended Mode Register

Definition Digram

NOTE:

1. E14 and E13 (BA1 and BA0) must be "0, 1" to select the

Extended Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

Operating Mode

Reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

E1,

Operating Mode

A10

A11

A12

BA1 BA0

E6 E5

E10

E11

E12

1GB and 2GB Modules

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Commands

Truth Table 1 provides a general reference of avail-

able commands. For a more detailed description of
commands and operations, refer to the Micron 256Mb,

512Mb, 512Mb TwinDie, or 1Gb TwinDie DDR SDRAM
component data sheets.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.
2. DESELECT and NOP are functionally interchangeable.
3. BA0-BA1 provide device bank address and A0-A12 provide row address.
4. BA0-BA1 provide device bank address; A0-A9 (1GB), A0A9, A11 (2GB) provide column address; A10 HIGH enables the

auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.

5. Applies only to READ bursts with auto precharge disabled; this command is undefined (and should not be used) for

READ bursts with auto precharge enabled and for WRITE bursts.

6. A10 LOW: BA0-BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0-

BA1 are "Don't Care."

7. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
8. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
9. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A12 provide the op-code
to be written to the selected mode register.

Table 8:

Commands Truth Table

Note: 1

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select device bank and activate row)

Bank/Row

READ (Select device bank and column, and start READ burst)

Bank/Col

WRITE (Select device bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in device bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

7, 8

LOAD MODE REGISTER

Op-Code

Table 9:

DM Operation Truth Table

Used to mask write data; provided coincident with the corresponding data.

NAME (FUNCTION)

Write Enable

Valid

Write Inhibit

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

Supply

Relative to V

-1V to +3.6V

Voltage on V

Q Supply

Relative to V

-1V to +3.6V

Voltage on V

REF

and Inputs

Relative to V

-1V to +3.6V

Voltage on I/O Pins

Relative to V

-0.5V to V

Q +0.5V

Operating Temperature

(ambient)0

°C to +55°C

Storage Temperature (plastic) . . . . . .-70

°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 36W
Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 15, 14; notes appear on pages 1922; 0

°C £ T

£ +70°C

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

2.3

2.7

32, 36

I/O Supply Voltage

2.3

2.7

32,

36,39

I/O Reference Voltage

REF

0.49 x V

0.51 x V

6, 39

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 39

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT (All Modules)
Any input 0V

£ VIN £ VDD,

VREF pin 0V

£ VIN £ 1.35V

(All other pins not under test = 0V)

Command/Address, CAS#,
RAS#, WE#, S#, CKE

-5

µA

CK, CK#

-10

DQS, DQM

-8

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ V

OUT

£ V

-20

µA

OUTPUT LEVELS:
High Current (V

OUT

= V

DDQ

-0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 34

16.8

Table 11: AC Input Operating Conditions

Notes: 15, 14; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.310

12, 25, 35

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

12, 25, 35

I/O Reference Voltage

REF

(

)

0.49 x V

0.51 x V

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 12: I

Specifications and Conditions (MT36VDDS12872D)

Notes: 15, 8, 10, 12; DDR SDRAM components; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-262

-26A/

-265

-202

UNITS NOTES

OPERATING CURRENT: One die in I

DD0

condition, one die in I

DD2P

condition. (I

DD0

Condition) one device bank; Active-Precharge;

RC=

(MIN);

CK=

CK (MIN); DQ, DM and DQS inputs changing once per clocke

cycle; Address and control inputs changing once every two clock cycles.

DD0

TBD

1,341

TBD

20, 42

OPERATING CURRENT: One die in I

DD1

condition, one die in I

DD2P

condition. (I

1 Condition) one device bank; Active-Precharge; Burst = 2;

RC=

RC (MIN);

CK=

CK (MIN); Iout = 0mA; Address and control inputs

changing once per clock cycle.

DD1

TBD

1,521

TBD

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: Both die in I

DD2P

condition . (I

DD2P

Condition) All device banks idle; Power-down mode;

CK=

CK (MIN); CKE= LOW

DD2P

TBD

288

TBD

21, 28,

IDLE STANDBY CURRENT: Both die in I

DD2F

condition. (I

DD2F

Condition)

CS# = HIGH; All device banks idle;

CK =

CK (MIN); CK = HIGH; Address

and other control inputs changing once per clock cycle. V

= V

REF

for

DQ, DQS and DM

DD2F

TBD

2,880

TBD

ACTIVE POWER-DOWN STANDBY CURRENT: Both die in I

DD3P

condition.

3P Condition) One device bank active; Power-down mode;

CK = CK (MIN); CKE= LOW

DD3P

TBD

2,160

TBD

21, 28,

ACTIVE STANDBY CURRENT: Both die in I

DD3N

condition. (I

DD3N

condition)

CS# = HIGH; CKE= HIGH; One device bank active;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM andDQS inputs changing twice per clock cycle;

Address and other control inputs changing once per clock cycle

DD3N

TBD

3,240

TBD

OPERATING CURRENT: One die in I

DD4R

condition, one die in I

DD2P

condition. (I

DD4R

condition) Burst = 2; Reads; Continuous burst; One

device bank active; Address and control inputs changing once per clock

cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

TBD

1,836

TBD

20, 42

OPERATING CURRENT: One die in I

DD4W

condition, one die in I

DD2P

con-

dition. (I

DD4W

condition) Burst = 2; Writes; Continuous burst; One device

bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

TBD

1,971

TBD

AUTO REFRESH CURRENT: An AUTO REFRESH command is given to one
die, and on the next clock cycle the second die receives an AUTO

REFRESH command.

RC =

RC(MIN), CKE = HIGH

DD5

TBD

8,460

TBD

20, 44

AUTO REFRESH DISTRIBUTED CURRENT: An AUTO REFRESH command
given to one die and on the next clock cycle the second die recieves an

AUTO REFRESH command.

RC = 7.8125µs, CKE = LOW for

RFC time.

DD5A

TBD

360

TBD

24, 44

SELF REFRESH CURRENT: Both die are in I

DD6

condition, CKE

£ 0.2V

DD6

TBD

288

TBD

OPERATING CURRENT: One die in I

DD7

condition, one die in I

DD3N

condition. (I

DD7

condition) Four device bank interleaving READs (BL = 4)

with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and

control inputs change only during active READ or WRITE commands.

DD7

TBD

3,906

TBD

20, 43

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 13: I

Specifications and Conditions (MT36VDDT12872D)

Notes: 15, 8, 10, 12; DDR SDRAM components; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-262

-26A/

-265

-202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

(MIN);

CK =

CK (MIN); DQ, DM and DQS inputs changing once per clock

cyle; Address and control inputs changing once every two clock cycles;

DD0

1,233

1,053

1,188

20, 42

OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst =

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address and control

inputs changing once per clock cycle

DD1

1,548

1,413

1,503

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;

Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

144

21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

1,620

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;

Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

900

1,080

21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;

Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM and DQS

inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle

DD3N

1,800

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

1,458

1,683

20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

1,323

1,818

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

8,460

8,820

20, 44

RC = 7.81µs

DD5A

216

24, 44

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

144

OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with

auto precharge with,

RC = minimum

RC allowed;

CK =

CK (MIN);

Address and control inputs change only during Active READ, or WRITE
commands.

DD7

3,258

3,393

20, 43

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

1GB, 2GB (x72, ECC)

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128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 14: I

Specifications and Conditions (MT36VDDS25672D)

Notes: 15, 8, 10, 12; DDR SDRAM components; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-262

-26A/

-265

-202

UNITS NOTES

OPERATING CURRENT: One die in I

DD0

condition, one die in I

DD2P

condition. (I

DD0

Condition) one device bank; Active-Precharge;

RC=

(MIN);

CK=

CK (MIN); DQ, DM and DQS inputs changing once per clocke

cycle; Address and control inputs changing once every two clock cycles.

DD0

TBD

20, 42

OPERATING CURRENT: One die in I

DD1

condition, one die in I

DD2P

condition. (I

1 Condition) one device bank; Active-Precharge; Burst = 2;

RC=

RC (MIN);

CK=

CK (MIN); Iout = 0mA; Address and control inputs

changing once per clock cycle.

DD1

TBD

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: Both die in I

DD2P

condition . (I

DD2P

Condition) All device banks idle; Power-down mode;

CK=

CK (MIN); CKE= LOW

DD2P

TBD

21, 28,

IDLE STANDBY CURRENT: Both die in I

DD2F

condition. (I

DD2F

Condition)

CS# = HIGH; All device banks idle;

CK =

CK (MIN); CK = HIGH; Address

and other control inputs changing once per clock cycle. V

= V

REF

for

DQ, DQS and DM

DD2F

TBD

ACTIVE POWER-DOWN STANDBY CURRENT: Both die in I

DD3P

condition.

3P Condition) One device bank active; Power-down mode;

CK = CK (MIN); CKE= LOW

DD3P

TBD

21, 28,

ACTIVE STANDBY CURRENT: Both die in I

DD3N

condition. (I

DD3N

condition)

CS# = HIGH; CKE= HIGH; One device bank active;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM and DQS inputs changing twice per clock cycle;

Address and other control inputs changing once per clock cycle

DD3N

TBD

OPERATING CURRENT: One die in I

DD4R

condition, one die in I

DD2P

condition. (I

DD4R

condition) Burst = 2; Reads; Continuous burst; One

device bank active; Address and control inputs changing once per clock

cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

TBD

20, 42

OPERATING CURRENT: One die in I

DD4W

condition, one die in I

DD2P

con-

dition. (I

DD4W

condition) Burst = 2; Writes; Continuous burst; One device

bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

TBD

AUTO REFRESH CURRENT: An AUTO REFRESH command is given to one
die, and on the next clock cycle the second die receives an AUTO

REFRESH command.

RC =

RC(MIN), CKE = HIGH

DD5

TBD

20, 44

AUTO REFRESH DISTRIBUTED CURRENT: An AUTO REFRESH command
given to one die and on the next clock cycle the second die recieves an

AUTO REFRESH command.

RC = 7.8125µs, CKE = LOW for

RFC time.

DD5A

TBD

24, 44

SELF REFRESH CURRENT: Both die are in I

DD6

condition, CKE

£ 0.2V

DD6

TBD

OPERATING CURRENT: One die in I

DD7

condition, one die in I

DD3N

condition. (I

DD7

condition) Four device bank interleaving READs (BL = 4)

with auto precharge,

RC =

RC (MIN);

CK =

CK (MIN); Address and

control inputs change only during active READ or WRITE commands.

DD7

TBD

20, 43

NOTE:

a - Value calculated as one module bank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

1GB, 2GB (x72, ECC)

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128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 15: I

Specifications and Conditions (MT36VDDT25672D)

Notes: 15, 8, 10, 12; DDR SDRAM components; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

, V

Q = +2.5V ±0.2V

MAX

PARAMETER/CONDITION

SYM

-262

-26A/

-265

-202

UNITS NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

(MIN);

CK =

CK (MIN); DQ, DM and DQS inputs changing once per clock

cyle; Address and control inputs changing once every two clock cycles;

DD0

TBD

945

1,332

20, 42

OPERATING CURRENT: One device bank; Active-Read-Precharge; Burst =

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address and control

inputs changing once per clock cycle

DD1

TBD

1,170

1,467

20, 42

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;

Power-down mode;

CK =

CK (MIN); CKE = (LOW)

DD2P

TBD

180

216

21, 28,

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

MIN; CKE = HIGH; Address and other control inputs changing once per
clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

TBD

1,440

1,260

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;

Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

TBD

648

900

21, 28,

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank;

Active-Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM and DQS

inputs changing twice per clock cycle; Address and other control inputs
changing once per clock cycle

DD3N

TBD

1,440

1,260

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

TBD

1,665

1,647

20, 42

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

TBD

1,845

1,737

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

TBD

1,845

2,997

20, 44

RC = 7.81µs

DD5A

TBD

288

252

24, 44

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

TBD

108

252

OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with

auto precharge with,

RC = minimum

RC allowed;

CK =

CK (MIN);

Address and control inputs change only during Active READ, or WRITE
commands.

DD7

TBD

2,835

3,987

20, 43

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in I

(CKE LOW) mode.

b - Value calculated reflects all module ranks in this operating condition.

1GB, 2GB (x72, ECC)

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128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

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DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 16: Capacitance (MT36VDDS12872D and MT36VDDT12872D)

Note: 11; notes appear on pages 1922

PARAMETER

SYMBOL

MIN

MAX

Input/Output Capacitance: DQ, DQS/DM

16.0

20.0

Input Capacitance: Command and Address

2.5

3.5

Input Capacitance: S#

2.5

3.5

Input Capacitance: CK, CK#

Input Capacitance: CKE

2.5

3.5

Table 17: Capacitance (MT36VDDS25672D and MT36VDDT25672D)

Note: 11; notes appear on pages 1922

PARAMETER

SYMBOL

MIN

MAX

Input/Output Capacitance: DQ, DQS/DM

TBD

Input Capacitance: Command and Address

TBD

Input Capacitance: S#

TBD

Input Capacitance: CK, CK#

TBD

Input Capacitance: CKE

TBD

Table 18: DDR SDRAM Electrical Characteristics and Recommended AC Operating

Conditions

Notes: 15, 1215, 29; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

ACCHARACTERISTICS

-262

-26A/-265

-202

UNITS NOTES

PARAMETER

SYM

MIN

MAX

MIN

MAX

MIN

MAX

Access window of DQs from CK/CK#

-0.70

+0.70

-0.75

+0.75

-0.8

+0.75

CK high-level width

0.45

0.55

0.45

0.55

0.45

0.55

CK low-level width

0.45

0.55

0.45

0.55

0.45

0.55

Clock cycle time

CL = 2.5

CK (2.5)

7.5

40, 46

CL = 2

CK (2)

7.5

40, 46

DQ and DM input hold time relative to DQS

0.45

0.5

0.6

23, 27

DQ and DM input setup time relative to DQS

0.45

0.5

0.6

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.65

+0.6

-0.75

+0.75

-0.8

+0.75

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group,
per access

DQSQ

0.45

0.5

22, 23

Write command to first DQS latching
transition

DQSS

0.75

1.25

0.75

1.25

0.75

1.25

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.7

+0.75

16, 37

1GB, 2GB (x72, ECC)

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DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Data-out low-impedance window from CK/CK#

-0.7

-0.75

-0.8

16,38

Address and control input hold time (fast slew
rate)

0.75

0.90

1.1

Address and control input setup time (fast
slew rate)

0.75

0.90

1.1

Address and control input hold time (slow slew
rate)

0.8

1.1

Address and control input setup time (slow
slew rate)

0.8

1.1

Address and control input pulse width (for
each input)

IPW

2.2

2.5

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid,
per access

HP-

QHS

HP-

QHS

HP -

QHS

22, 23

Data Hold Skew Factor

QHS

0.75

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to READ with Auto Precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command
period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

0.9

1.1

0.9

1.1

DQS read postamble

RPST

0.4

0.6

0.4

0.6

0.4

0.6

ACTIVE bank a to ACTIVEbank b command

RRD

DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

0.4

0.6

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window (DVW)

QH -

DQSQ

QH -

DQSQ

QH -

DQSQ

REFRESH to REFRESH command interval

REFC

70.3

Average periodic refresh interval

REFI

7.8

µs

Terminating voltage delay to V

VTD

µs

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 18: DDR SDRAM Electrical Characteristics and Recommended AC Operating

Conditions (Continued)

Notes: 15, 1215, 29; notes appear on pages 1922; 0

°C £ T

£ +70°C; V

= V

Q = +2.5V ±0.2V

ACCHARACTERISTICS

-262

-26A/-265

-202

UNITS NOTES

PARAMETER

SYM

MIN

MAX

MIN

MAX

MIN

MAX

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DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing, I

, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to V

REF

(or to the

crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(

)

and V

(

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal V

Q/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on V

REF

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

by-pass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle
time at CL = 2 for -262 and -26A; CL = 2.5 for -265 with
the outputs open.

9. Enables on-chip refresh and address counters.

10. I

specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

11. This parameter is sampled. V

= +2.5V ±0.2V,

Q = +2.5V ±0.2V, V

REF

= VSS, f = 100 MHz, T

°C, V

OUT

(DC) = V

Q/2, V

OUT

(peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.

12. Command/Address input slew rate = 0.5V/ns. For

-262, -26A, and -265 with slew rates 1V/ns and
faster,

IS and

IH are reduced to 900ps. If the slew

rate is less than 0.5V/ns, timing must be derated:

IS has an additional 50ps per each 100mV/ns

reduction in slew rate from the 500mV/ns, while

IH remains constant. If the slew rate exceeds

4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for

ignals

other than CK/CK# is V

REF

14. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before V

REF

stabilizes, CKE

£ 0.3 x V

Q is recognized as LOW.

15. The output timing reference level, as measured at

the timing reference point indicated in Note 3, is
V

16.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

17. The maximum limit for this parameter is not a

device limit. The device will operate with a greater
value for this parameter, but system performance
(bus turnaround) will degrade accordingly.

18. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on

DQSS.

20. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

(MAX) for I

measurements is the largest multi-

ple of

CK that meets the maximum absolute

value for

RAS.

Output
(V

OUT

)

30pF

1GB, 2GB (x72, ECC)

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128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 7.821µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.

22. The valid data window is derived by achieving

other specifications -

HP (

CK/2),

DQSQ, and

QH (

QH =

HP -

QHS). The data valid window

derates directly porportional with the clock duty
cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty
cycle variation of 45/55. Functionality is uncer-
tain when operating beyond a 45/55 ratio. Figure
7, Derating Data Valid Window (

QH -

DQSQ),

shows the derating curves for duty cycles ranging
between 50/50 and 45/55.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during
REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:

a. Sustain a constant slew rate from the current

AC level through to the target AC level, V

(

)

or V

(

b.Reach at least the target AC level.

c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(

) or

(

26. JEDEC specifies CK and CK# input slew rate must

³ 1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to

DS and

DH for each 100mv/ns reduction in slew rate. If

slew rate exceeds 4V/ns, functionality is uncer-
tain.

28. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

Figure 7: Derating Data Valid Window (

QH -

DQSQ)

3.750

3.700

3.650

3.600

3.550

3.500

3.450

3.400

3.350

3.300

3.250

3.400

3.350

3.300

3.250

3.200

3.150

3.100

3.050

3.000

2.950

2.900

2.500

2.463

2.425

2.388

2.350

2.313

2.275

2.238

2.200

2.163

2.125

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

3.8

50/50

49.5/50.5 49/51

48.5/52.5

48/52

47.5/53.5

47/53

46.5/54.5

46/54

45.5/55.5

45/55

Clock Duty Cycle

-26A/-265 @

CK = 10ns

-202 @

CK = 10ns

-26A/-265 @

CK = 7.5ns

-202 @

CK = 8ns

-262 @

CK = 7.5ns

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

30.

HP min is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK# inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS(MIN) can be satis-

fied prior to the internal precharge command
being issued.

32. Any positive glitch must be less than 1/3 of the

clock and not more than +400mV or 2.9V, which-
ever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -
300mV or 2.2V, whichever is more positive.

33. Normal Output Drive Curves:

a. The full variation in driver pull-down current

from minimum to maximum process, temper-
ature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.

b. The variation in driver pull-down current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 8,
Pull-Down Characteristics.

c. The full variation in driver pull-up current from

minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 9, Pull-Up Char-
acteristics.

d. The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 9,
Pull-Up Characteristics.

e. The full variation in the ratio of the maximum to

minimum pull-up and pull-down current

should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f. The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.

34. The voltage levels used are derived from a mini-

mum V

level and the referenced test load. In

practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.

35. V

overshoot: V

(MAX) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

l undershoot:

(MIN) = -1.5V for a pulse width

£ 3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

36. V

and V

DDQ

must track each other.

37. This maximum value is derived from the refer-

enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for

HZ(MAX) and the last DVW.

HZ(MAX) will prevail over

DQSCK(MAX) +

RPST(MAX) condition.

LZ(MIN) will prevail over

DQSCK(MIN) +

RPRE(MAX) condition.

38. or slew rates greater than 1V/ns the (LZ) transition

will start about 310ps earlier.

39. During initialization, V

DDQ

, V

, and V

REF

must be

equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if
V

DDQ

are 0V, provided a minimum of 42

W of

series resistance is used between the V

supply

and the input pin.

Figure 8: Pull-Down Characteristics

Figure 9: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

-20

OUT

(mA)

Nom

inal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

41. For the -262, -26A, and -265 modules, I

3N is

specified to be 35mA at 100 MHz.

42. Random addressing changing and 50 percent of

data changing at every transfer.

43. Random addressing changing and 100 percent of

data changing at every transfer.

44. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until

REF later.

45. I

2N specifies the DQ, DQS, and DM to be

driven to a valid high or low logic level. I

2Q is

similar to I

2F except I

2Q specifies the

address and control inputs to remain stable.
Although I

2F, I

2N, and I

2Q are similar,

2F is "worst case."

46. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.

47. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

NOTE:

1. This parameter is not necessarily production tested.
2. Data inputs must be low a minimum time of

act MAX, after RESET is taken HIGH.

3. Data and clock inputs must be held at valid levels (not floating) a minimum time of

inact MAX, after RESET# is taken

LOW.

4. For data signal input slew rate

³ 1 V/ns.

5. For data signal input slew rate

³ 0.5 V/ns and < 1 V/ns.

6. CK, CK# signals input slew rates are

³ 1 V/ns.

Table 19: Register Timing Requirements and Switching Characteristics

Notes: 26

PARAMETER

SYMBOL

CONDITIONS

°C £ T

£ +70°C

= 2.5V ± 0.2V

UNITS NOTES

MIN

MAX

1:1

13-26 bit

SSTL

Clock Frequency

clock

200

MHz

Pulse duration, CK, CK# HIGH or
LOW

2.5

Differential inputs, active time
(see Note 1)

act

Differential inputs, inactive time
(see Note 2)

inact

Setup time, fast slew rate
(See Notes 3 and 5)

Data before

, CK¯

0.75

Setup time, slow slew rate
(See Notes 4 and 5)

0.9

Hold time, fast slew rate
(See Notes 3 and 5)

Data after

, CK¯

0.75

Hold time, slow slew rate
(See Notes 4 and 5)

0.9

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

NOTE:

1. The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM

Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module.
Detailed information for this PLL is available in JEDEC Standard JESD82.

2.The PLL must be able to handle spread spectrum induced skew.
3.Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to

meet the other timing parameters. (Used for low-speed system debug.)

4.Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its

reference signal after power up.

5.Static Phase Offset does not include Jitter.
6.Period jitter and half-period jitter specifications are separate specifications that must be met independently of each

other.

7.The output slew rate is determined from the IBIS model:

Table 20: PLL Clock Driver Timing Requirements and Switching Characteristics

Note: 1

PARAMETER

SYMBOL

TEST CONDITIONS

= 070ºC

= 2.5V ± 0.2V

UNITS

NOTES

MIN

NOM

MAX

Clock frequency

167

MHz

2, 3

Input clock duty cycle

40%

60%

Stabilization time

0.1

Low-to high level
propagation delay time

PLH

CK mode/CK to any output

1.5

3.5

High-to low level
propagation delay time

PHL

CK mode/CK to any output

1.5

3.5

Output enable time

CK mode/G to any Y output

Output disable time

dis

CK mode/G to any Y output

Jitter (peak-to-peak)

(jitter)

66 MHz

120

100/125/133/167 MHz

Jitter (cycle-to-cycle)

(jitter)

66 MHz

110

100/125/133/167 MHz

2, 3

Phase error

(phase

error)

Terminated with 120

W/16pF

-150

150

Output skew

skew(o)

Terminated with 120

W/16pF

100

Pulse skew

dis

Terminated with 120

W/16pF

100

Duty cycle

66 MHz to 100 MHz

49.5%

50.5%

101 MHz to 167 MHz

49%

51%

Output rise and fall
times (20% - 80%)

Load = 120

W/16pF

650

800

950

GND

CDCV857

R=60

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Figure 10: Component Case Temperature Vs. Air Flow

NOTE:

1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across MT36VDDS12872D,

MT36VDDT12872D, MT36VDDS25672D, and MT36VDDT25672D modules when installed in a system.

2. The component case temperature measurements shown above were obtained experimentally. The typical system to be

used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered
memory modules. Case temperatures charted represent worst-case component locations on modules installed in the
internal slots of the system.

3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from

its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard
for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test
chamber.

4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic soft-

ware application developed for internal use by Micron Technology, Inc.

100

0.0

0.5

1.0

2.0

Air Flow (meters/sec)

Degrees Celsius

Ambient Temperature = 25º C

max

- memory stress software

ave

- 3D gaming software

ave

- memory stress software

Minimum Air Flow

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 11, Data Validity, and Figure 12, Defi-
nition of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 13, Acknowledge Response from Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 11: Data Validity

Figure 12: Definition of Start and Stop

Figure 13: Acknowledge Response from Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

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DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Table 21: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 22: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = `1'

Random Address Read

or V

START, Device Select, RW = `0', Address

or V

reSTART, Device Select, RW = `1'

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = `0'

Page Write

£ 16

START, Device Select, RW = `0'

Table 23: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

DDSPD

2.3

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

DDSPD

0.7

DDSPD

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

DDSPD

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V; All other inputs = V

or V

µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

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DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

Figure 14: SPD EEPROM Timing Diagram

NOTE:

1. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

Table 24: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

µs

Time the bus must be free before a new transition can start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

ClockHIGHperiod

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

1GB, 2GB (x72, ECC)

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Table 25: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of SPD Matrix

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT36VDDS12872D/

MT36VDDT12872D

MT36VDDS25672D/

MT36VDDT25672D

Number of Bytes Used by Micron

128

Total Number of SPD Memory Bytes

256

Memory Type

DDR SDRAM

Number of Row Addresses

Number of Column Addresses

10 or 11

Number of Module Ranks

Module Data Width

Module Data Width (continued)

Module Voltage Interface Levels

SSTL 2.5V

SDRAM Cycle Time,

CK, CAS Latency = 2.5,

(See note 1)

7ns(-262/-26A)

7.5ns (-265)

8ns (-202)

70
75
80

SDRAM Access From Clock,

AC,

CAS Latency = 2.5

0.75ns (-262/-26A/-265)

0.8ns (-202)

75
80

Module Configuration Type

ECC

Refresh Rate/ Type

7.81µs/SELF

SDRAM Width (Primary SDRAM)

Error-checking SDRAM Data Width

Minimum Clock Delay, Back-to-Back
Random Column Access

Burst Lengths Supported

2, 4, 8

Number of Banks on SDRAM Device

CAS Latencies Supported

2, 2.5

CS Latency

WE Latency

SDRAM Module Attributes

Registered, PLL

SDRAM Device Attributes: General

Fast/Concurrent AP

SDRAM Cycle Time,

CK,CAS Latency = 2

7.5ns (-262/-26A)

10ns (-265/-202)

SDRAM Cycle Time,

CK, CAS Latency = 2

7.5ns

SDRAM Cycle Time,

CK, CAS Latency = 1

SDRAM Access From CK,

AC, CAS Latency = 1

Minimum Row Precharge Time,

15ns (-262)

20ns (-26A/-265/-202)

3C
50

Minimum Row Active to Row Active,

RRD

15ns

Minimum RAS# to CAS# Delay,

RCD

15ns (-262)

20ns (-26A/-265/-202)

3C
50

Minimum RAS# Pulse Width,

RAS

(See note 2)

45ns (-262/-26A/-265)

40ns (-202)

Module Rank Density

256MB or 512MB

Address and Command Setup Time,

IS,

(See note 3)

1.0ns (-262/-26A/-265)

1.1ns (-202)

Address and Command Hold Time,

(See note 3)

1.0ns (-262/-26A/-265)

1.1ns (-202)

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

NOTE:

1. Value for -26A

CK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. value is 7.5ns.

2. The value of

RAS for -262, -26A, and -265 modules is calculated from

RC -

RP. Actual device spec. value is 40ns.

3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is

represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster mini-
mum slew rate is met.

Data/Data Mask Input Setup Time,

0.5ns (-262/-26A/-265)

0.6ns (-202)

50
60

Data/Data Mask Input Hold Time,

0.5ns (-262/-26A/-265)

0.6ns (-202)

50
60

36-40

Reserved

Minimum Active/auto Refresh Time,

60ns (-262)

65ns (-26A/-265)

70ns (-202)

3C
41
46

Minimum Auto Refresh to Active/ Auto

Refresh Command Period,

RFC

75ns (-262/-26A/-265)

80ns (-202)

4B
50

Maximum Cycle Time,

CK(MAX)

13ns

Maximum DQS-DQ SKEW TIME,

DQSQ

0.5ns (-262/-26A/-265)

0.6ns (-202)

32
3C

Maximum Read Data Hold Skew Factor,

QHS

0.75ns (-262/-26A/-265)

1.0ns (-202)

Reserved

DIMM Height

4861

Reserved

SPD Revision

Release 1.0

Checksum for Bytes 0-62

-262

-26A

-265
-202

02
32

16
43
73
0E

Manufacturer's JEDEC ID Code

MICRON

65-71

Manufacturer's JEDEC ID Code

(continued)

Manufacturing Location

1 - 12

01 - 0C

73-90

Module Part Number (ASCII)

Variable Data

PCB Identification Code

1 - 9

01-09

Identification Code (Continued)

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98

Module Serial Number

Variable Data

99-127

Manufacturer-Specific Data (RSVD)

Table 25: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"; notes at end of SPD Matrix

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT36VDDS12872D/

MT36VDDT12872D

MT36VDDS25672D/

MT36VDDT25672D

1GB, 2GB (x72, ECC)

184-PIN REGISTERED DDR SDRAM DIMM

128Meg (x72) 184-pin Registered QUAD-BANK DDRSDRAM DIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DD36C128_256x72DG_C.fm - Rev. C 7/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 15: Low-Profile 184-Pin DIMM (Quad Rank)

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

Data Sheet Designation

Advance: This data sheet contains initial descrip-

tions of products still under development.

.054 (1.37)
.046 (1.17)

.268 (6.81)

MAX

1.205 (30.61)
1.195 (30.35)

PIN 1

.700 (17.78)

TYP.

.098 (2.50) D

(2X)

.091 (2.30) TYP.

.250 (6.35) TYP.

4.750 (120.65)

.050 (1.27)

TYP.

.091 (2.30)

TYP.

.040 (1.02)

TYP.

.079 (2.00) R

(4X)

.035 (0.90) R

PIN 92

FRONT VIEW

5.256 (133.50)
5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

.394 (10.00)

TYP.

U19

U20

BACK VIEW

PIN 184

PIN 93

U10

U11

U12

U13

U14

U21

U22

U15

U16

U17

U18

.054 (1.37)
.046 (1.17)

.157 (3.99)

MAX

TwinDie DDR

36VDDS12872D

Stacked TSOP DDR

36VDDT12872D

MAX

MIN

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