Document Outline
- Features
- Options
- DDR333 Compatibility
- Configuration
- Key Timing Parameters
- FBGA 60-Ball Package Dimension
- FBGA Package Marking
- FBGA Package Pinout
- 66-Pin TSOP Package Dimension
- 66-Pin TSOP Package Pin Assignment
- Pin Descriptions
- General Description
- Capacitance (FBGA)
- Capacitance (TSOP)
- Electrical Characteristics and Recommended AC Operating Conditions
1
256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION AND DATA SHEET SPECIFICATIONS.
PRELIMINARY
Architecture
64 Meg x 4
32 Meg x 8
16 Meg x 16
Configuration
16 Meg x 4 x 4 banks 8 Meg x 8 x 4 banks 4 Meg x 16 x 4 banks
Refresh Count
8K
8K
8K
Row Addressing
8K (A0A12)
8K (A0A12)
8K (A0A12)
Bank Addressing
4 (BA0, BA1)
4 (BA0, BA1)
4 (BA0, BA1)
Column Addressing
2K (A0A9, A11)
1K (A0A9)
512 (A0 A8)
DOUBLE DATA RATE
(DDR) SDRAM
MT46V64M4 16 Meg x 4 x 4 banks
MT46V32M8 8 Meg x 8 x 4 banks
MT46V16M16 4 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site:
www.micron.com/dramds
FEATURES
167 MHz Clock, 333 Mb/s/p data rate
V
DD
= +2.5V 0.2V, V
DD
Q = +2.5V 0.2V
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (x16 has two - one per byte)
Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
Differential clock inputs (CK and CK#)
Commands entered on each positive CK edge
DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
DLL to align DQ and DQS transitions with CK
Four internal banks for concurrent operation
Data mask (DM) for masking write data (x16 has
two - one per byte)
Programmable burst lengths: 2, 4, or 8
Concurrent Auto Precharge option supported
Auto Refresh and Self Refresh Modes
FBGA package available
2.5V I/O (SSTL_2 compatible)
t
RAS lockout (
t
RAP =
t
RCD)
Backwards compatible with DDR200 and DDR266
OPTIONS PART NUMBER
Configuration
64 Meg x 4 (16 Meg x 4 x 4 banks)
64M4
32 Meg x 8 (8 Meg x 8 x 4 banks)
32M8
16 Meg x 16 (4 Meg x 16 x 4 banks)
16M16
Plastic Package
66-Pin TSOP (OCPL)
T G
60-Ball FBGA (16x9mm)
FJ
Timing - Cycle Time
6ns @ CL = 2.5 (DDR333BFBGA)
1
-6
6ns @ CL = 2.5 (DDR333BTSOP)
1
-6T
7.5ns @ CL = 2 (DDR266A)
2
-75Z
Self Refresh
Standard
none
NOTE: 1. Supports PC2700 modules with 2.5-3-3 timing
2. Supports PC2100 modules with 2-3-3 timing
CONFIGURATION
DDR333 COMPATIBILITY
DDR333 meets or surpasses all DDR266 timing re-
quirements thus assuring full backwards compatibility
with current DDR designs. In addition, these devices
support concurrent auto-precharge and
t
RAS lockout
for improved timing performance. The 256Mb,
DDR333 device will support an (
t
REFI) average peri-
odic refresh interval of 7.8us.
The standard 66-pin TSOP package is offered for
point-to-point applications where the FBGA package
is intended for the multi-drop systems.
The Micron 256Mb data sheet provides full specifi-
cations and functionality unless specified herein.
KEY TIMING PARAMETERS
3
SPEED
CLOCK RATE
DATA-OUT
ACCESS DQS-DQ
GRADE
CL = 2
1
CL = 2.5
1
WINDOW
2
WINDOW
SKEW
-6
133 MHz
167 MHz
2.15ns
0.70ns
+0.35ns
-6T
133 MHz
167 MHz
2.0ns
0.75ns
+0.45ns
-75Z
133 MHz
133 MHz
2.5ns
0.75ns
+0.50ns
NOTE:
1. CL = CAS (Read) Latency
2. With a 50/50 clock duty cycle and a minimum clock
rate @ CL = 2 ( -75Z) and CL = 2.5 (-6, -6T).
3. -75, -8 are also available; see base data sheet.
2
256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRELIMINARY
FBGA PACKAGE PINOUT
V
SS
Q
DQ14
DQ12
DQ10
DQ8
V
REF
DQ15
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
CK
A12
A11
A8
A6
A4
V
SS
DQ13
DQ11
DQ9
UDQS
UDM
CK#
CKE
A9
A7
A5
V
SS
V
DD
DQ2
DQ4
DQ6
LDQS
LDM
WE#
RAS#
BA1
A0
A2
V
DD
DQ0
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
DD
CAS#
CS#
BA0
A10
A1
A3
V
DD
Q
DQ1
DQ3
DQ5
DQ7
A13
x16 (Top View)
V
SS
Q
NC
NC
NC
NC
V
REF
NC
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
CK
A12
A11
A8
A6
A4
V
SS
DQ3
NC
DQ2
DQS
DM
CK#
CKE
A9
A7
A5
V
SS
V
DD
DQ0
NC
DQ1
NC
NC
WE#
RAS#
BA1
A0
A2
V
DD
NC
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
DD
CAS#
CS#
BA0
A10
A1
A3
V
DD
Q
NC
NC
NC
NC
A13
x4 (Top View)
V
SS
Q
NC
NC
NC
NC
V
REF
DQ7
V
DD
Q
V
SS
Q
V
DD
Q
V
SS
Q
V
SS
CK
A12
A11
A8
A6
A4
V
SS
DQ6
DQ5
DQ4
DQS
DM
CK#
CKE
A9
A7
A5
V
SS
V
DD
DQ1
DQ2
DQ3
NC
NC
WE#
RAS#
BA1
A0
A2
V
DD
DQ0
V
SS
Q
V
DD
Q
V
SS
Q
V
DD
Q
V
DD
CAS#
CS#
BA0
A10
A1
A3
V
DD
Q
NC
NC
NC
NC
A13
x8 (Top View)
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
L
A
B
C
D
E
F
G
H
J
K
M
L
A
B
C
D
E
F
G
H
J
K
M
FBGA PACKAGE MARKING
FBGA 60-BALL PACKAGE DIMENSION
Due to the physical size of the FBGA package, the full
ordering part number is not printed on the package.
Instead the following package code is utilized.
Top mark contains five fields
12345
Field 1 (Product Family)
DRAM
D
DRAM - ES
Z
Field 2 (Product Type)
2.5 Volt, DDR SDRAM, 60-ball
L
Field 3 (Width)
x4 devices
B
x8 devices
C
x16 devices
D
Field 4 (Density / Size)
256Mb
H
Filed 5 (Speed Grade)
-6
J
-75Z
P
-75
F
-8
C
Example top mark for a MT46V32M4FJ-6: DLBFJ
1.20 MAX
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb or
62% Sn, 36% Pb, 2%Ag
SOLDER BALL PAD: .33mm
0.850 0.075
16.00 0.10
8.00 0.05
SEATING PLANE
C
0.10 C
BALL A1
BALL A9
PIN A1 ID
61X
0.45
SOLDER BALL DIAMETER
REFERS TO POST REFLOW
CONDITION. THE PRE-
REFLOW DIAMETER IS 0.40
5.50 0.05
11.00
1.00
TYP
0.80 TYP
1.80
CTR
9 .00 0.10
3.20 0.05
4.50 0.05
6.40
C
L
C
L
Bottom View
3
256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRELIMINARY
66-PIN TSOP PACKAGE PIN ASSIGMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
V
SS
DQ15
V
SS
Q
DQ14
DQ13
V
DD
Q
DQ12
DQ11
V
SS
Q
DQ10
DQ9
V
DD
Q
DQ8
NC
V
SS
Q
UDQS
DNU
V
REF
V
SS
UDM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x16
V
DD
DQ0
V
DD
Q
DQ1
DQ2
VssQ
DQ3
DQ4
V
DD
Q
DQ5
DQ6
VssQ
DQ7
NC
V
DD
Q
LDQS
NC
V
DD
DNU
LDM
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
x16
V
SS
DQ7
V
SS
Q
NC
DQ6
V
DD
Q
NC
DQ5
V
SS
Q
NC
DQ4
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
x8
x4
V
SS
NC
V
SS
Q
NC
DQ3
V
DD
Q
NC
NC
V
SS
Q
NC
DQ2
V
DD
Q
NC
NC
V
SS
Q
DQS
DNU
V
REF
V
SS
DM
CK#
CK
CKE
NC
A12
A11
A9
A8
A7
A6
A5
A4
V
SS
V
DD
DQ0
V
DD
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
DD
Q
NC
DQ3
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
x8
x4
V
DD
NC
V
DD
Q
NC
DQ0
V
SS
Q
NC
NC
V
DD
Q
NC
DQ1
V
SS
Q
NC
NC
V
DD
Q
NC
NC
V
DD
DNU
NC
WE#
CAS#
RAS#
CS#
NC
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
66-PIN TSOP PACKAGE DIMENSION
SEE DETAIL A
0.10
0.65 TYP
0.71
10.16 0.08
0.15
0.50 0.10
PIN #1 ID
DETAIL A
22.22 0.08
0.32 .075 TYP
+0.03
-0.02
+0.10
-0.05
1.20 MAX
0.10
0.25
11.76 0.10
0.80 TYP
0.10 (2X)
GAGE PLANE
(TOP VIEW)
NOTE:
1. All dimensions in millimeters.
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm
per side.
4
256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRELIMINARY
(continued on next page)
PIN DESCRIPTIONS
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL
TYPE
DESCRIPTION
G2, G3
45, 46
CK, CK#
Input
Clock: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.
H3
44
CKE
Input
Clock Enable: CKE HIGH activates and CKE LOW deactivates the
internal clock, input buffers and output drivers. Taking CKE LOW
provides PRECHARGE POWER-DOWN and SELF REFRESH
operations (all banks idle), or ACTIVE POWER-DOWN (row
ACTIVE in any bank). CKE is synchronous for POWER-DOWN
entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit and for disabling the outputs. CKE must be
maintained HIGH throughout read and write accesses. Input
buffers (excluding CK, CK# and CKE) are disabled during POWER-
DOWN. Input buffers (excluding CKE) are disabled during SELF
REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS
LOW level after V
DD
is applied.
H8
24
CS#
Input
Chip Select: CS# enables (registered LOW) and disables (regis-
tered HIGH) the command decoder. All commands are masked
when CS# is registered HIGH. CS# provides for external bank
selection on systems with multiple banks. CS# is considered part
of the command code.
H7, G8, G7
23, 22, 21
RAS#, CAS#,
Input
Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
WE#
command being entered.
3F
47
DM
Input
Input Data Mask: DM is an input mask signal for write data. Input
F7, 3F
20, 47
LDM, UDM
data is masked when DM is sampled HIGH along with that input
data during a WRITE access. DM is sampled on both edges of
DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. For the x16 , LDM is
DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC
on x4 and x8
J8,J7
26, 27
BA0, BA1
Input
Bank Address Inputs: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
K7, L8, L7
29-32
A0, A1, A2
Input
Address Inputs: Provide the row address for ACTIVE commands, and
M8, M2, L3
32, 35, 36
A3, A4, A5
the column address and auto precharge bit (A10) for READ/WRITE
L2, K3, K2
36, 38, 39
A6, A7, A8
commands, to select one location out of the memory array in the
J3, K8, J2
40, 29, 41
A9, A10, A11
respective bank. A10 sampled during a PRECHARGE command
H2
42
A12
determines whether the PRECHARGE applies to one bank (A10 LOW,
bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs
also provide the op-code during a MODE REGISTER SET command. BA0
and BA1 define which mode register (mode register or extended mode
register) is loaded during the LOAD MODE REGISTER command.
5
256Mb: x4, x8, x16 DDR333 SDRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
256Mx4x8x16DDR333_B.p65 Rev. B; Pub. 10/01
2001, Micron Technology, Inc.
256Mb: x4, x8, x16
DDR333 SDRAM Addendum
PRELIMINARY
PIN DESCRIPTIONS (continued)
BALL / PIN NUMBERS
FBGA
TSOP
SYMBOL
TYPE
DESCRIPTION
A8, B9, B7
2, 4, 5,
DQ0-2
I/O
Data Input/Output: Data bus for x16
C9, C7, D9
7, 8, 10
DQ3-5
D7, E9, E1
11, 13, 54
DQ6-8
D3, D1, C3
56, 57, 59
DQ9-11
C1, B3, B1,
60, 62, 63,
DQ12-14
A2
65
DQ15
A8, B7, C7,
2, 5, 8,
DQ0-2
I/O
Data Input/Output: Data bus for x8
D7, D3, C3,
11, 56, 59
DQ3-5
B3, A2
62, 65
DQ6-7
B7, D7, D3,
5, 11, 56
DQ0-2
I/O
Data Input/Output: Data bus for x4
B3
62
DQ2
E3
51
DQS
I/O
Data Strobe: Output with read data, input with write data. DQS is
E7, E3
16, 51
LDQS, UDQS
edge-aligned with read data, centered in write data. It is used to
capture data. For the x16 , LDQS is DQS for DQ0-DQ7 and UDQS
IS DQS for DQ8-DQ15. Pin 16 (H7) is NC on x4 and x8.
14, 17, 25,
NC
-
No Connect: These pins should be left unconnected.
43, 53
19, 50
DNU
Do Not Use: Must float to minimize noise on Vref
B2, D2, C8, 3, 9, 15, 55,
V
DD
Q
Supply
DQ Power Supply: +2.5V 0.2V. Isolated on the die for improved
E8, A9
61
noise immunity.
A1, C2, E2,
6, 12, 52,
V
SS
Q
Supply
DQ Ground. Isolated on the die for improved noise immunity.
B8, D8
58, 64
F8, M7, A7
1, 18, 33
V
DD
Supply
Power Supply: +2.5V 0.2V.
A1, A3, F2,
34, 48, 66
V
SS
Supply
Ground.
M3
F1
49
V
REF
Supply
SSTL_2 reference voltage.
F9
17
A13
I
Address input A13 for 1Gb devices.
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