Document Outline

Features
Options
512Mb SDRAM Part Numbers
Pin Assignment (Top View)
Key Timing Parameters
General Description
Table of Contents
Functional Block Diagrams
- 128 Meg x 4 SDRAM
- 64 Meg x 8 SDRAM
- 32 Meg x 16 SDRAM
Pin Descriptions
Functional Description
Initialization
Register Definition
- Mode Register
- Burst Length
- Burst Type
- CAS Latency
- Operating Mode
- Write Burst Mode
Figure 1 Mode Register Definition
Table 1 Burst Definition
Figure 2 CAS Latency
Table 2 CAS Latency
Commands
- Command Inhibit
- No Operation (NOP)
- Load Mode Register
- Active
- Read
- Write
- Precharge
- Auto Precharge
- Burst Terminate
- Auto Refresh
- Self Refresh
Truth Table 1 - Commands and DQM Operation
Operation
- Bank/Row Activation
- READs
- WRITEs
- Precharge
- Power-Down
- Clock Suspend
- Burst Read/Single Write
- Concurrent Auto Precharge
Figure 3 Activating a Specific Row in a Specific Bank
Figure 4 Example
Figure 5 READ Command
Figure 6 CAS Latency
Figure 7 Consecutive READ Bursts
Figure 8 Random READ Accesses
Figure 9 READ to WRITE
Figure 10 READ to WRITE with Extra Clock Cycle
Figure 11 READ to PRECHARGE
Figure 12 Terminating a READ Burst
Figure 13 WRITE Command
Figure 14 WRITE Burst
Figure 15 WRITE to WRITE
Figure 16 Random WRITE Cycles
Figure 17 WRITE to READ
Figure 18 WRITE to PRECHARGE
Figure 19 Terminating a WRITE Burst
Figure 20 PRECHARGE Command
Figure 21 Power-Down
Figure 22 Clock Suspend During WRITE Burst
Figure 23 Clock Suspend During READ Burst
Figure 24 READ with Auto Precharge Interrupted by a READ
Figure 25 READ with Auto Precharge Interrupted by a WRITE
Figure 26 WRITE with Auto Precharge Interrupted by a READ
Figure 27 READ with Auto Precharge Interrupted by a WRITE
Truth Table 2 - CKE
Truth Table 3 - Current State Bank n - Command to Bank n
Truth Table 4 - Current State Bank n - Command to Bank m
Absolute Maximum Ratings
DC Electrical Characteristics and Operating Conditions
IDD Specifications and Conditions
Capacitance
Electrical Characteristics and Recommended AC Operating Conditions
AC Functional Characteristics
Notes
Initialize and Load Mode Register
Power-Down Mode
Clock Suspend Mode
Auto Refresh Mode
Self Refresh Mode
Read - Without Auto Precharge
Read - With Auto Precharge
Single Read - Without Auto Precharge
Single Read - With Auto Precharge
Alternating Bank Read Accesses
Read - Full-Page Burst
Read - DQM Operation
Write - Without Auto Precharge
Write - With Auto Precharge
Single Write - Without Auto Precharge
Single Write - With Auto Precharge
Alternating Bank Write Accesses
Write - Full-Page Burst
Write - DQM Operation
54-Pin Plastic TSOP

ADVANCE

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE

BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

512Mb: x4, x8, x16

SDRAM

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

KEY TIMING PARAMETERS

SPEED

CLOCK

ACCESS TIME

SETUP

HOLD

GRADE

FREQUENCY CL = 2* CL = 3*

TIME

-7E

143 MHz

5.4ns

1.5ns

0.8ns

-75

133 MHz

5.4ns

1.5ns

0.8ns

-7E

133 MHz

5.4ns

1.5ns

0.8ns

-75

100 MHz

6ns

1.5ns

0.8ns

128 Meg x 4

64 Meg x 8

32 Meg x 16

Configuration

32 Meg x 4 x 4 banks 16 Meg x 8 x 4 banks 8 Meg x 16 x 4 banks

Refresh Count

Row Addressing

8K (A0A12)

Bank Addressing

4 (BA0, BA1)

Column Addressing 4K (A0A9, A11, A12)

2K (A0A9, A11)

1K (A0A9)

SYNCHRONOUS
DRAM

MT48LC128M4A2 32 Meg x 4 x 4 banks
MT48LC64M8A2 16 Meg x 8 x 4 banks
MT48LC32M16A2 8 Meg x 16 x 4 banks

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/dramds

Pin Assignment (Top View)

54-Pin TSOP

FEATURES

· PC100- and PC133-compliant
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can be

changed every clock cycle

· Internal banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, includes CONCURRENT AUTO

PRECHARGE, and Auto Refresh Modes

· Self Refresh Mode
· 64ms, 8,192-cycle refresh
· LVTTL-compatible inputs and outputs
· Single +3.3V ±0.3V power supply

OPTIONS

MARKING

· Configurations

128 Meg x 4 (32 Meg x 4 x 4 banks)

128M4

64 Meg x 8 (16 Meg x 8 x 4 banks)

64M8

32 Meg x 16 (8 Meg x 16 x 4 banks)

32M16

· WRITE Recovery (

WR)

WR = "2 CLK"

· Plastic Package OCPL

54-pin TSOP II (400 mil)

· Timing (Cycle Time)

7.5ns @ CL = 2 (PC133)

-7E

7.5ns @ CL = 3 (PC133)

-75

· Self Refresh

Standard

None

Low power

· Operating Temperature

Commercial (0

C to +70

None

NOTE: 1. Refer to Micron Technical Note TN-48-05.

2. Off-center parting line.

Part Number Example:

MT48LC32M16A2TG-75

NOTE: The # symbol indicates signal is active LOW. A dash

() indicates x8 and x4 pin function is same as x16
pin function.

DQ0

DQ1
DQ2

VssQ

DQ3
DQ4

DQ5
DQ6

VssQ

DQ7

DQML

WE#

CAS#
RAS#

CS#

BA0
BA1

A10

A0
A1
A2
A3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27

54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28

Vss

DQ15

VssQ

DQ14
DQ13

DQ12
DQ11

VssQ

DQ10
DQ9

DQ8

Vss
NC
DQMH
CLK
CKE

A12
A11
A9
A8
A7
A6
A5
A4

Vss

x16

DQ0

DQ1

DQ2

DQ3

DQ0

NC
NC

DQ1

DQ7

DQ6

DQ5

DQ4

DQM

DQ3

NC
NC

DQ2

DQM

*CL = CAS (READ) latency

512Mb SDRAM PART NUMBERS

PART NUMBER

ARCHITECTURE

MT48LC128M4A2TG

128 Meg x 4

MT48LC64M8A2TG

64 Meg x 8

MT48LC32M16A2TG

32 Meg x 16

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst se-
quence.

The 512Mb SDRAM uses an internal pipelined archi-

tecture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch architec-
tures, but it also allows the column address to be changed
on every clock cycle to achieve a high-speed, fully ran-
dom access. Precharging one bank while accessing one of
the other three banks will hide the precharge cycles and
provide seamless, high-speed, random-access operation.

The 512Mb SDRAM is designed to operate at 3.3V. An

auto refresh mode is provided, along with a power-sav-
ing, power-down mode. All inputs and outputs are LVTTL-
compatible.

SDRAMs offer substantial advances in DRAM operat-

ing performance, including the ability to synchronously
burst data at a high data rate with automatic column-
address generation, the ability to interleave between in-
ternal banks to hide precharge time and the capability to
randomly change column addresses on each clock cycle
during a burst access.

GENERAL DESCRIPTION

The 512Mb SDRAM is a high-speed CMOS, dynamic

random-access memory containing 536,870,912 bits. It is
internally configured as a quad-bank DRAM with a syn-
chronous interface (all signals are registered on the posi-
tive edge of the clock signal, CLK). Each of the x4's
134,217,728-bit banks is organized as 8,192 rows by 4,096
columns by 4 bits. Each of the x8's 134,217,728-bit banks
is organized as 8,192 rows by 2,048 columns by 8 bits.
Each of the x16's 134,217,728-bit banks is organized as
8,192 rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-A12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.

The SDRAM provides for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TABLE OF CONTENTS

Functional Block Diagram 128 Meg x 4 ....................

Functional Block Diagram 64 Meg x 8 ...................

Functional Block Diagram 32 Meg x 16 .................

Pin Descriptions ...........................................................

Functional Description ...............................................

Initialization ............................................................

Mode Register ....................................................

Burst Length .................................................

Burst Type ....................................................

CAS Latency ................................................. 10
Operating Mode ........................................... 10
Write Burst Mode ......................................... 10

Commands .................................................................... 11

Truth Table 1 (Commands and DQM Operation)

............ 11

Command Inhibit ................................................... 12
No Operation (NOP) ............................................... 12
Load Mode Register ................................................ 12
Active ....................................................................... 12
Read ....................................................................... 12
Write ....................................................................... 12
Precharge ................................................................. 12
Auto Precharge ........................................................ 12
Burst Terminate ...................................................... 13
Auto Refresh ............................................................ 13
Self Refresh .............................................................. 13

Operation ...................................................................... 14

Bank/Row Activation .............................................. 14
Reads ....................................................................... 16
Writes ....................................................................... 21
Precharge ................................................................. 23
Power-Down ............................................................ 23
Clock Suspend ......................................................... 24

Burst Read/Single Write ......................................... 24
Concurrent Auto Precharge ................................... 25

Truth Table 2 (CKE)

..................................................... 27

Truth Table 3 (Current State, Same Bank)

...................... 28

Truth Table 4 (Current State, Different Bank)

................. 30

Absolute Maximum Ratings ........................................ 32
DC Electrical Characteristics and Operating

Conditions ................................................................ 32

Specifications and Conditions .............................. 32

Capacitance ................................................................... 33

AC Electrical Characteristics (Timing Table) ............ 33

Timing Waveforms

Initialize and Load Mode Register ......................... 36
Power-Down Mode ................................................. 37
Clock Suspend Mode .............................................. 38
Auto Refresh Mode ................................................. 39
Self Refresh Mode ................................................... 40
Reads

Read Without Auto Precharge ....................... 41
Read With Auto Precharge ............................. 42
Single Read Without Auto Precharge ............ 43
Single Read With Auto Precharge ................. 44
Alternating Bank Read Accesses ...................... 45
Read Full-Page Burst ...................................... 46
Read DQM Operation .................................... 47

Writes

Write Without Auto Precharge ...................... 48
Write With Auto Precharge ............................ 49
Single Write Without Auto Precharge ........... 50
Single Write With Auto Precharge ................. 51
Alternating Bank Write Accesses ..................... 52
Write Full-Page Burst ..................................... 53
Write DQM Operation .................................... 54

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

PIN DESCRIPTIONS

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.

18, 17, 16

RAS#, CAS#,

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the

WE#

command being entered.

x4, x8: DQM

Input

Input/Output Mask: DQM is an input mask signal for write accesses and
an output enable signal for read accesses. Input data is masked when

15, 39

x16: DQML,

DQM is sampled HIGH during a WRITE cycle. The output buffers are

DQMH

placed in a High-Z state (two-clock latency) when DQM is sampled HIGH
during a READ cycle. On the x4 and x8, DQML (Pin 15) is a NC and DQMH
is DQM. On the x16, DQML corresponds to DQ0-DQ7 and DQMH
corresponds to DQ8-DQ15. DQML and DQMH are considered same state
when referenced as DQM.

20, 21

BA0, BA1

Input

Bank Address Inputs: BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.

23-26, 29-34, 22, 35, 36

A0A12

Input

Address Inputs: A0-A12 are sampled during the ACTIVE command (row-
address A0-A12) and READ/WRITE command (column-address A0-A9, A11,
A12 [x4]; A0-A9, A11 [x8]; A0-A9 [x16]; with A10 defining auto precharge)
to select one location out of the memory array in the respective bank.
A10 is sampled during a PRECHARGE command to determine if all banks
are to be precharged (A10 [HIGH]) or bank selected by (A10 [LOW]). The
address inputs also provide the op-code during a LOAD MODE REGISTER
command.

2, 4, 5, 7, 8, 10, 11, 13, 42,

DQ0DQ15

x16: I/O Data Input/Output: Data bus for x16 (4, 7, 10, 13, 15, 42, 45, 48, and 51 are

44, 45, 47, 48, 50, 51, 53

NCs for x8; and 2, 4, 7, 8, 10, 13, 15, 42, 45, 47, 48, 51, and 53 are NCs for x4).

2, 5, 8, 11, 44, 47, 50, 53

DQ0DQ7

x8: I/O

Data Input/Output: Data bus for x8 (2, 8, 47, and 53 are NCs for x4).

5, 11, 44, 50

DQ0DQ3

x4: I/O

Data Input/Output: Data bus for x4.

No Connect: This pin should be left unconnected.

3, 9, 43, 49

Supply DQ Power: Isolated DQ power to the die for improved noise immunity.

6, 12, 46, 52

Supply DQ Ground: Isolated DQ ground to the die for improved noise immunity.

1, 14, 27

Supply Power Supply: +3.3V ±0.3V.

28, 41, 54

Supply Ground.

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

FUNCTIONAL DESCRIPTION

In general, the 512Mb SDRAMs (32 Meg x 4 x 4 banks,

16 Meg x 8 x 4 banks, and 8 Meg x 16 x 4 banks) are quad-
bank DRAMs that operate at 3.3V and include a synchro-
nous interface (all signals are registered on the positive
edge of the clock signal, CLK). Each of the x4's 134,217,728-
bit banks is organized as 8,192 rows by 4,096 columns by
4 bits. Each of the x8's 134,217,728-bit banks is organized
as 8,192 rows by 2,048 columns by 8 bits. Each of the x16's
134,217,728-bit banks is organized as 8,192 rows by 1,024
columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an AC-
TIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank, A0-
A12 select the row). The address bits (x4: A0-A9, A11, A12;
x8: A0-A9, A11; x16: A0-A9) registered coincident with the
READ or WRITE command are used to select the starting
column location for the burst access.

Prior to normal operation, the SDRAM must be initial-

ized. The following sections provide detailed informa-
tion covering device initialization, register definition,
command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than
those specified may result in undefined operation. Once
power is applied to V

and V

Q (simultaneously) and

the clock is stable (stable clock is defined as a signal
cycling within timing constraints specified for the clock
pin), the SDRAM requires a 100µs delay prior to issuing
any command other than a COMMAND INHIBIT or NOP.
Starting at some point during this 100µs period and con-
tinuing at least through the end of this period, COM-
MAND INHIBIT or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must then be precharged, thereby placing the
device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for Mode Register pro-
gramming. Because the Mode Register will power up in
an unknown state, it should be loaded prior to applying
any operational command.

MODE REGISTER

The Mode Register is used to define the specific mode

of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency, an
operating mode and a write burst mode, as shown in
Figure 1. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.

Mode Register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the write burst mode, and
M10 and M11 are reserved for future use. Address A12
(M12) is undefined but should be driven LOW during
loading of the Mode Register.

The Mode Register must be loaded when all banks are

idle, and the controller must wait the specified time
before initiating the subsequent operation. Violating ei-
ther of these requirements will result in unspecified op-
eration.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 1. The burst length determines the maxi-
mum number of column locations that can be accessed
for a given READ or WRITE command. Burst lengths of 1,
2, 4 or 8 locations are available for both the sequential
and the interleaved burst types, and a full-page burst is
available for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.

Reserved states should not be used, as unknown op-

eration or incompatibility with future versions may re-
sult.

When a READ or WRITE command is issued, a block of

columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-A9, A11, A12 (x4); A1-A9, A11 (x8); or A1-A9 (x16) when
the burst length is set to two; by A2-A9, A11, A12 (x4); A2-
A9, A11 (x8) or A2-A9 (x16) when the burst length is set to
four; and by A3-A9, A11, A12 (x4); A3-A9, A11 (x8) or A3-A9
(x16) when the burst length is set to eight. The remaining
(least significant) address bit(s) is (are) used to select the
starting location within the block. Full-page bursts wrap
within the page if the boundary is reached.

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

NOTE: 1. For full-page accesses: y = 4,096 (x4); y = 2,048

(x8); y = 1,024 (x16).

2. For a burst length of two, A1-A9, A11, A12 (x4);

A1-A9, A11 (x8); or A1-A9 (x16) select the block-
of-two burst; A0 selects the starting column
within the block.

3. For a burst length of four, A2-A9, A11, A12 (x4);

A2-A9, A11 (x8); or A2-A9 (x16) select the block-
of-four burst; A0-A1 select the starting column
within the block.

4. For a burst length of eight, A3-A9, A11, A12 (x4);

A3-A9, A11 (x8); or A3-A9 (x16) select the block-
of-eight burst; A0-A2 select the starting column
within the block.

5. For a full-page burst, the full row is selected and

A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9
(x16) select the starting column.

6. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

7. For a burst length of one, A0-A9, A11, A12 (x4);

A0-A9, A11 (x8); or A0-A9 (x16) select the unique
column to be accessed, and Mode Register bit M3
is ignored.

Table 1

Burst Definition

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

A11

Reserved*

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = "0, 0, 0"

to ensure compatibility

with future devices.

A12

Figure 1

Mode Register Definition

Burst Type

Accesses within a given burst may be programmed to

be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.

The ordering of accesses within a burst is determined

by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.

Burst

Starting Column

Order of Accesses Within a Burst

Length

Address

Type = Sequential

Type = Interleaved

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

n = A0-A11/9/8

Cn, Cn + 1, Cn + 2

Page

Cn + 3, Cn + 4...

Not Supported

(y)

(location 0-y)

...Cn - 1,

Cn...

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

Operating Mode

The normal operating mode is selected by setting M7

and M8 to zero; the other combinations of values for M7
and M8 are reserved for future use and/or test modes.
The programmed burst length applies to both READ and
WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with fu-
ture versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via

M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.

CAS Latency

The CAS latency is the delay, in clock cycles, between

the registration of a READ command and the availability
of the first piece of output data. The latency can be set to
two or three clocks.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by clock
edge n + m. The DQs will start driving as a result of the
clock edge one cycle earlier (n + m - 1), and provided that
the relevant access times are met, the data will be valid by
clock edge n + m. For example, assuming that the clock
cycle time is such that all relevant access times are met,
if a READ command is registered at T0 and the latency is
programmed to two clocks, the DQs will start driving
after T1 and the data will be valid by T2, as shown in
Figure 2. Table 2 below indicates the operating frequen-
cies at which each CAS latency setting can be used.

Reserved states should not be used as unknown op-

eration or incompatibility with future versions may re-
sult.

Figure 2

CAS Latency

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

Table 2

CAS Latency

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS

SPEED

LATENCY = 2

LATENCY = 3

-7E

133

143

-75

100

133

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SDRAM

ADVANCE

TRUTH TABLE 1 COMMANDS AND DQM OPERATION

(Note: 1)

NAME (FUNCTION)

CS# RAS# CAS# WE# DQM

ADDR

DQs

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH

6, 7

(Enter self refresh mode)

LOAD MODE REGISTER

Op-Code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

following the Operation section; these tables provide
current state/next state information.

COMMANDS

Truth Table 1 provides a quick reference of available

commands. This is followed by a written description of
each command. Three additional Truth Tables appear

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 define the op-code written to the Mode Register, and A12 should be driven LOW.
3. A0-A12 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) provide column address; A10 HIGH enables the auto precharge

feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being
read from or written to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are "Don't

Care."

6. This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

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SDRAM

ADVANCE

COMMAND INHIBIT

The COMMAND INHIBIT function prevents new com-

mands from being executed by the SDRAM, regardless of
whether the CLK signal is enabled. The SDRAM is effec-
tively deselected. Operations already in progress are not
affected.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to per-

form a NOP to an SDRAM which is selected (CS# is LOW).
This prevents unwanted commands from being regis-
tered during idle or wait states. Operations already in
progress are not affected.

LOAD MODE REGISTER

The Mode Register is loaded via inputs A0-A11 (A12

should be driven LOW.) See Mode Register heading in the
Register Definition section. The LOAD MODE REGISTER
command can only be issued when all banks are idle, and
a subsequent executable command cannot be issued
until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate) a

row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A12 selects the row. This
row remains active (or open) for accesses until a
PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening a
different row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects
the starting column location. The value on input A10
determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the READ burst; if auto precharge
is not selected, the row will remain open for subsequent
accesses. Read data appears on the DQs subject to the
logic level on the DQM inputs two clocks earlier. If a given
DQM signal was registered HIGH, the corresponding
DQs will be High-Z two clocks later; if the DQM signal was
registered LOW, the DQs will provide valid data.

WRITE

The WRITE command is used to initiate a burst write

access to an active row. The value on the BA0, BA1 inputs
selects the bank, and the address provided on inputs A0-
A9, A11, A12 (x4); A0-A9, A11 (x8); or A0-A9 (x16) selects
the starting column location. The value on input A10
determines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the WRITE burst; if auto
precharge is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs is
written to the memory array subject to the DQM input
logic level appearing coincident with the data. If a given
DQM signal is registered LOW, the corresponding data
will be written to memory; if the DQM signal is registered
HIGH, the corresponding data inputs will be ignored,
and a WRITE will not be executed to that byte/column
location.

PRECHARGE

The PRECHARGE command is used to deactivate the

open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (

RP) after the PRECHARGE command is

issued. Input A10 determines whether one or all banks
are to be precharged, and in the case where only one bank
is to be precharged, inputs BA0, BA1 select the bank.
Otherwise BA0, BA1 are treated as "Don't Care." Once a
bank has been precharged, it is in the idle state and must
be activated prior to any READ or WRITE commands
being issued to that bank.

AUTO PRECHARGE

Auto precharge is a feature which performs the same

individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accom-
plished by using A10 to enable auto precharge in con-
junction with a specific READ or WRITE command. A
PRECHARGE of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst, except in
the full-page burst mode, where auto precharge does not
apply. Auto precharge is nonpersistent in that it is either
enabled or disabled for each individual READ or WRITE
command.

Auto precharge ensures that the precharge is initiated

at the earliest valid stage within a burst. The user must
not issue another command to the same bank until the
precharge time (

RP) is completed. This is determined as

if an explicit PRECHARGE command was issued at the
earliest possible time, as described for each burst type in
the Operation section of this data sheet.

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SDRAM

ADVANCE

BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated, as
shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All active banks must be PRECHARGED prior
to issuing a AUTO REFRESH comand. The AUTO RE-
FRESH command should not be issued until the mini-
mum tRP has been met after the PRECHARGE command
as shown in the operations section.

The addressing is generated by the internal refresh

controller. This makes the address bits "Don't Care"
during an AUTO REFRESH command. The 512Mb SDRAM
requires 8,192 AUTO REFRESH cycles every 64ms (

REF),

regardless of width option. Providing a distributed AUTO
REFRESH command every 7.81µs will meet the refresh
requirement and ensure that each row is refreshed. Alter-
natively, 8,192 AUTO REFRESH commands can be issued
in a burst at the minimum cycle rate (

RC), once every

64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the SDRAM
retains data without external clocking. The SELF RE-
FRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). Once the SELF
REFRESH command is registered, all the inputs to the
SDRAM become "Don't Care" with the exception of CKE,
which must remain LOW.

Once self refresh mode is engaged, the SDRAM pro-

vides its own internal clocking, causing it to perform its
own AUTO REFRESH cycles. The SDRAM must remain in
self refresh mode for a minimum period equal to

RAS

and may remain in self refresh mode for an indefinite
period beyond that.

The procedure for exiting self refresh requires a se-

quence of commands. First, CLK must be stable (stable
clock is defined as a signal cycling within timing con-
straints specified for the clock pin) prior to CKE going
back HIGH. Once CKE is HIGH, the SDRAM must have
NOP commands issued (a minimum of two clocks) for

XSR because time is required for the completion of any

internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH

commands must be issued every 7.81µs or less as both
SELF REFRESH and AUTO REFRESH utilize the row re-
fresh counter.

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SDRAM

ADVANCE

Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be issued

to a bank within the SDRAM, a row in that bank must be
"opened." This is accomplished via the ACTIVE com-
mand, which selects both the bank and the row to be
activated (see Figure 3).

After opening a row (issuing an ACTIVE command), a

READ or WRITE command may be issued to that row,
subject to the

RCD specification.

RCD (MIN) should be

divided by the clock period and rounded up to the next
whole number to determine the earliest clock edge after
the ACTIVE command on which a READ or WRITE com-
mand can be entered. For example, a

RCD specification

of 20ns with a 125 MHz clock (8ns period) results in 2.5
clocks, rounded to 3. This is reflected in Figure 4, which
covers any case where 2 <

RCD (MIN)/

CK - 3. (The same

procedure is used to convert other specification limits
from time units to clock cycles.)

A subsequent ACTIVE command to a different row in

the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by

RC.

A subsequent ACTIVE command to another bank can

be issued while the first bank is being accessed, which
results in a reduction of total row-access overhead. The
minimum time interval between successive ACTIVE com-
mands to different banks is defined by

RRD.

Figure 4

Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK <

CLK

COMMAND

NOP

ACTIVE

READ or

WRITE

NOP

RCD

DON'T CARE

Figure 3

Activating a Specific Row In a

Specific Bank

CS#

WE#

CAS#

RAS#

CKE

CLK

A0-A12

ROW

ADDRESS

HIGH

BA0, BA1

BANK

ADDRESS

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SDRAM

ADVANCE

Upon completion of a burst, assuming no other com-

mands have been initiated, the DQs will go High-Z. A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to the start address and continue.)

Data from any READ burst may be truncated with a

subsequent READ command, and data from a fixed-length
READ burst may be immediately followed by data from a
READ command. In either case, a continuous flow of data
can be maintained. The first data element from the new
burst follows either the last element of a completed burst
or the last desired data element of a longer burst that is
being truncated. The new READ command should be
issued x cycles before the clock edge at which the last
desired data element is valid, where x equals the CAS
latency minus one. This is shown in Figure 7 for CAS

READs

READ bursts are initiated with a READ command, as

shown in Figure 5.

The starting column and bank addresses are provided

with the READ command, and auto precharge is either
enabled or disabled for that burst access. If auto precharge
is enabled, the row being accessed is precharged at the
completion of the burst. For the generic READ com-
mands used in the following illustrations, auto precharge
is disabled.

During READ bursts, the valid data-out element from

the starting column address will be available following
the CAS latency after the READ command. Each subse-
quent data-out element will be valid by the next positive
clock edge. Figure 6 shows general timing for each pos-
sible CAS latency setting.

Figure 5

READ Command

Figure 6

CAS Latency

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN
ADDRESS

A0-A9, A11, A12: x4

A0-A9, A11: x8

A0-A9: x16

A10

BA0,1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A12: x4

A11,

A12: x8

A9, A11, A12: x16

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SDRAM

ADVANCE

latencies of two and three; data element n + 3 is either the
last of a burst of four or the last desired of a longer burst.
The 512Mb SDRAM uses a pipelined architecture and
therefore does not require the 2n rule associated with a
prefetch architecture. A READ command can be initiated

Figure 7

Consecutive READ Bursts

on any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to
the same bank, as shown in Figure 8, or each subsequent
READ may be performed to a different bank.

DON'T CARE

NOTE: Each READ command may be to any bank. DQM is LOW.

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

NOP

X = 2 cycles

CAS Latency = 3

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SDRAM

ADVANCE

Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by data
from a WRITE command (subject to bus turnaround
limitations). The WRITE burst may be initiated on the
clock edge immediately following the last (or last de-
sired) data element from the READ burst, provided that I/
O contention can be avoided. In a given system design,
there may be a possibility that the device driving the
input data will go Low-Z before the SDRAM DQs go High-
Z. In this case, at least a single-cycle delay should occur
between the last read data and the WRITE command.

The DQM input is used to avoid I/O contention, as

shown in Figures 9 and 10. The DQM signal must be
asserted (HIGH) at least two clocks prior to the WRITE
command (DQM latency is two clocks for output buffers)

DON'T CARE

READ

NOP

DQM

CLK

OUT

COMMAND

ADDRESS

BANK,

COL n

WRITE

BANK,

COL b

tHZ

NOTE:

A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.

Figure 10

READ to WRITE with Extra Clock Cycle

Figure 9

READ to WRITE

READ

NOP

WRITE

NOP

CLK

DQM

OUT

COMMAND

ADDRESS

BANK,

COL n

BANK,

COL b

tHZ

tCK

NOTE:

A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.

to suppress data-out from the READ. Once the WRITE
command is registered, the DQs will go High-Z (or re-
main High-Z), regardless of the state of the DQM signal;
provided the DQM was active on the clock just prior to
the WRITE command that truncated the READ com-
mand. If not, the second WRITE will be an invalid WRITE.
For example, if DQM was LOW during T4 in Figure 10,
then the WRITEs at T5 and T7 would be valid, while the
WRITE at T6 would be invalid.

The DQM signal must be de-asserted prior to the

WRITE command (DQM latency is zero clocks for input
buffers) to ensure that the written data is not masked.
Figure 9 shows the case where the clock frequency allows
for bus contention to be avoided without adding a NOP
cycle, and Figure 10 shows the case where the additional
NOP is needed.

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SDRAM

ADVANCE

Figure 11

READ to PRECHARGE

A fixed-length READ burst may be followed by, or

truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data

element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until

RP is met. Note that part of the row

precharge time is hidden during the access of the last
data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-

DON'T CARE

CLK

OUT

COMMAND

ADDRESS

READ

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

t RP

NOTE: DQM is LOW.

CLK

OUT

COMMAND

ADDRESS

READ

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

t RP

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

BANK a,

COL n

BANK a,

ROW

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

BANK

(a or all)

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SDRAM

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Figure 12

Terminating a READ Burst

eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.

Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length READ
bursts may be truncated with a BURST TERMINATE com-
mand, provided that auto precharge was not activated.
The BURST TERMINATE command should be issued x
cycles before the clock edge at which the last desired data
element is valid, where x equals the CAS latency minus
one. This is shown in Figure 12 for each possible CAS
latency; data element n + 3 is the last desired data ele-
ment of a longer burst.

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

DON'T CARE

NOTE: DQM is LOW.

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

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SDRAM

ADVANCE

WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 13.

The starting column and bank addresses are provided

with the WRITE command, and auto precharge is either
enabled or disabled for that access. If auto precharge is
enabled, the row being accessed is precharged at the
completion of the burst. For the generic WRITE com-
mands used in the following illustrations, auto precharge
is disabled.

During WRITE bursts, the first valid data-in element

will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to the start address and continue.)

Data for any WRITE burst may be truncated with a

subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
command applies to the new command. An example is

Figure 15

WRITE to WRITE

shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 512Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
the same bank, as shown in Figure 16, or each subsequent
WRITE may be performed to a different bank.

CLK

COMMAND

ADDRESS

NOP

WRITE

n + 1

NOP

BANK,

COL n

NOTE B

t l

2 DQM i LOW

Figure 14

WRITE Burst

CLK

COMMAND

ADDRESS

NOP

WRITE

BANK,

COL n

BANK,

COL b

n + 1

NOTE:

DQM is LOW. Each WRITE
command may be to any bank.

DON'T CARE

Figure 13

WRITE Command

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN
ADDRESS

A10

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

A0-A9, A11, A12: x4

A0-A9, A11: x8

A0-A9: x16

A12: x4

A11, A12: x8

A9, A11, A12: x16

BA0, BA, 1

BANK

ADDRESS

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SDRAM

ADVANCE

registered. The auto precharge mode requires a

WR of at

least one clock plus time, regardless of frequency. In
addition, when truncating a WRITE burst, the DQM sig-
nal must be used to mask input data for the clock edge
prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure
18. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until

RP is met. The precharge can be

issued coincident with the first coincident clock edge (T2
in Figure 18) on an A1 Version and with the second clock
on an A2 Version (Figure 18.)

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the

Figure 18

WRITE To PRECHARGE

DON'T CARE

DQM

CLK

COMMAND

ADDRESS

BANK a,

COL n

NOP

WRITE

PRECHARGE

NOP

n + 1

ACTIVE

t RP

BANK

(a or all)

t WR

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOP

WRITE

PRECHARGE

NOP

n + 1

ACTIVE

t RP

BANK

(a or all)

t WR

NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.

BANK a,

ROW

NOP

tWR @ tCLK 15ns

tWR = tCLK < 15ns

Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be
executed. An example is shown in Figure 17. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst.

Data for a fixed-length WRITE burst may be followed

by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued

WR after the

clock edge at which the last desired input data element is

Figure 17

WRITE To READ

CLK

COMMAND

ADDRESS

NOP

WRITE

BANK,

COL n

n + 1

OUT

READ

NOP

BANK,

COL b

NOP

OUT

b + 1

NOTE:

The WRITE command may be to any bank, and the READ command
may be to any bank. DQM is LOW. CAS latency = 2 for illustration.

Figure 16

Random WRITE Cycles

CLK

COMMAND

ADDRESS

WRITE

BANK,

COL n

WRITE

BANK,

COL a

BANK,

COL x

BANK,
COL m

NOTE:

Each WRITE command may be to any bank.
DQM is LOW.

512Mb: x4, x8, x16 SDRAM

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512Mb: x4, x8, x16

SDRAM

ADVANCE

PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.

Fixed-length or full-page WRITE bursts can be trun-

cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coinci-
dent with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock
previous to the BURST TERMINATE command. This is

Figure 21

Power-Down

DON'T CARE

tRAS

tRCD

tRC

All banks idle

Input buffers gated off

Exit power-down mode.

(

)

(

)

(

)

(

)

(

)

(

)

tCKS

> tCKS

COMMAND

NOP

ACTIVE

Enter power-down mode.

NOP

CLK

CKE

(

)

(

)

(

)

(

)

Figure 20

PRECHARGE Command

Figure 19

Terminating a WRITE Burst

CLK

COMMAND

ADDRESS

BANK,

COL n

WRITE

BURST

TERMINATE

COMMAND

(ADDRESS)

(DATA)

NOTE: DQMs are LOW.

shown in Figure 19, where data n is the last desired data
element of a longer burst.

PRECHARGE

The PRECHARGE command (see Figure 20) is used to

deactivate the open row in a particular bank or the open
row in all banks. The bank(s) will be available for a subse-
quent row access some specified time (

RP) after the

precharge command is issued. Input A10 determines
whether one or all banks are to be precharged, and in the
case where only one bank is to be precharged, inputs
BA0, BA1 select the bank. When all banks are to be
precharged, inputs BA0, BA1 are treated as "Don't Care."
Once a bank has been precharged, it is in the idle state
and must be activated prior to any READ or WRITE com-
mands being issued to that bank.

POWER-DOWN

Power-down occurs if CKE is registered low coinci-

dent with a NOP or COMMAND INHIBIT when no ac-
cesses are in progress. If power-down occurs when all
banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a row
active in any bank, this mode is referred to as active
power-down. Entering power-down deactivates the in-
put and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not
remain in the power-down state longer than the refresh
period (64ms) since no refresh operations are performed
in this mode.

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting

CKS). (See Figure 21.)

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

HIGH

All Banks

Bank Selected

A0-A9, A11, A12

BA0, BA1

BANK

ADDRESS

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512Mb: x4, x8, x16

SDRAM

ADVANCE

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOP

CLK

CKE

INTERNAL

CLOCK

NOP

n + 1

n + 2

NOTE: For this example, burst length = 4 or greater, and DM

is LOW.

Figure 22

Clock Suspend During WRITE Burst

DON'T CARE

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

Figure 23

Clock Suspend During READ Burst

CLOCK SUSPEND

The clock suspend mode occurs when a column ac-

cess/burst is in progress and CKE is registered LOW. In
the clock suspend mode, the internal clock is deacti-
vated, "freezing" the synchronous logic.

For each positive clock edge on which CKE is sampled

LOW, the next internal positive clock edge is suspended.
Any command or data present on the input pins at the
time of a suspended internal clock edge is ignored; any
data present on the DQ pins remains driven; and burst
counters are not incremented, as long as the clock is
suspended. (See examples in Figures 22 and 23.)

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will re-
sume on the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the Mode
Register to a logic 1. In this mode, all WRITE commands
result in the access of a single column location (burst of
one), regardless of the programmed burst length. READ
commands access columns according to the programmed
burst length and sequence, just as in the normal mode of
operation (M9 = 0).

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512Mb: x4, x8, x16

SDRAM

ADVANCE

CONCURRENT AUTO PRECHARGE

An access command to (READ or WRITE) another

bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports CONCURRENT AUTO PRECHARGE.
Micron SDRAMs support CONCURRENT AUTO
PRECHARGE. Four cases where CONCURRENT AUTO
PRECHARGE occurs are defined below.

READ with auto precharge
1. Interrupted by a READ (with or without auto

precharge): A READ to bank m will interrupt a READ

on bank n, CAS latency later. The PRECHARGE to
bank n will begin when the READ to bank m is regis-
tered (Figure 24).

2. Interrupted by a WRITE (with or without auto

precharge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used two
clocks prior to the WRITE command to prevent bus
contention. The PRECHARGE to bank n will begin
when the WRITE to bank m is registered (Figure 25).

CLK

OUT

COMMAND

READ - AP

BANK n

NOP

OUT

a + 1

OUT

d + 1

NOP

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

NOTE: DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal
States

Page Active

READ with Burst of 4

Interrupt Burst, Precharge

Page Active

READ with Burst of 4

Precharge

RP - BANK n

tRP - BANK m

CAS Latency = 3 (BANK n)

Figure 24

READ With Auto Precharge Interrupted by a READ

CLK

OUT

COMMAND

NOP

d + 1

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

NOTE: 1. DQM is HIGH at T2 to prevent D

OUT

-a+1 from contending with D

-d at T4.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal
States

Page

Active

READ with Burst of 4

Interrupt Burst, Precharge

Page Active

WRITE with Burst of 4

Write-Back

RP - BANK n

t WR - BANK m

CAS Latency = 3 (BANK n)

READ - AP

BANK n

DON'T CARE

Figure 25

READ With Auto Precharge Interrupted by a WRITE

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512Mb: x4, x8, x16

SDRAM

ADVANCE

CLK

COMMAND

WRITE - AP

BANK n

NOP

a + 1

NOP

BANK n

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal
States

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active

READ with Burst of 4

tRP - BANK m

OUT

d + 1

CAS Latency = 3 (BANK m)

RP - BANK n

WR - BANK n

Figure 26

WRITE With Auto Precharge Interrupted by a READ

DON'T CARE

CLK

COMMAND

WRITE - AP

BANK n

NOP

d + 1

a + 1

a + 2

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal
States

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active

WRITE with Burst of 4

Write-Back

WR - BANK n

tRP - BANK n

t WR - BANK m

Figure 27

WRITE With Auto Precharge Interrupted by a WRITE

WRITE with auto precharge
3. Interrupted by a READ (with or without AUTO

PRECHARGE): A READ to bank m will interrupt a
WRITE on bank n when registered, with the data-out
appearing CAS latency later. The PRECHARGE to bank
n will begin after

WR is met, where

WR begins when

the READ to bank m is registered. The last valid WRITE
to bank n will be data-in registered one clock prior to
the READ to bank m (Figure 26).

4. Interrupted by a WRITE (with or without auto

precharge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The PRECHARGE to bank
n will begin after

WR is met, where

WR begins when

the WRITE to bank m is registered. The last valid data
WRITE to bank n will be data registered one clock
prior to a WRITE to bank m (Figure 27).

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512Mb: x4, x8, x16

SDRAM

ADVANCE

TRUTH TABLE 2 CKE

(Notes: 1-4)

CKE

n-1

CKE

CURRENT STATE

COMMAND

ACTION

NOTES

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Clock Suspend

Maintain Clock Suspend

Power-Down

COMMAND INHIBIT or NOP

Exit Power-Down

Self Refresh

COMMAND INHIBIT or NOP

Exit Self Refresh

Clock Suspend

Exit Clock Suspend

All Banks Idle

COMMAND INHIBIT or NOP

Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

Reading or Writing

VALID

Clock Suspend Entry

See Truth Table 3 (page 28)

NOTE: 1. CKE

is the logic state of CKE at clock edge n; CKE

n-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.

3. COMMAND

is the command registered at clock edge n, and ACTION

is a result of COMMAND

4. All states and sequences not shown are illegal or reserved.

5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1

(provided that

CKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once

XSR is met. COMMAND INHIBIT

or NOP commands should be issued on any clock edges occurring during the

XSR period. A minimum of two NOP

commands must be provided during

XSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at

clock edge n + 1.

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512Mb: x4, x8, x16

SDRAM

ADVANCE

TRUTH TABLE 3 CURRENT STATE BANK n - COMMAND TO BANK n

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE#

COMMAND (ACTION)

NOTES

Any

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

ACTIVE (Select and activate row)

Idle

AUTO REFRESH

LOAD MODE REGISTER

PRECHARGE

READ (Select column and start READ burst)

Row Active

WRITE (Select column and start WRITE burst)

PRECHARGE (Deactivate row in bank or banks)

Read

READ (Select column and start new READ burst)

(Auto

WRITE (Select column and start WRITE burst)

Precharge

PRECHARGE (Truncate READ burst, start PRECHARGE)

Disabled)

BURST TERMINATE

Write

READ (Select column and start READ burst)

(Auto

WRITE (Select column and start new WRITE burst)

Precharge

PRECHARGE (Truncate WRITE burst, start PRECHARGE)

Disabled)

BURST TERMINATE

NOTE: 1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSR has been

met (if the previous state was self refresh).

2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown

are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP

commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according to
Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once

RP is met, the

bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when

RCD is met. Once

RCD is met, the

bank will be in the row active state.

Read w/Auto

Precharge

Enabled: Starts with registration of a READ command with auto precharge enabled and ends when

RP has

been met. Once

RP is met, the bank will be in the idle state.

Write w/Auto

Precharge

Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when

RP has

been met. Once

RP is met, the bank will be in the idle state.

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512Mb: x4, x8, x16

SDRAM

ADVANCE

NOTE (continued):

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands

must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

RC is met. Once

RC is met,

the SDRAM will be in the all banks idle state.

Accessing Mode

MRD has been met.

Once

MRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

RP is met. Once

RP is met,

all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

7. Not bank-specific; requires that all banks are idle.

8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.

9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.

10. READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

11. Does not affect the state of the bank and acts as a NOP to that bank.

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512Mb: x4, x8, x16

SDRAM

ADVANCE

TRUTH TABLE 4 CURRENT STATE BANK n - COMMAND TO BANK m

(Notes: 1-6; notes appear below and on next page)

CURRENT STATE CS# RAS# CAS# WE#

COMMAND (ACTION)

NOTES

Any

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Idle

Any Command Otherwise Allowed to Bank m

Row

ACTIVE (Select and activate row)

Activating,

READ (Select column and start READ burst)

Active, or

WRITE (Select column and start WRITE burst)

Precharging

PRECHARGE

Read

ACTIVE (Select and activate row)

(Auto

READ (Select column and start new READ burst)

7, 10

Precharge

WRITE (Select column and start WRITE burst)

7, 11

Disabled)

PRECHARGE

Write

ACTIVE (Select and activate row)

(Auto

READ (Select column and start READ burst)

7, 12

Precharge

WRITE (Select column and start new WRITE burst)

7, 13

Disabled)

PRECHARGE

Read

ACTIVE (Select and activate row)

(With Auto

READ (Select column and start new READ burst)

7, 8, 14

Precharge)

WRITE (Select column and start WRITE burst)

7, 8, 15

PRECHARGE

Write

ACTIVE (Select and activate row)

(With Auto

READ (Select column and start READ burst)

7, 8, 16

Precharge)

WRITE (Select column and start new WRITE burst)

7, 8, 17

PRECHARGE

NOTE: 1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after

XSR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the

commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given
command is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been

terminated.

Read w/Auto

Precharge

Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when

RP has

been met. Once

RP is met, the bank will be in the idle state.

Write w/Auto

Precharge

Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when

RP has

been met. Once

RP is met, the bank will be in the idle state.

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512Mb: x4, x8, x16

SDRAM

ADVANCE

NOTE (continued):

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.

5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current

state only.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been

interrupted by bank m's burst.

9. Burst in bank n continues as initiated.

10. For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m

will interrupt the READ on bank n, CAS latency later (Figure 7).

11. For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

will interrupt the READ on bank n when registered (Figures 9 and 10). DQM should be used one clock prior to the
WRITE command to prevent bus contention.

12. For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m

will interrupt the WRITE on bank n when registered (Figure 17), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13. For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

will interrupt the WRITE on bank n when registered (Figure 15). The last valid WRITE to bank n will be data-in
registered one clock prior to the READ to bank m.

14. For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 24).

15. For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to
prevent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 25).

16. For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to
bank n will begin after

WR is met, where

WR begins when the READ to bank m is registered. The last valid WRITE to

bank n will be data-in registered one clock prior to the READ to bank m (Figure 26).

17. For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after

WR is met, where

begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock prior
to the WRITE to bank m (Figure 27).

512Mb: x4, x8, x16 SDRAM

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512Mb: x4, x8, x16

SDRAM

ADVANCE

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes appear on page 35) (V

, V

Q = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

Supply Voltage

, V

3.6

Input High Voltage: Logic 1; All inputs

+ 0.3

Input Low Voltage: Logic 0; All inputs

-0.3

0.8

Input Leakage Current:
Any input 0V

-5

µA

(All other pins not under test = 0V)

Output Leakage Current: DQs are disabled;

-5

µA

OUT

Output Levels:

2.4

Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

0.4

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

, V

Q Supply

Relative to V

....................................... -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to V

....................................... -1V to +4.6V

Operating Temperature,

(Commercial) ................................... 0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 1W

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

MAX

SPECIFICATIONS AND CONDITIONS

(Notes: 1, 5, 6, 11, 13; notes appear on page 35) (V

, V

Q = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

-7E

-75

UNITS NOTES

Operating Current: Active Mode;

TBD

3, 18,

Burst = 1; READ or WRITE;

RC =

RC (MIN)

19, 29

Standby Current: Power-Down Mode;

TBD

CKE = LOW; All banks idle

Standby Current: Active Mode; CS# = HIGH;

TBD

3, 12,

CKE = HIGH; All banks active after

RCD met;

19, 29

No accesses in progress

Operating Current: Burst Mode; Continuous burst;

TBD

3, 18,

READ or WRITE; All banks active

19, 29

Auto Refresh Current:

RFC =

RFC (MIN)

TBD

3, 12,

CS# = HIGH; CKE = HIGH

18, 19,

RFC = 7.81µs

TBD

29,30

Self Refresh Current: CKE

0.2V

Standard

TBD

Low power (L)

TBD

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512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

CAPACITANCE

(Note: 2; notes appear on page 35)

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: CLK

2.5

3.5

Input Capacitance: All other input-only pins

2.5

3.8

Input/Output Capacitance: DQs

4.0

6.0

AC CHARACTERISTICS

-7E

-75

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from CLK (pos. edge)

CL = 3

AC(3)

5.4

CL = 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL = 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

2.7

Data-out hold time (no load)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period (8,192 rows)

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK +

7ns

7.5ns

Exit SELF REFRESH to ACTIVE command

XSR

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

(Notes: 5, 6, 8, 9, 11; notes appear on page 35)

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

AC FUNCTIONAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 11; notes appear on page 35)

PARAMETER

SYMBOL

-7E

-75

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE command

CL = 3

ROH(3)

CL = 2

ROH(2)

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

13. I

specifications are tested after the device is

properly initialized.

14. Timing actually specified by

CKS; clock(s)

specified as a reference only at minimum cycle
rate.

15. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC functional-

ity and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease in a

proportional amount by the amount the frequency
is altered for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 7.5ns for -75 and -7E.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

3ns, and the pulse width cannot be greater

than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for a pulse width

3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7.5ns/7ns after the first clock

delay, after the last WRITE is executed.

25. Precharge mode only.
26. JEDEC and PC100, PC133 specify three clocks.
27.

AC for -75/-7E at CL = 3 with no load is 4.6ns and is

guaranteed by design.

28. Parameter guaranteed by design.
29. For -75, CL = 3,

CK = 7.5ns; For -7E, CL = 2,

CK = 7.5ns

30. CKE is HIGH during refresh command period

RFC(MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

NOTES
1.

All voltages referenced to V

This parameter is sampled. V

, V

Q = +3.3V;

f = 1 MHz, T

= 25°C; pin under test biased at 1.4V.

is dependent on output loading and cycle

rates. Specified values are obtained with minimum
cycle time and the outputs open.

Enables on-chip refresh and address counters.

The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C

70°C) is

ensured.

An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously. V

and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be
repeated any time the

REF refresh requirement is

exceeded.

AC characteristics assume

T = 1ns.

In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between V

and V

(or between V

and V

) in a monotonic

manner.

Outputs measured at 1.5V with equivalent load:

50pF

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V,

with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V

(MAX) and V

(MIN)

and no longer at the 1.5V crossover point.

12. Other input signals are allowed to transition no

more than once every two clocks and are otherwise
at valid V

or V

levels.

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

INITIALIZE AND LOAD MODE REGISTER

*CAS latency indicated in parentheses.

NOTE: 1. The Mode Register may be loaded prior to the AUTO REFRESH cycles if desired.

2. If CS is HIGH at clock high time, all commands applied are NOP, with CKE a "Don't Care."
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
5. A12 should be a LOW at

P + 1.

CKS

1.5

CMH

0.8

CMS

1.5

MRD

RFC

tCH

tCL

tCK

CKE

COMMAND

BA0, BA1

BANK

tRFC

tMRD

tRFC

AUTO REFRESH

Program Mode Register

1, 3, 4

tCMH

tCMS

Precharge
all banks

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tRP

(

)

(

)

(

)

(

)

tCKS

Power-up:
V

and

CLK stable

T = 100µs

MIN

PRECHARGE

NOP

AUTO

REFRESH

NOP

LOAD MODE

ACTIVE

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

AUTO

REFRESH

ALL

BANKS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

High-Z

tCKH

(

)

(

)

(

)

(

)

DQM/

DQML, DQMH

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

NOP

(

)

(

)

(

)

(

)

tCMH

tCMS

tCMH

tCMS

A0-A9, A11, A12

ROW

tAH

tAS

CODE

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

A10

ROW

tAH

tAS

CODE

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

DON'T CARE

UNDEFINED

Tn + 1

To + 1

Tp + 1

Tp + 2

Tp + 3

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

NOTE: 1. Violating refresh requirements during power-down may result in a loss of data.

POWER-DOWN MODE

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter
power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

(

)

(

)

(

)

(

)

DON'T CARE

tCKS

COMMAND

tCMH

tCMS

PRECHARGE

NOP

ACTIVE

NOP

(

)

(

)

(

)

(

)

All banks idle

BA0, BA1

BANK

BANK(S)

(

)

(

)

(

)

(

)

High-Z

tAH

tAS

tCKH

tCKS

DQM/

DQML, DQMH

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

A0-A9, A11, A12

ROW

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

A10

ROW

(

)

(

)

(

)

(

)

Tn + 1

Tn + 2

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

CMS

1.5

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CLOCK SUSPEND MODE

tCH

tCL

tCK

tAC

tLZ

DQM/

DQML, DQMH

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

OUT

tAC

tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOP

READ

WRITE

DON'T CARE

CKE

tCKS tCKH

BANK

COLUMN m

tDS

OUT

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e2

NOTE: 1. For this example, the burst length = 2, the CAS latency = 3, and AUTO PRECHARGE is disabled.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKS

1.5

CMH

0.8

CMS

1.5

0.8

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

AUTO REFRESH MODE

tCH

tCL

tCK

CKE

CLK

tRFC

RFC

(

)

(

)

(

)

(

)

(

)

(

)

tRP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

COMMAND

tCMH

tCMS

NOP

(

)

(

)

(

)

(

)

BANK

ACTIVE

AUTO

REFRESH

(

)

(

)

(

)

(

)

NOP

PRECHARGE

Precharge all

active banks

AUTO

REFRESH

High-Z

BA0, BA1

BANK(S)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tAH

tAS

tCKH

tCKS

(

)

(

)

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

DQM /

DQML, DQMH

A0-A9, A11, A12

ROW

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

A10

ROW

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

DON'T CARE

Tn + 1

To + 1

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKH

0.8

CKS

1.5

CMH

0.8

CMS

1.5

RFC

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

SELF REFRESH MODE

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

DON'T CARE

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE

NOP

or COMMAND

INHIBIT

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

BA0, BA1

BANK(S)

(

)

(

)

(

)

(

)

High-Z

tCKS

AUTO

REFRESH

tRAS(MIN)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tCKH

tCKS

DQM/

DQML, DQMH

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

A0-A9, A11,A12

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

A10

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Tn + 1

To + 1

To + 2

(

)

(

)

(

)

(

)

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKS

1.5

CMH

0.8

CMS

1.5

RAS

120,000

XSR

NOTES: 1. No maximum time limit for Self Refresh.

RAS(MAX) applies to non-Self Refresh mode.

XSR requires minimum of two clocks regardless of frequency or timing.

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

READ WITHOUT AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD

CAS Latency

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

ROW

BANK

tHZ

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2

OUT

m + 1

COMMAND

tCMH

tCMS

PRECHARGE

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

DISABLE AUTO PRECHARGE

SINGLE BANK

DON'T CARE

UNDEFINED

tCKH

tCKS

COLUMN m 2

NOTE: 1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual"

PRECHARGE.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMH

0.8

CMS

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

RAS

120,000

RCD

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

READ WITH AUTO PRECHARGE

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD

CAS Latency

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

ROW

BANK

DON'T CARE

UNDEFINED

tHZ

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2

OUT

m + 1

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

NOP

tCKH

tCKS

COLUMN m 2

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMH

0.8

CMS

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

RAS

120,000

RCD

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

SINGLE READ WITHOUT AUTO PRECHARGE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

CMS

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

RAS

120,000

RCD

*CAS latency indicated in parentheses.

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD

CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

BANK(S)

BANK

ROW

BANK

tHZ

tCMH

tCMS

NOP

PRECHARGE

ACTIVE

NOP

READ

ACTIVE

NOP

DISABLE AUTO PRECHARGE

SINGLE BANKS

DON'T CARE

UNDEFINED

COLUMN m

tCKH

tCKS

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

COMMAND

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a "manual"

PRECHARGE.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

NOTE: 1. For this example, the burst length = 1, and the CAS latency = 2.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

3. READ command not allowed else

RAS would be violated

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMH

0.8

CMS

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

RAS

120,000

RCD

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

SINGLE READ WITH AUTO PRECHARGE

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

CAS Latency

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

ROW

BANK

DON'T CARE

UNDEFINED

tHZ

t OH

OUT

tAC

COMMAND

tCMH

tCMS

NOP3

READ

ACTIVE

NOP

NOP3

ACTIVE

NOP

tCKH

tCKS

COLUMN m2

NOP

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

ALTERNATING BANK READ ACCESSES

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

DQM/

DQML, DQMH

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

DON'T CARE

UNDEFINED

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2

OUT

m + 1

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

tOH

OUT

tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0

BANK 3

BANK 0

CKE

tCKH

tCKS

COLUMN m 2

COLUMN b 2

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 1

CAS Latency - BANK 1

RC - BANK 0

RRD

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMH

0.8

CMS

1.5

2.7

RAS

120,000

RCD

RRD

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

READ FULL-PAGE BURST

NOTE: 1. For this example, the CAS latency = 2.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

3. Page left open; no

RP.

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKS

1.5

CMH

0.8

CMS

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

RCD

tCH

tCL

tCK

tAC

tLZ

tRCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC

tOH

OUT

m+1

ROW

tHZ

tAC

tOH

OUT

m+1

tAC

tOH

OUT

m+2

tAC

tOH

OUT

m-1

tAC

tOH

Dout m

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Full page completed

1,024 (x16) locations within same row
2,048 (x8) locations within same row
4,096 (x4) locations within same row

DON'T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

READ

NOP

BURST TERM

NOP

(

)

(

)

(

)

(

)

NOP

(

)

(

)

(

)

(

)

tAH

tAS

BANK

(

)

(

)

(

)

(

)

BANK

tCKH

tCKS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

COLUMN m 2

Tn + 1

Tn + 2

Tn + 3

Tn + 4

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

AC (3)

5.4

AC (2)

5.4

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

READ DQM OPERATION

tCH

tCL

tCK

tRCD

CAS Latency

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

DON'T CARE

UNDEFINED

tAC

OUT

tOH

OUT

m + 3

OUT

m + 2

tHZ

tCMH

COMMAND

NOP

ACTIVE

NOP

READ

NOP

tHZ

tAC

tOH

tAC

tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m 2

NOTE: 1. For this example, the burst length = 4, and the CAS latency = 2.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKS

1.5

CMH

0.8

CMS

1.5

HZ (3)

5.4

HZ (2)

5.4

2.7

RCD

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

WRITE WITHOUT AUTO PRECHARGE

DISABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

DON'T CARE

tDH

tDS

m + 1

m + 2

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

PRECHARGE

tAH

tAS

tAH

tAS

tDH

tDS

tDH

tDS

tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m3

ROW

BANK

ROW

ACTIVE

NOP

ALL BANKs

NOTE: 1. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE.

2. 14ns to 15ns is required between <D

m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMS

1.5

0.8

1.5

RAS

120,000

RCD

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

WRITE WITH AUTO PRECHARGE

NOTE: 1. For this example, the burst length = 4.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMS

1.5

0.8

1.5

RAS

120,000

RCD

1 CLK +

7ns

7.5ns

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

tWR

DON'T CARE

tDH

tDS

m + 1

m + 2

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tDH

tDS

tDH

tDS

tCKH

tCKS

NOP

COLUMN

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

SINGLE WRITE WITHOUT AUTO PRECHARGE

CMS

1.5

0.8

1.5

RAS

120,000

RCD

*CAS latency indicated in parentheses.

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

BANK

ROW

BANK

t WR

tDH

tDS

COMMAND

tCMH

tCMS

NOP4

PRECHARGE

ACTIVE

NOP

WRITE

ACTIVE

NOP

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m 3

DON'T CARE

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE.

2. 14ns to 15ns is required between <D

m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

4. PRECHARGE command not allowed else

RAS would be violated

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

SINGLE WRITE WITH AUTO PRECHARGE

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

NOTE: 1. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE.

2. 14ns to 15ns is required between <D

m> and the PRECHARGE command, regardless of frequency.

3. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

4. WRITE command not allowed else

RAS would be violated

*CAS latency indicated in parentheses.

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD3

tRC

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

tWR

COMMAND

tCMH

tCMS

NOP4

NOP

ACTIVE

NOP4

WRITE

NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tCKH

tCKS

NOP

COLUMN m

DON'T CARE

CMS

1.5

0.8

1.5

RAS

120,000

RCD

1 CLK +

7ns

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

CKS

1.5

CMH

0.8

ALTERNATING BANK WRITE ACCESSES

tCH

tCL

tCK

CLK

DON'T CARE

tDH

tDS

m + 1

m + 2

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

tDH

tDS

tDH

tDS

tDH

tDS

ACTIVE

WRITE

tDH

tDS

b + 1

b + 3

tDH

tDS

tDH

tDS

ENABLE AUTO PRECHARGE

DQM/

DQML, DQMH

A0-A9, A11, A12

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0

BANK 1

BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b 3

COLUMN m 3

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

RC - BANK 0

RRD

NOTE: 1. For this example, the burst length = 4.

2. Requires one clock plus time (7ns to 7.5ns) with auto precharge or 14ns to 15ns with PRECHARGE.
3. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CMS

1.5

0.8

1.5

RAS

120,000

RCD

RRD

Note 2

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

WRITE FULL-PAGE BURST

NOTE: 1. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

WR must be satisfied prior to PRECHARGE command.

3. Page left open; no

RP.

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKS

1.5

CMH

0.8

CMS

1.5

0.8

1.5

RCD

tCH

tCL

tCK

tRCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does
not self-terminate.
Can use BURST TERMINATE
command to stop.

2, 3

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Full page completed

DON'T CARE

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

BURST TERM

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tDH

tDS

m + 1

m + 2

m + 3

tDH

tDS

tDH

tDS

tDH

tDS

m - 1

tDH

tDS

tAH

tAS

BANK

(

)

(

)

(

)

(

)

BANK

tCMH

tCKH

tCKS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

1,024 (x16) locations within same row

2,048 (x8) locations within same row
4,096 (x4) locations within same row

COLUMN

Tn + 1

Tn + 2

Tn + 3

512Mb: x4, x8, x16 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

512MSDRAM_D.p65 Rev. D; Pub 1/02

512Mb: x4, x8, x16

SDRAM

ADVANCE

TIMING PARAMETERS

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

0.8

1.5

2.5

CK (3)

7.5

CK (2)

7.5

CKH

0.8

WRITE DQM OPERATION

tCH

tCL

tCK

tRCD

DQM/

DQML, DQMH

CKE

CLK

A0-A9, A11, A12

BA0, BA1

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

m + 3

tDH

tDS

m + 2

tCMH

COMMAND

NOP

ACTIVE

NOP

WRITE

NOP

DON'T CARE

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m 2

NOTE: 1. For this example, the burst length = 4.

2. x16: A11 and A12 = "Don't Care"

x8: A12 = "Don't Care"

*CAS latency indicated in parentheses.

-7E

-75

SYMBOL*

MIN

MAX

MIN

MAX

UNITS

CKS

1.5

CMH

0.8

CMS

1.5

0.8

1.5

RCD

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Document Outline

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