09005aef808ebf65
128Mbx16x32.fm - Rev. G 3/03 EN

128Mb: x16, x32

MOBILE SDRAM

SYNCHRONOUS
DRAM

MT48LC8M16LFFF, MT48V8M16LFFF - 2 MEG X 16 X 4 BANKS
MT48LC4M32LFFC, MT48V4M32LFFC - 1 MEG X 32 X 4
BANKS

For the latest data sheet, please refer to the Micron Web
site:

www.micron.com/dramds

FEATURES

· Temperature Compensated Self Refresh (TCSR)
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge, includes CONCURRENT auto

precharge, and Auto Refresh Modes

· Self Refresh Mode; standard and low power
· 64ms, 4,096-cycle refresh
· LVTTL-compatible inputs and outputs
· Low voltage power supply
· Partial Array Self Refresh power-saving mode

Part Number Example:

MT48V8M16LFFF-8

*CL = CAS (READ) latency

OPTIONS

MARKING

· V

3.3V/3.3V

2.5V/2.5V or 1.8V

· Configurations

8 Meg x 16 (2 Meg x 16 x 4 banks)

8M16

4 Meg x 32 (1 Meg x 32 x 4 banks)

4M32

· Package/Ball out

54-ball FBGA (8mm x 9mm )

NOTE:

1. x16 Only.

54-ball FBGA (8mm x 9mm )

Lead-Free

90-ball FBGA (11mm x 13mm)

2. x32 Only.

90-ball FBGA (11mm x 13mm)

Lead-Free

· Timing (Cycle Time)

8ns @ CL = 3 (125 MHz)

-8

10ns @ CL = 3 (100 MHz)

-10

· Temperature

Commercial (0°C to +70°C)

None

Industrial (-40°C to +85°C)

8 Meg x 16

4 Meg x 32

Configuration

2 Meg x 16 x 4 banks 1 Meg x 32 x 4 banks

Refresh Count

Row Addressing

4K (A0A11)

Bank Addressing

4 (BA0, BA1)

Column Addressing

512 (A0A8)

256 (A0A7)

KEY TIMING PARAMETERS

SPEED

GRADE

CLOCK

FREQUENCY

ACCESS TIME

RCD

CL=1*

CL=2*

CL=3*

-8

125 MHz

6ns

20ns

-10

100 MHz

6ns

20ns

-8

100 MHz

7ns

20ns

-10

83 MHz

7ns

20ns

-8

50 MHz

18ns

20ns

-10

40 MHz

18ns

20ns

1 2 3 4 5 6 7 8

Top View

(Ball Down)

DQ14

DQ12

DQ10

DQ8

UDQM

NC/A12

DQ15

DQ13

DQ11

DQ9

CLK

A11

CKE

CAS#

BA0

DQ0

DQ2

DQ4

DQ6

LDQM

RAS#

BA1

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A10

Figure 1: PIN ASSIGNMENT (Top View)

54-Ball FBGA

128Mb: x16, x32

MOBILE SDRAM

09005aef808ebf65

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

General Description

The Micron® 128Mb SDRAM is a high-speed

CMOS, dynamic random-access memory containing
134,217,728 bits. It is internally configured as a quad-
bank DRAM with a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). Each of the x16's 33,554,432-bit banks is orga-
nized as 4,096 rows by 512 columns by 16 bits. Each of
the x32's 33,554,432-bit banks is organized as 4,096
rows by 256 columns by 32 bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0, BA1 select the bank; A0-A11(x16) or A0-A10(x32)
select the row). The address bits registered coincident
with the READ or WRITE command are used to select
the starting column location for the burst access.

The SDRAM provides for programmable read or

write burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge

function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.

The 128Mb SDRAM uses an internal pipelined

architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one bank
while accessing one of the other three banks will hide
the precharge cycles and provide seamless high-speed,
random-access operation.

The 128Mb SDRAM is designed to operate in 3.3V or

2.5V low-power memory systems. An auto refresh
mode is provided, along with a power-saving, power-
down mode. All inputs and outputs are LVTTL-com-
patible.

SDRAMs offer substantial advances in DRAM oper-

ating performance, including the ability to synchro-
nously burst data at a high data rate with automatic
column-address generation, the ability to interleave
between internal banks in order to hide precharge
time and the capability to randomly change column
addresses on each clock cycle during a burst access.

Table 1:

128Mb SDRAM Part Numbers

PART NUMBER

ARCHITECTURE

PACKAGE

MT48LC8M16LFFF-xx

3.3V / 3.3V

8 Meg x 16

54-BALL FBGA

MT48V8M16LFFF-xx

2.5V / 2.5V - 1.8V

8 Meg x 16

54-BALL FBGA

MT48LC4M32LFFC-xx

3.3V / 3.3V

4 Meg x 32

90-BALL FBGA

MT48V4M32LFFC-xx

2.5V / 2.5V - 1.8V

4 Meg x 32

90-BALL FBGA

128Mb: x16, x32

MOBILE SDRAM

09005aef808ebf65

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

Table 2:

Ball Descriptions: 54-Ball FBGA

54-BALL FBGA

SYMBOL

TYPE

DESCRIPTION

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.

CKE

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.
Deactivating the clock provides PRECHARGE POWER-DOWN and SELF
REFRESH operation (all banks idle), ACTIVE POWER-DOWN (row active in
any bank) or CLOCK SUSPEND operation (burst/access in progress). CKE is
synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CLK, are disabled during power-down
and self refresh modes, providing low standby power. CKE may be tied
HIGH.

CS#

Input

Chip Select: CS# enables (registered LOW) and disables (registered HIGH)
the command decoder. All commands are masked when CS# is registered
HIGH. CS# provides for external bank selection on systems with multiple
banks. CS# is considered part of the command code.

F7, F8, F9

CAS#, RAS#,

WE#

Input

Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the
command being entered.

E8, F1

LDQM,
UDQM

Input

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. LDQM corresponds to
DQ0DQ7, UDQM corresponds to DQ8DQ15. LDQM and UDQM are
considered same state when referenced as DQM.

G7, G8

BA0, BA1

Input

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command

H7, H8, J8, J7, J3, J2, H3,

H2, H1, G3, H9, G2

A0A11

Input

Address Inputs: A0A11 are sampled during the ACTIVE command (row-
address A0A11) and READ/WRITE command (column-address A0A8;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.

A8, B9, B8, C9, C8, D9,
D8, E9, E1, D2, D1, C2,

C1, B2, B1, A2

DQ0DQ15

I/O

Data Input/Output: Data bus

E2, G1

No Connect: These pins should be left unconnected.
G1 is a no connect for this part but may be used as A12 in future designs.

A7, B3, C7, D3

Supply DQ Power: Isolated DQ power on the die to improve noise immunity.

A3, B7, C3, D7,

Supply DQ Ground: Isolated DQ power on the die to improve noise immunity.

A9, E7, J9

Supply Power Supply: Voltage dependant on option.

A1, E3, J1

Supply Ground.

128Mb: x16, x32

MOBILE SDRAM

09005aef808ebf65

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

Table 3:

Ball Descriptions: 90-Ball FBGA

90-BALL FBGA

SYMBOL

TYPE

DESCRIPTION

CLK

Input

Clock: CLK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CLK. CLK also increments the internal
burst counter and controls the output registers.

CKE

Input

CS#

Input

J9, K7, K8

RAS#, CAS#,

WE#

Input

Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the
command being entered.

K9, K1, F8, F2

DQM03

Input

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for
write accesses and an output enable signal for read accesses. Input data is
masked during a WRITE cycle. The output buffers are placed in a High-Z
state (two-clock latency) when during a READ cycle. DQM0 corresponds to
DQ0DQ7, DQM1 corresponds to DQ8DQ15, DQM2 corresponds to
DQ16DQ23 and DQM3 corresponds to DQ24DQ31. DQM0-3 are
considered same state when referenced as DQM.

J7, H8

BA0, BA1

Input

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE,
READ, WRITE or PRECHARGE command is being applied. These pins also
provide the op-code during a LOAD MODE REGISTER command

G8, G9, F7, F3, G1, G2,

G3, H1, H2, J3, G7, H9

A0A11

Input

Address Inputs: A0A11 are sampled during the ACTIVE command (row-
address A0A11) and READ/WRITE command (column-address A0A7;
with A10 defining auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine if all banks are to be precharged
(A10 HIGH) or bank selected by BA0, BA1 (LOW). The address inputs also
provide the op-code during a LOAD MODE REGISTER command.

R8, N7, R9, N8, P9, M8,

M7, L8, L2, M3, M2, P1,

N2, R1, N3, R2, E8, D7,
D8, B9, C8, A9, C7, A8,
A2, C3, A1, C2, B1, D2,

D3, E2

DQ0DQ31

I/O

Data Input/Output: Data bus

E3, E7, H3, H7, K2, K3

No Connect: These pins should be left unconnected. H7 is a no connect for
this part but may be used as A12 in future designs.

B2, B7, C9, D9, E1,

L1, M9, N9, P2, P7

Supply DQ Power: Isolated DQ power on the die to improve noise immunity.

B8, B3, C1, D1, E9,

L9, M1, N1, P3, P8

Supply DQ Ground: Isolated DQ power on the die to improve noise immunity.

A7, F9, L7, R7

Supply Power Supply: Voltage dependant on option.

A3, F1, L3, R3

Supply Ground.

128Mb: x16, x32

MOBILE SDRAM

09005aef808ebf65

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

Functional Description

In general, the 128Mb SDRAMs (2 Meg x16 x 4 banks

and 1 Meg x 32 x 4 banks) are quad-bank DRAMs that
operate at 3.3V or 2.5V and include a synchronous
interface (all signals are registered on the positive edge
of the clock signal, CLK). Each of the x16's 33,554,432-
bit banks is organized as 4,096 rows by 512 columns by
16 bits. Each of the x32's 33,554,432-bit banks is orga-
nized as 4,096 rows by 256 columns by 32bits.

Read and write accesses to the SDRAM are burst ori-

ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed
(BA0 and BA1 select the bank, A0-A11 select the row).
The address bits ( x16: A0-A8; x32: A0-A7; ) registered
coincident with the READ or WRITE command are
used to select the starting column location for the
burst access.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, command descriptions and device opera-
tion.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to Vdd and VddQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, Command Inhibit or NOP com-
mands should be applied.

Once the 100µs delay has been satisfied with at least

one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All banks must then be precharged, thereby placing
the device in the all banks idle state.

Once in the idle state, two AUTO refresh cycles must

be performed. After the AUTO refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.

Mode Register

In order to achieve low power consumption, there

are two mode registers in the Mobile component,
Mode Register and Extended Mode Register. For this
section, Mode Register is referred to. Extended Mode
register is discussed on

. The mode register is used

to define the specific mode of operation of the
SDRAM. This definition includes the selection of a
burst length, a burst type, a CAS latency, an operating
mode and a write burst mode, as shown in Figure 5.
The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.

Mode Register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9, M10, and M11 should
be set to zero. M12 and M13 should be set to zero to
prevent extended mode register.

The mode register must be loaded when all banks

are idle, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 5. The burst length determines the
maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 1, 2, 4, or 8 locations are available for both
the sequential and the interleaved burst types, and a
full-page burst is available for the sequential type. The
full-page burst is used in conjunction with the BURST
TERMINATE command to generate arbitrary burst
lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1-A8 (x16) or A1-A7 (x32) when the burst
length is set to two; by A2-A8 (x16) or A2-A7 (x32)
when the burst length is set to four; and by A3-A8 (x16)

128Mb: x16, x32

MOBILE SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

or A3-A7 (x32) when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block.
Full-page bursts wrap within the page if the boundary
is reached.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 1.

Figure 5: Mode Register Definition

NOTE:

1. For full-page accesses: y = 512 (x16), y = 256 (x32).
2. For a burst length of two, A1-A8 (x16) or A1-A7 (x32)

select the block-of-two burst; A0 selects the starting col-
umn within the block.

3. For a burst length of four, A2-A8 (x16) or A2-A7 (x32)

select the block-of-four burst; A0-A1 select the starting
column within the block.

4. For a burst length of eight, A3-A8 (x16) or A3-A7 (x32)

select the block-of-eight burst; A0-A2 select the starting
column within the block.

5. For a full-page burst, the full row is selected and A0-A8

(x16) or A0-A7 (x32) select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

7. For a burst length of one, A0-A8 (x16) or A0-A7 (x32)

select the unique column to be accessed, and mode reg-
ister bit M3 is ignored.

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency

A7 A6

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M10 = "0, 0"

to ensure compatibility

with future devices.

BA0

BA1

M7 M6 M5 M4

M2 M1 M0

M10

A11

M11

M12

M13

LMR

Load Mode Register

Program Mode Register

All other states reserved

M13

M12

Table 4:

Burst Definition

BURST

LENGTH

ORDER OF ACCESSES WITHIN

A BURST

STARTING

COLUMN

ADDRESS

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page (y)

n = A0-A11/

9/8

(location

0-y)

Cn, Cn + 1,

Cn + 2

Cn + 3, Cn + 4...

...Cn - 1,

Cn...

Not Supported

128Mb: x16, x32

MOBILE SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to one, two, or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a read command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 6. Table 5 indi-
cates the operating frequencies at which each CAS
latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 6: CAS Latency

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 1

OUT

tOH

COMMAND

NOP

READ

tAC

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

128Mb: x16, x32

MOBILE SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
read and write bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with
future versions may result.

Figure 7: Extended Mode Register

Table

NOTE:

1. E13 and E12 (BA1 and BA0) must be "1, 0" to

select the Extended Mode Register (vs. the base
Mode Register).

2. RFU: Reserved for Future Use.

Extended Mode Register

The Extended Mode Register controls the functions

beyond those controlled by the Mode Register. These
additional functions are special features of the Mobile
device. They include Temperature Compensated Self
Refresh (TCSR) Control, and Partial Array Self Refresh
(PASR).

The Extended Mode Register is programmed via the

Mode Register Set command (BA1=1,BA0=0) and
retains the stored information until it is programmed
again or the device loses power.

The Extended Mode Register must be programmed

with M5 through M11 set to "0". The Extended Mode
Register must be loaded when all banks are idle and no
bursts are in progress, and the controller must wait the
specified time before before initiating any subsequent
operation. Violating either of these requirements
results in unspecified operation.

Temperature Compensated Self Refresh

Temperature Compensated Self Refresh (TCSR)

allows the controller to program the Refresh interval
during SELF REFRESH mode, according to the case
temperature of the Mobile device. This allows great
power savings during SELF REFRESH during most
operating temperature ranges. Only during extreme
temperatures would the controller have to select a
TCSR level that will guarantee data during SELF
REFRESH.

Every cell in the DRAM requires refreshing due to

the capacitor losing its charge over time. The refresh
rate is dependent on temperature. At higher tempera-
tures a capacitor loses charge quicker than at lower
temperatures, requiring the cells to be refreshed more
often. Historically, during Self Refresh, the refresh rate
has been set to accomodate the worst case, or highest
temperature range expected.

Thus, during ambient temperatures, the power con-

sumed during refresh was unnecessarily high, because
the refresh rate was set to accommodate the higher
temperatures. Setting M4 and M3, allow the DRAM to
accomodate more specific temperature regions during
SELF REFRESH. There are four temperature settings,
which will vary the SELF REFRESH current according
to the selected temperature. This selectable refresh
rate will save power when the DRAM is operating at
normal temperatures.

Table 5:

CAS Latency

SPEED

ALLOWABLE OPERATING FREQUENCY

(MHZ)

CAS

LATENCY = 1

CAS

LATENCY = 2

CAS

LATENCY = 3

- 8

£ 50

£ 100

£ 125

- 10

£ 40

£ 83

£ 100

Maximum Case Temp

A4 A3

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

A10

A11

PASR

TCSR

All must be set to "0"

BA0

M7 M6 M5 M4 M3

M2 M1 M0

M10

M11

M12

BA1

M13

85°C

70°C

45°C

15°C

Self Refresh Coverage

Four Banks

Two Banks (Bank 0,1)

One Bank (Bank 0)

RFU

128Mb: x16, x32

MOBILE SDRAM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx16x32.fm - Rev. G 3/03 EN

Commands

Truth Table 1 provides a quick reference of available

commands. This is followed by a written description of
each command. Three additional Truth Tables appear
following the Operation section; these tables provide
current state/next state information.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A10 define the op-code written to the mode register.
3. A0-A11 provide row address, and BA0, BA1 determine which bank is made active.
4. A0-A8 (x16) or A0-A7 (x32) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent),

while A10 LOW disables the auto precharge feature; BA0, BA1 determine which bank is being read from or written
to.

5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks precharged and BA0, BA1 are

"Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). DQM0 controls

DQ0-7, DQM1 controls DQ8-15, DQM2 controls DQ16-23, and DQM3 controls DQ24-31.

Table 6:

TRUTH TABLE 1 - Commands and DQM Operation

(Note: 1)

NAME (FUNCTION)

CS#

RAS

CAS

WE#

ADDR

DQS

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

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COMMAND INHIBIT

The COMMAND INHIBIT function prevents new

commands from being executed by the SDRAM,
regardless of whether the CLK signal is enabled. The
SDRAM is effectively deselected. Operations already in
progress are not affected.

NO Operation (NOP)

The NO OPERATION (NOP) command is used to

perform a NOP to an SDRAM which is selected (CS# is
LOW). This prevents unwanted commands from being
registered during idle or wait states. Operations
already in progress are not affected.

LOAD mode register

The mode register is loaded via inputs A0, BA0, BA1.

See mode register heading in the Register Definition
section. The LOAD MODE REGISTER and LOAD
EXTENDED MODE REGISTER commands can only be
issued when all banks are idle, and a subsequent exe-
cutable command cannot be issued until

MRD is met.

ACTIVE

The ACTIVE command is used to open (or activate)

a row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and the
address provided on inputs A0-A11 selects the row.
This row remains active (or open) for accesses until a
precharge command is issued to that bank. A pre-
charge command must be issued before opening a dif-
ferent row in the same bank.

READ

The READ command is used to initiate a burst read

access to an active row. The value on the BA0, BA1
inputs selects the bank, and the address provided on
inputs A0-A8 (x16) or A0-A7 (x32) selects the starting
column location. The value on input A10 determines
whether or not auto precharge is used. If auto pre-
charge is selected, the row being accessed will be pre-
charged at the end of the read burst; if auto precharge
is not selected, the row will remain open for subse-
quent accesses. Read data appears on the DQs subject
to the logic level on the DQM inputs two clocks earlier.
If a given DQM signal was registered HIGH, the corre-
sponding DQs will be High-Z two clocks later; if the
DQM signal was registered LOW, the DQs will provide
valid data.

WRITE

The WRITE command is used to initiate a burst

write access to an active row. The value on the BA0,
BA1 inputs selects the bank, and the address provided
on inputs A0-A8 (x16) or A0-A7 (x32) selects the start-
ing column location. The value on input A10 deter-
mines whether or not auto precharge is used. If auto
precharge is selected, the row being accessed will be
precharged at the end of the write burst; if auto pre-
charge is not selected, the row will remain open for
subsequent accesses. Input data appearing on the DQs
is written to the memory array subject to the DQM
input logic level appearing coincident with the data. If
a given DQM signal is registered LOW, the correspond-
ing data will be written to memory; if the DQM signal
is registered HIGH, the corresponding data inputs will
be ignored, and a write will not be executed to that
byte/column location.

PRECHARGE

The PRECHARGE command is used to deactivate

the open row in a particular bank or the open row in all
banks. The bank(s) will be available for a subsequent
row access a specified time (

RP) after the precharge

command is issued. Input A10 determines whether
one or all banks are to be precharged, and in the case
where only one bank is to be precharged, inputs BA0,
BA1 select the bank. Otherwise BA0, BA1 are treated as
"Don't Care." Once a bank has been precharged, it is in
the idle state and must be activated prior to any READ
or WRITE commands being issued to that bank.

Auto Precharge

Auto precharge is a feature which performs the

same individual-bank precharge function described
above, without requiring an explicit command. This is
accomplished by using A10 to enable auto precharge
in conjunction with a specific READ or WRITE com-
mand. A precharge of the bank/row that is addressed
with the READ or WRITE command is automatically
performed upon completion of the READ or WRITE
burst, except in the full-page burst mode, where auto
precharge does not apply. Auto precharge is nonpersis-
tent in that it is either enabled or disabled for each
individual Read or Write command.

Auto precharge ensures that the precharge is initi-

ated at the earliest valid stage within a burst. The user
must not issue another command to the same bank
until the precharge time (

RP) is completed. This is

determined as if an explicit PRECHARGE command
was issued at the earliest possible time, as described
for each burst type in the Operation section of this
data sheet.

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BURST TERMINATE

The BURST TERMINATE command is used to trun-

cate either fixed-length or full-page bursts. The most
recently registered READ or WRITE command prior to
the BURST TERMINATE command will be truncated,
as shown in the Operation section of this data sheet.

AUTO REFRESH

AUTO REFRESH is used during normal operation of

the SDRAM and is analogous to CAS#-BEFORE-RAS#
(CBR) refresh in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a
refresh is required. All active banks must be PRE-
CHARGED prior to issuing an AUTO REFRESH com-
mand. The AUTO REFRESH command should not be
issued until the minimum

RP has been met after the

PRECHARGE command as shown in the operation sec-
tion.

The addressing is generated by the internal refresh

controller. This makes the address bits "Don't Care"
during an AUTO REFRESH command. The 128Mb
SDRAM requires 4,096 AUTO REFRESH cycles every
64ms (

REF), regardless of width option. Providing a

distributed AUTO REFRESH command every 15.625µs
will meet the refresh requirement and ensure that each
row is refreshed. Alternatively, 4,096 AUTO REFRESH
commands can be issued in a burst at the minimum
cycle rate (

RFC), once every 64ms.

SELF REFRESH

The SELF REFRESH command can be used to retain

data in the SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the
SDRAM retains data without external clocking. The
SELF REFRESH command is initiated like an AUTO
REFRESH command except CKE is disabled (LOW).
Once the SELF REFRESH command is registered, all
the inputs to the SDRAM become "Don't Care" with the
exception of CKE, which must remain LOW.

Once self refresh mode is engaged, the SDRAM pro-

vides its own internal clocking, causing it to perform
its own auto refresh cycles. The SDRAM must remain
in self refresh mode for a minimum period equal to

RAS and may remain in self refresh mode for an indef-

inite period beyond that.

The procedure for exiting self refresh requires a

sequence of commands. First, CLK must be stable (sta-
ble clock is defined as a signal cycling within timing
constraints specified for the clock pin) prior to CKE
going back HIGH. Once CKE is HIGH, the SDRAM
must have NOP commands issued (a minimum of two
clocks) for

XSR because time is required for the com-

pletion of any internal refresh in progress.

Upon exiting the self refresh mode, AUTO REFRESH

commands must be issued every 15.625µs or less as
both SELF REFRESH and AUTO REFRESH utilize the
row refresh counter.

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Operation

BANK/ROW ACTIVATION

Before any READ or WRITE commands can be

issued to a bank within the SDRAM, a row in that bank
must be "opened." This is accomplished via the
ACTIVE command, which selects both the bank and
the row to be activated (seeFigure 8).

After opening a row (issuing an ACTIVE command),

a READ or WRITE command may be issued to that row,
subject to the tRCD specification.

RCD (MIN) should

be divided by the clock period and rounded up to the
next whole number to determine the earliest clock
edge after the ACTIVE command on which a READ or
WRITE command can be entered. For example, a

RCD

specification of 20ns with a 125 MHz clock (8ns
period) results in 2.5 clocks, rounded to 3. This is
reflected in Figure 9, which covers any case where 2 <

RCD (MIN)/

£ 3. (The same procedure is used to

convert other specification limits from time units to
clock cycles.)

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous
active row has been "closed" (precharged). The mini-
mum time interval between successive ACTIVE com-
mands to the same bank is defined by

RC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,
which results in a reduction of total row-access over-

head. The minimum time interval between successive
ACTIVE commands to different banks is defined by

RRD.

Figure 8: Activating a Specific Row in a

Specific Bank

Figure 9: Example: Meeting

RCD (MIN) When 2 <

RCD (MIN)/

CK< 3

CS#

WE#

CAS#

RAS#

CKE

CLK

A0A10, A11

ROW

ADDRESS

DON'T CARE

HIGH

BA0, BA1

BANK

ADDRESS

CLK

COMMAND

NOP

ACTIVE

READ or

WRITE

NOP

RCD

DON'T CARE

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READs

READ bursts are initiated with a READ command, as

shown in Figure 10.

The starting column and bank addresses are pro-

vided with the READ command, and auto precharge is
either enabled or disabled for that burst access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the generic
READ commands used in the following illustrations,
auto precharge is disabled.

During READ bursts, the valid data-out element

from the starting column address will be available fol-
lowing the CAS latency after the READ command.
Each subsequent data-out element will be valid by the
next positive clock edge. Figure 11 shows general tim-
ing for each possible CAS latency setting.

Figure 10: READ Command

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-
Z. A full-page burst will continue until terminated. (At
the end of the page, it will wrap to column 0 and con-
tinue.)

Data from any READ burst may be truncated with a

subsequent READ command, and data from a fixed-
length READ burst may be immediately followed by
data from a READ command. In either case, a continu-
ous flow of data can be maintained. The first data ele-
ment from the new burst follows either the last
element of a completed burst or the last desired data
element of a longer burst that is being truncated. The
new READ command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one.

Figure 11: CAS Latency

DON'T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN
ADDRESS

A0-A8

A10

BA0,1

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A9, A11

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 1

OUT

tOH

COMMAND

NOP

READ

tAC

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

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This is shown in Figure 11 for CAS latencies of two and
three; data element n + 3 is either the last of a burst of
four or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch

architecture. A READ command can be initiated on
any clock cycle following a previous READ command.
Full-speed random read accesses can be performed to
the same bank, as shown in Figure 12, or each subse-
quent READ may be performed to a different bank.

Figure 12: Consecutive READ Bursts

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 0 cycles

NOTE: Each READ command may be to either bank. DQM is LOW.

CAS Latency = 1

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

X = 1 cycle

CAS Latency = 2

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

BANK,

COL b

OUT

n + 1

OUT

n + 2

OUT

n + 3

OUT

READ

NOP

X = 2 cycles

CAS Latency = 3

DON'T CARE

TRANSITIONING DATA

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Data from any READ burst may be truncated with a

subsequent WRITE command, and data from a fixed-
length READ burst may be immediately followed by
data from a WRITE command (subject to bus turn-
around limitations). The WRITE burst may be initiated
on the clock edge immediately following the last (or
last desired) data element from the READ burst, pro-
vided that I/O contention can be avoided. In a given
system design, there may be a possibility that the
device driving the input data will go Low-Z before the
SDRAM DQs go High-Z. In this case, at least a single-
cycle delay should occur between the last read data
and the WRITE command.

Figure 14: READ to WRITE

The DQM input is used to avoid I/O contention, as

shown in Figure 14 and Figure 15. The DQM signal
must be asserted (HIGH) at least two clocks prior to
the WRITE command (DQM latency is two clocks for
output buffers) to suppress data-out from the READ.
Once the WRITE command is registered, the DQs will
go High-Z (or remain High-Z), regardless of the state of
the DQM signal, provided the DQM was active on the
clock just prior to the WRITE command that truncated
the READ command. If not, the second WRITE will be
an invalid WRITE. For example, if DQM was LOW dur-
ing T4 in Figure 15, then the WRITEs at T5 and T7
would be valid, while the WRITE at T6 would be
invalid.

The DQM signal must be de-asserted prior to the

WRITE command (DQM latency is zero clocks for
input buffers) to ensure that the written data is not
masked. Figure 14 shows the case where the clock fre-
quency allows for bus contention to be avoided with-
out adding a NOP cycle, and Figure 15 shows the case
where the additional NOP is needed.

Figure 15: READ to WRITE with Extra

Clock Cycle

A fixed-length READ burst may be followed by, or

truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a PRE-
CHARGE command to the same bank. The PRE-
CHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This
is shown in Figure 16 for each possible CAS latency;
data element n + 3 is either the last of a burst of four or
the last desired of a longer burst. Following the PRE-
CHARGE command, a subsequent command to the
same bank cannot be issued until

RP is met. Note that

part of the row precharge time is hidden during the
access of the last data element(s).

In the case of a fixed-length burst being executed to

completion, a PRECHARGE command issued at the
optimum time (as described above) provides the same
operation that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the
command and address buses be available at the
appropriate time to issue the command; the advantage
of the PRECHARGE command is that it can be used to
truncate fixed-length or full-page bursts.

DON'T CARE

READ

NOP

WRITE

NOP

CLK

DQM

OUT

COMMAND

ADDRESS

BANK,

COL n

BANK,

COL b

tHZ

tCK

NOTE:

A CAS latency of three is used for illustration. The READ
command may be to any bank, and the WRITE command
may be to any bank. If a burst of one is used, then DQM is
not required.

TRANSITIONING DATA

DON'T CARE

READ

NOP

DQM

CLK

OUT

COMMAND

ADDRESS

BANK,

COL n

WRITE

BANK,

COL b

tHZ

NOTE:

A CAS latency of three is used for illustration. The READ command
may be to any bank, and the WRITE command may be to any bank.

TRANSITIONING DATA

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Figure 16: READ to PRECHARGE

CLK

OUT

COMMAND

ADDRESS

READ

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

t RP

NOTE: DQM is LOW.

CLK

OUT

COMMAND

ADDRESS

READ

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

t RP

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK a,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

PRECHARGE

ACTIVE

t RP

BANK a,

ROW

BANK

(a or all)

DON'T CARE

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

BANK a,

COL n

BANK a,

ROW

BANK

(a or all)

BANK a,

COL n

BANK a,

ROW

BANK

(a or all)

X = 2 cycles

TRANSITIONING DATA

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Full-page READ bursts can be truncated with the

BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that auto precharge was
not activated. The BURST TERMINATE command

should be issued x cycles before the clock edge at
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 17 for each possible CAS latency; data element
n + 3 is the last desired data element of a longer burst.

Figure 17: Terminating a READ Burst

DON'T CARE

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

NOTE: DQM is LOW.

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

BURST

TERMINATE

NOP

X = 0 cycles

CAS Latency = 1

X = 1 cycle

CAS Latency = 2

CAS Latency = 3

X = 2 cycles

TRANSITIONING DATA

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WRITEs

WRITE bursts are initiated with a WRITE command,

as shown in Figure 18.

The starting column and bank addresses are pro-

vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the generic
WRITE commands used in the following illustrations,
auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQs will remain High-Z and
any additional input data will be ignored (see
Figure 19). A full-page burst will continue until termi-
nated. (At the end of the page, it will wrap to column 0
and continue.)

Figure 18: WRITE Command

Data for any WRITE burst may be truncated with a

subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE com-
mand can be issued on any clock following the previ-
ous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 19. Data n +
1 is either the last of a burst of two or the last desired of
a longer burst. The 128Mb SDRAM uses a pipelined
architecture and therefore does not require the 2n rule
associated with a prefetch architecture. A WRITE com-
mand can be initiated on any clock cycle following a
previous WRITE command. Full-speed random write
accesses within a page can be performed to the same
bank, as shown in Figure 20, or each subsequent
WRITE may be performed to a different bank.

Figure 19: WRITE Burst

Figure 20: WRITE to WRITE

CS#

WE#

CAS#

RAS#

CKE

CLK

COLUMN
ADDRESS

DON'T CARE

HIGH

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

BANK

ADDRESS

A0-A8

A10

BA0,1

A9, A11

VALID ADDRESS

CLK

COMMAND

ADDRESS

NOP

WRITE

n + 1

NOP

BANK,

COL n

NOTE:

Burst length = 2. DQM is LOW.

DON'T CARE

TRANSITIONING DATA

DON'T CARE

CLK

COMMAND

ADDRESS

NOP

WRITE

BANK,

COL n

BANK,

COL b

n + 1

NOTE:

DQM is LOW. Each WRITE
command may be to any bank.

TRANSITIONING DATA

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Data for any WRITE burst may be truncated with a

subsequent READ command, and data for a fixed-
length WRITE burst may be immediately followed by a
READ command. Once the READ command is regis-
tered, the data inputs will be ignored, and writes will
not be executed. An example is shown in Figure 22.
Data n + 1 is either the last of a burst of two or the last
desired of a longer burst.

Data for a fixed-length WRITE burst may be fol-

lowed by, or truncated with, a PRECHARGE command
to the same bank (provided that auto precharge was
not activated), and a full-page WRITE burst may be
truncated with a PRECHARGE command to the same
bank. The PRECHARGE command should be issued

WR after the clock edge at which the last desired input

data element is registered. The auto precharge mode
requires a

WR of at least one clock plus time, regard-

less of frequency.

In addition, when truncating a WRITE burst, the

DQM signal must be used to mask input data for the
clock edge prior to, and the clock edge coincident with,
the PRECHARGE command. An example is shown in
Figure 23. Data n + 1 is either the last of a burst of two
or the last desired of a longer burst. Following the PRE-
CHARGE command, a subsequent command to the
same bank cannot be issued until

RP is met.

In the case of a fixed-length burst being executed to

Figure 21: Random WRITE Cycles

Figure 22: WRITE to READ

Figure 23: WRITE to PRECHARGE

DON'T CARE

CLK

COMMAND

ADDRESS

WRITE

BANK,

COL n

WRITE

BANK,

COL a

BANK,

COL x

BANK,
COL m

NOTE:

Each WRITE command may be to any bank.
DQM is LOW.

TRANSITIONING DATA

DON'T CARE

CLK

COMMAND

ADDRESS

NOP

WRITE

BANK,

COL n

n + 1

OUT

READ

NOP

BANK,

COL b

NOP

OUT

b + 1

NOTE:

The WRITE command may be to any bank, and the READ command may
be to any bank. DQM is LOW. CAS latency = 2 for illustration.

TRANSITIONING DATA

DQM

CLK

COMMAND

ADDRESS

BANK a,

COL n

NOP

WRITE

PRECHARGE

NOP

n + 1

ACTIVE

t RP

BANK

(a or all)

t WR

BANK a,

ROW

DQM

COMMAND

ADDRESS

BANK a,

COL n

NOP

WRITE

PRECHARGE

NOP

n + 1

ACTIVE

t RP

DON'T CARE

BANK

(a or all)

t WR

NOTE:

DQM could remain LOW in this example if the WRITE burst is a fixed length
of two.

BANK a,

ROW

NOP

WR@

CK 15ns

WR@

CK < 15ns

TRANSITIONING DATA

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Fixed-length or full-page WRITE bursts can be trun-

cated with the BURST TERMINATE command. When
truncating a WRITE burst, the input data applied coin-
cident with the BURST TERMINATE command will be
ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one
clock previous to the BURST TERMINATE command.
This is shown in Figure 24, where data n is the last
desired data element of a longer burst.

Figure 24: Terminating a WRITE Burst

Figure 25: PRECHARGE Command

PRECHARGE

The PRECHARGE command (see Figure 25) is used

to deactivate the open row in a particular bank or the
open row in all banks. The bank(s) will be available for
a subsequent row access some specified time (

RP)

after the precharge command is issued. Input A10
determines whether one or all banks are to be pre-
charged, and in the case where only one bank is to be
precharged, inputs BA0, BA1 select the bank. When all
banks are to be precharged, inputs BA0, BA1 are
treated as "Don't Care." Once a bank has been pre-
charged, it is in the idle state and must be activated
prior to any READ or WRITE commands being issued
to that bank.

POWER-DOWN

Power-down occurs if CKE is registered low coinci-

dent with a NOP or COMMAND INHIBIT when no
accesses are in progress. If power-down occurs when
all banks are idle, this mode is referred to as precharge
power-down; if power-down occurs when there is a
row active in any bank, this mode is referred to as
active power-down. Entering power-down deactivates
the input and output buffers, excluding CKE, for maxi-
mum power savings while in standby. The device may
not remain in the power-down state longer than the
refresh period (64ms) since no refresh operations are
performed in this mode.

The power-down state is exited by registering a NOP

or COMMAND INHIBIT and CKE HIGH at the desired
clock edge (meeting

CKS). See Figure 26.

Figure 26: Power-Down

CLK

COMMAND

ADDRESS

BANK,

COL n

WRITE

BURST

TERMINATE

COMMAND

(ADDRESS)

(DATA)

NOTE:

DQMs are LOW.

TRANSITIONING DATA

DON'T CARE

CS#

WE#

CAS#

RAS#

CKE

CLK

A10

DON'T CARE

HIGH

All Banks

Bank Selected

A0-A9

BA0,1

BANK

ADDRESS

VALID ADDRESS

DON'T CARE

tRAS

tRCD

tRC

All banks idle

Input buffers gated off

Exit power-down mode.

(

)

(

)

(

)

(

)

(

)

(

)

tCKS

> tCKS

COMMAND

NOP

ACTIVE

Enter power-down mode.

NOP

CLK

CKE

(

)

(

)

(

)

(

)

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CLOCK SUSPEND

The clock suspend mode occurs when a column

access/burst is in progress and CKE is registered low.
In the clock suspend mode, the internal clock is deacti-
vated, "freezing" the synchronous logic.

For each positive clock edge on which CKE is sam-

pled LOW, the next internal positive clock edge is sus-
pended. Any command or data present on the input
pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in
Figure 27 and Figure 28.)

Figure 27: Clock Suspend During WRITE

Burst

Clock suspend mode is exited by registering CKE

HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.

BURST READ/SINGLE WRITE

The burst read/single write mode is entered by pro-

gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one), regardless of the programmed burst
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).

Figure 28: Clock Suspend During READ

Burst

DON'T CARE

COMMAND

ADDRESS

WRITE

BANK,

COL n

NOP

CLK

CKE

INTERNAL

CLOCK

NOP

n + 1

n + 2

NOTE: For this example, burst length = 4 or greater, and DM

is LOW.

TRANSITIONING DATA

DON'T CARE

CLK

OUT

COMMAND

ADDRESS

READ

NOP

BANK,

COL n

NOP

OUT

n + 1

OUT

n + 2

OUT

n + 3

NOTE: For this example, CAS latency = 2, burst length = 4 or greater, and

DQM is LOW.

CKE

INTERNAL

CLOCK

NOP

TRANSITIONING DATA

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CONCURRENT Auto Precharge

An access command (READ or WRITE) to another

bank while an access command with auto precharge
enabled is executing is not allowed by SDRAMs, unless
the SDRAM supports Concurrent Auto precharge.
Micron SDRAMs support Concurrent Auto precharge.
Four cases where Concurrent Auto precharge occurs
are defined below.

READ with Auto Precharge
1. Interrupted by a READ (with or without auto pre-

charge): A READ to bank m will interrupt a READ on
bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered
(Figure 29).

2. Interrupted by a WRITE (with or without auto pre-

charge): A WRITE to bank m will interrupt a READ
on bank n when registered. DQM should be used
two clocks prior to the WRITE command to prevent
bus contention. The precharge to bank n will begin
when the WRITE to bank m is registered (Figure 30).

Figure 29: READ With Auto Precharge Interrupted by a READ

Figure 30: READ With Auto Precharge Interrupted by a WRITE

DON'T CARE

CLK

OUT

COMMAND

READ - AP

BANK n

NOP

OUT

a + 1

OUT

d + 1

NOP

BANK n

CAS Latency = 3 (BANK m)

BANK m

ADDRESS

Idle

NOP

NOTE: DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal
States

Page Active

READ with Burst of 4

Interrupt Burst, Precharge

Page Active

READ with Burst of 4

Precharge

RP - BANK n

tRP - BANK m

CAS Latency = 3 (BANK n)

TRANSITIONING DATA

CLK

OUT

COMMAND

NOP

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

Idle

NOP

DQM

NOTE: 1. DQM is HIGH at T2 to prevent D

OUT

-a+1 from contending with D

-d at T4.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal
States

Page

Active

READ with Burst of 4

Interrupt Burst, Precharge

Page Active

WRITE with Burst of 4

Write-Back

RP - BANK n

t WR - BANK m

CAS Latency = 3 (BANK n)

READ - AP

BANK n

DON'T CARE

TRANSITIONING DATA

d + 1

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WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto pre-

charge): A READ to bank m will interrupt a WRITE
on bank n when registered, with the data-out
appearing CAS latency later. The precharge to bank
n will begin after

WR is met, where

WR begins

when the READ to bank m is registered. The last
valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 31).

4. Interrupted by a WRITE (with or without auto pre-

charge): A WRITE to bank m will interrupt a WRITE
on bank n when registered. The precharge to bank n
will begin after

WR is met, where

WR begins when

the WRITE to bank m is registered. The last valid
data WRITE to bank n will be data registered one
clock prior to a WRITE to bank m (Figure 32).

Figure 31: WRITE With Auto Precharge Interrupted by a READ

Figure 32: WRITE With Auto Precharge Interrupted by a WRITE

DON'T CARE

CLK

COMMAND

WRITE - AP

BANK n

NOP

a + 1

NOP

BANK n

BANK m

ADDRESS

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

READ - AP

BANK m

Internal
States

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active

READ with Burst of 4

tRP - BANK m

OUT

d + 1

CAS Latency = 3 (BANK m)

RP - BANK n

WR - BANK n

TRANSITIONING DATA

DON'T CARE

CLK

COMMAND

WRITE - AP

BANK n

NOP

d + 1

a + 1

a + 2

d + 2

d + 3

NOP

BANK n

BANK m

ADDRESS

NOP

NOTE: 1. DQM is LOW.

BANK n,

COL a

BANK m,

COL d

WRITE - AP

BANK m

Internal
States

Page Active

WRITE with Burst of 4

Interrupt Burst, Write-Back

Precharge

Page Active

WRITE with Burst of 4

Write-Back

WR - BANK n

tRP - BANK n

t WR - BANK m

TRANSITIONING DATA

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NOTE:

1. CKE

is the logic state of CKE at clock edge n; CKE

n-1

was the state of CKE at the previous clock edge.

2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND

is the command registered at clock edge n, and ACTION

is a result of COMMAND

4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided

that

CKS is met).

6. Exiting self refresh at clock edge n will put the device in the all banks idle state once

XSR is met. COMMAND INHIBIT or

NOP commands should be issued on any clock edges occurring during the

XSR period. A minimum of two NOP com-

mands must be provided during

XSR period.

7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock

edge n + 1.

Table 7:

Truth Table CKE

(Notes: 1-4)

CKE

n-1

CKE

CURRENT STATE

COMMAND

ACTION

NOTES

Power-Down

Maintain Power-Down

Self Refresh

Maintain Self Refresh

Clock Suspend

Maintain Clock Suspend

Power-Down

COMMAND INHIBIT or NOP

Exit Power-Down

Self Refresh

COMMAND INHIBIT or NOP

Exit Self Refresh

Clock Suspend

Exit Clock Suspend

All Banks Idle

COMMAND INHIBIT or NOP

Power-Down Entry

All Banks Idle

AUTO REFRESH

Self Refresh Entry

Reading or Writing

VALID

Clock Suspend Entry

See Truth Table 3

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NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after tXSR has been met (if the

previous state was self refresh).

2. This table is bank-specific, except where noted; i.e., the current state is for a specific bank and the commands shown

are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below.

3. Current state definitions:

Idle:The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no register accesses are

4. The following states must not be interrupted by a command issued to the same bank. COMMAND INHIBIT or NOP

commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and Truth Table 3, and according
to Truth Table 4.

Precharging: Starts with registration of a PRECHARGE command and ends when

RP is met. Once

RP is met, the bank will be in

the idle state.
Row Activating: Starts with registration of an ACTIVE command and ends when

RCD is met. Once

RCD is met, the bank will be

in the row active state.
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when

has been met. Once

RP is met, the bank will be in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when

RP has been met. Once

RP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; COMMAND INHIBIT or NOP commands

must be applied on each positive clock edge during these states.

Refreshing: Starts with registration of an AUTO REFRESH command and ends when

RC is met. Once

RC is met, the SDRAM will

be in the all banks idle state.
Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when

MRD has been met.

Once

MRD is met, the SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when

RP is met. Once

RP is met, all banks

will be in the idle state.

6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all banks are to be precharged, all must be in a valid state for precharging.
9. Not bank-specific; BURST TERMINATE affects the most recent READ or WRITE burst, regardless of bank.
10.READs or WRITEs listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

11.Does not affect the state of the bank and acts as a NOP to that bank.

Table 8:

TRUTH TABLE 3 CURRENT STATE BANK n, COMMAND TO BANK n

Notes: 1-6; notes appear below table

CURRENT

STATE

CS#

RAS# CAS# WE# COMMAND (ACTION)

NOTES

Any

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Idle

ACTIVE (Select and activate row)

AUTO REFRESH

LOAD MODE REGISTER

PRECHARGE

Row Active

READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Deactivate row in bank or banks)

Read (Auto

Precharge

Disabled)

READ (Select column and start new READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE (Truncate READ burst, start PRECHARGE)

BURST TERMINATE

Write (Auto

Precharge

Disabled)

READ (Select column and start READ burst)

WRITE (Select column and start new WRITE burst)

PRECHARGE (Truncate WRITE burst, start PRECHARGE)

BURST TERMINATE

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NOTE:

1. This table applies when CKE

n-1

was HIGH and CKE

is HIGH (see Truth Table 2) and after tXSR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the com-

mands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given com-
mand is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and

RP has been met.

Row Active: A row in the bank has been activated, and

RCD has been met. No data bursts/accesses and no register accesses are

in progress.
Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated.
Read w/Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled, and ends when

has been met. Once

RP is met, the bank will be in the idle state.

Write w/Auto Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled, and ends when

RP has been met. Once

RP is met, the bank will be in the idle state.

4. AUTO REFRESH, SELF REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle.
5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current

state only.

6. All states and sequences not shown are illegal or reserved.
7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge

enabled and READs or WRITEs with auto precharge disabled.

8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the auto precharge command when its burst has been inter-

rupted by bank m's burst.

9. Burst in bank n continues as initiated.

Table 9:

TRUTH TABLE 4 CURRENT STATE BANK n, COMMAND TO BANK m

Notes: 1-6; notes appear below and on next page

CURRENT STATE CS# RAS# CAS# WE# COMMAND (ACTION)

NOTES

Any

COMMAND INHIBIT (NOP/Continue previous operation)

NO OPERATION (NOP/Continue previous operation)

Idle

Any Command Otherwise Allowed to Bank m

Row

Activating,

Active, or

Precharging

ACTIVE (Select and activate row)

READ (Select column and start READ burst)

WRITE (Select column and start WRITE burst)

PRECHARGE

Read

(Auto

Precharge

Disabled)

ACTIVE (Select and activate row)

READ (Select column and start new READ burst)

7, 10

WRITE (Select column and start WRITE burst)

7, 11

PRECHARGE

Write

(Auto

Precharge

Disabled)

ACTIVE (Select and activate row)

READ (Select column and start READ burst)

7, 12

WRITE (Select column and start new WRITE burst)

7, 13

PRECHARGE

Read

(With Auto

Precharge)

ACTIVE (Select and activate row)

READ (Select column and start new READ burst)

7, 8, 14

WRITE (Select column and start WRITE burst)

7, 8, 15

PRECHARGE

Write

(With Auto

Precharge)

ACTIVE (Select and activate row)

READ (Select column and start READ burst)

7, 8, 16

WRITE (Select column and start new WRITE burst)

7, 8, 17

PRECHARGE

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10.For a READ without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m

will interrupt the READ on bank n, CAS latency later (Figure 12).

11.For a READ without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

will interrupt the READ on bank n when registered (Figure 14 and Figure 15). DQM should be used one clock prior to
the WRITE command to prevent bus contention.

12.For a WRITE without auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m

will interrupt the WRITE on bank n when registered (Figure 22), with the data-out appearing CAS latency later. The
last valid WRITE to bank n will be data-in registered one clock prior to the READ to bank m.

13.For a WRITE without auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank

will interrupt the WRITE on bank n when registered (Figure 20). The last valid WRITE to bank n will be data-in regis-
tered one clock prior to the READ to bank m.

14.For a READ with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the READ on bank n, CAS latency later. The PRECHARGE to bank n will begin when the READ to bank m is
registered (Figure 29).

15.For a READ with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m will

interrupt the READ on bank n when registered. DQM should be used two clocks prior to the WRITE command to pre-
vent bus contention. The PRECHARGE to bank n will begin when the WRITE to bank m is registered (Figure 30).

16.For a WRITE with auto precharge interrupted by a READ (with or without auto precharge), the READ to bank m will

interrupt the WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to

bank n will begin after

WR is met, where

WR begins when the READ to bank m is registered. The last valid WRITE

bank n will be data-in registered one clock prior to the READ to bank m (Figure 31).

17.For a WRITE with auto precharge interrupted by a WRITE (with or without auto precharge), the WRITE to bank m

interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after

WR is met, where

begins when the WRITE to bank m is registered. The last valid WRITE to bank n will be data registered one clock to
the WRITE to bank m (Figure 32).

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ABSOLUTE MAXIMUM RATINGS

Voltage on V

Q Supply

Relative to V

(3.3V) . . . . . . . . . . . . . . . .-1V to +4.6V

Relative to V

(2.5V). . . . . . . . . . . . . . . . 0.5V to +3.6V

Voltage on Inputs, NC or I/O Pins
Relative to V

((3.3V) . . . . . . . . . . . . . . . .-1V to +4.6V

Relative to V

(2.5V). . . . . . . . . . . . . . . .-0.5V to +3.6V

Operating Temperature
T

(Commercial) . . . . . . . . . . . . . . . . . . . 0°C to +70°C

(Industrial) . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Storage Temperature (plastic) . . . . -55°C to +150°C
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1W

Stresses greater than those listed under "Absolute

Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

Table 10: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(LC VERSION)

Notes: 1, 5, 6; notes appear on page 37; V

= +3.3V ±0.3V, V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

3.6

I/O Supply Voltage

3.6

Input High Voltage: Logic 1; All inputs

+ 0.3

Input Low Voltage: Logic 0; All inputs

-0.3

0.8

Data Output High Voltage: Logic 1; All inputs

2.4

Data Output LOW Voltage: LOGIC 0; All inputs

0.4

Input Leakage Current:

-5

µA

Any Input 0V

£ VIN £ V

(All other pins not under test = 0V)

Output Leakage Current: DQs are disabled; 0V

£ VOUT £ V

-5

µA

Table 11: DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(V VERSION)

Notes: 1, 5, 6; notes appear on page 37; V

= 2.5 ±0.2V, V

Q = +2.5V ±0.2V or +1.8V ±0.15V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.3

2.7

I/O Supply Voltage

1.65

2.7

Input High Voltage: Logic 1; All inputs

1.25

+ 0.3

Input Low Voltage: Logic 0; All inputs

-0.3

+0.55

Data Output High Voltage: Logic 1; All inputs

Q - 0.2

Data Output Low Voltage: LOGIC 0; All inputs

0.2

Input Leakage Current:

-5

µA

Any input 0V

£ VIN £ V

(All other pins not under test = 0V)

Output Leakage Current: DQs are disabled; 0V

£ VOUT £ V

-5

µA

Table 12: AC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

= +3.3V ±0.3V or 2.5 ±0.2V, V

Q = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V ±0.15V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High Voltage: Logic 1; All inputs

1.4

Input Low Voltage: Logic 0; All inputs

0.4

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Table 13: ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING

CONDITIONS

Notes: 5, 6, 8, 9, 11; notes appear on page 37

AC CHARACTERISTICS

-8

-10

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

UNITS NOTES

Access time from CLK (pos. edge)

CL = 3

AC (3)

CL = 2

AC (2)

CL = 1

AC (1)

Address hold time

Address setup time

2.5

CLK high-level width

CLK low-level width

Clock cycle time

CL = 3

CK (3)

CL = 2

CK (2)

CL = 1

CK (1)

CKE hold time

CKH

CKE setup time

CKS

2.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

2.5

Data-in hold time

Data-in setup time

2.5

Data-out high-impedance time

CL = 3

HZ (3)

CL = 2

HZ (2)

CL = 1

HZ (1)

Data-out low-impedance time

Data-out hold time (load)

2.5

Data-out hold time (no load)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

100

ACTIVE to READ or WRITE delay

RCD

Refresh period (4,096 rows)

REF

AUTO REFRESH period

RFC

100

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b
command

RRD

Transition time

0.5

1.2

0.5

1.2

WRITE recovery time

Auto Precharge

Mode

WR (a)

1 CLK

+7ns

1 CLK+

5ns

Manual

Precharge Mode

WR (m)

Exit SELF REFRESH to ACTIVE command

XSR

100

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Table 14: AC FUNCTIONAL CHARACTERISTICS

Notes: 5, 6, 7, 8, 9, 11; notes appear on page 37

PARAMETER

SYMBOL

-8

-10

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH
command

MRD

Data-out to high-impedance from PRECHARGE command

CL = 3

ROH(3)

CL = 2

ROH(2)

CL = 1

ROH(1)

Table 15: I

SPECIFICATIONS AND CONDITIONS (x16)

Notes: 1, 5, 6, 11, 13; notes appear on page 37; V

= +3.3V ±0.3V or 2.5 ±0.2V, V

Q = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V

±0.15V

MAX

PARAMETER/CONDITION

SYMBOL

-8

-10

UNITS

NOTES

Operating Current: Active Mode;

Burst = 2; READ or WRITE;

RC =

RC (MIN)

DD1

130

100

3, 18,

19, 32

Standby Current: Power-Down Mode; All banks idle; CKE
= LOW

DD2

350

µA

Standby Current: Active Mode;

CKE = HIGH; CS# = HIGH; All banks active after

RCD met;

No accesses in progress

DD3

3, 18,

19, 32

Operating Current: Burst Mode; Page burst;
READ or WRITE; All banks active

DD4

100

3, 18,

19, 32

Auto Refresh Current
CKE = HIGH; CS# = HIGH

RFC =

RFC

(MIN)

DD5

210

170

3, 12,

18, 19,

32, 33

RFC =

15.625µs

DD6

Table 16: I

7 - SELF REFRESH CURRENT OPTIONS (x16)

(Notes: Note 4 appears on page 37) (V

= +3.3V ±0.3V or 2.5 ±0.2V, V

Q) = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V ±0.15V)

TEMPERATURE COMPENSATED SELF REFRESH
PARAMETER/CONDITION

MAX

TEMPERATURE

-8 AND -10

UNITS

NOTES

Self Refresh Current:
CKE < 0.2V

85ºC

800

µA

70ºC

500

µA

45ºC

350

µA

15ºC

300

µA

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Table 17: I

SPECIFICATIONS AND CONDITIONS (x32)

(Notes: 1, 5, 6, 11, 13; notes appear on page 37; V

= +3.3V ±0.3V or 2.5 ±0.2V, V

Q = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V

±0.15V

MAX

PARAMETER/CONDITION

SYMBOL

-8

-10

UNITS

NOTES

Operating Current: Active Mode;

Burst = 2; READ or WRITE;

RC =

RC (MIN)

DD1

150

120

3, 18,

19, 32

Standby Current: Power-Down Mode; All banks idle; CKE
= LOW

DD2

350

µA

Standby Current: Active Mode;

CKE = HIGH; CS# = HIGH; All banks active after

RCD met;

No accesses in progress

DD3

3, 12,

19, 32

Operating Current: Burst Mode; Page burst;
READ or WRITE; All banks active

DD4

115

110

3, 18,

19, 32

Auto Refresh Current
CKE = HIGH; CS# = HIGH

RFC =

RFC

(MIN)

DD5

220

180

3, 12,

18, 19,

32, 33

RFC =

15.625µs

DD6

Table 18: I

7 - SELF REFRESH CURRENT OPTIONS (x32)

(Notes: Note 4 appears on page 37) (V

= +3.3V ±0.3V or 2.5 ±0.2V, V

Q = +3.3V ±0.3V or +2.5V ±0.2V or +1.8V ±0.15V)

TEMPERATURE COMPENSATED SELF REFRESH
PARAMETER/CONDITION

MAX

TEMPERATURE

-8 AND -10

UNITS

NOTES

Self Refresh Current:
CKE < 0.2V

85ºC

1000

µA

70ºC

550

µA

45ºC

400

µA

15ºC

350

µA

Table 19: CAPACITANCE

(Note: 2; notes appear on page 37)

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Input Capacitance: CLK

2.0

4.0

Input Capacitance: All other input-only pins

2.0

5.0

Input/Output Capacitance: DQs

3.5

6.0

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Notes

1. This parameter is sampled. V

, V

Q = +3.3V; f =

1 MHz, T

= 25°C; pin under test biased at 1.4V.

2. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

3. Enables on-chip refresh and address counters.
4. The minimum specifications are used only to

indicate cycle time at which proper operation
over the full temperature range (-40°C

£ +85°C

for T

for IT parts) is ensured.

5. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be
repeated any time the

REF refresh requirement is

exceeded.

6. AC characteristics assume

T = 1ns.

7. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

8. Outputs measured for 3.3V at 1.5V or 2.5V at 1.25V

with equivalent load:

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

tOH before going High-Z.

10. AC timing and I

tests have V

and V

, with

timing referenced to V

/2 = crossover point. If

the input transition time is longer than

T (MAX),

then the timing is referenced at V

(MAX) and V

(MIN) and no longer at the V

/2 crossover point.

11. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

12. I

specifications are tested after the device is

properly initialized.

13. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

14. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

15. Timing actually specified by

WR.

16. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

17. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

18. Address transitions average one transition every

two clocks.

19. CLK must be toggled a minimum of two times

during this period.

20. Based on

CK =8ns for -8 and

CK =10ns for -10.

21. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

£ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

£ 3ns.

22. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

23. Auto precharge mode only. The precharge timing

budget (

RP) begins at 7ns for -8 after the first

clock delay, after the last WRITE is executed.

24. Precharge mode only.
25. JEDEC and PC100 specify three clocks.
26.

AC for -8 at CL = 3 with no load is 7ns and is guar-

anteed by design.

27. Parameter guaranteed by design.
28. PC100 specifies a maximum of 4pF.
29. PC100 specifies a maximum of 5pF.
30. PC100 specifies a maximum of 6.5pF.

31. For -8, CL = 2 and

CK = 10ns; for -10, CL = 3 and

CK =10ns.

32. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

30pF

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Figure 33: Initialize And Load Mode Register

1,2

NOTE:

1. The two AUTO REFRESH commands at T9 and T19 may be applied before either LOAD MODE REGISTER (LMR) com-

mand.

2. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT =

ACTIVE command, RA = Row Address, BA = Bank Address

3. Optional refresh command.
4. The Load Mode Register for both MR/EMR and 2 Auto Refresh commands can be in any order. However, all must

occur prior to an Active command.

5. Device timing is -10 with 100 MHz clock.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

CKH

2.5

CKS

2.5

CMH

CMS

2.5

CK (3)

MRD

CK (2)

RFC

100

CK (1)

CKE

BA0, BA1

Load Extended

Mode Register

Load Mode

CKS

Power-up:
V

and

CLK stable

T = 100µs

CKH

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

DQML, DQMU

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

High-Z

A0-A9, A11

A10

ALL BANKS

CLK

COMMAND

LMR4

NOP

PRE3

LMR4

AR4

ACT4

CMS

CMH

BA0 = L,
BA1 = H

tAS tAH

BA0 = L,

BA1 = L

(

)

(

)

(

)

(

)

CODE CODE

tAS tAH

CODE CODE

(

)

(

)

(

)

(

)

PRE

ALL BANKS

tAS tAH

(

)

(

)

(

)

(

)

T19

T29

DON'T CARE

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

MRD

RFC

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

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Figure 34: Power-down Mode

NOTE:

1. Violating refresh requirements during power-down may result in a loss of data.

tCH

tCL

tCK

Two clock cycles

CKE

CLK

All banks idle, enter
power-down mode

Precharge all

active banks

Input buffers gated off while in

power-down mode

Exit power-down mode

(

)

(

)

(

)

(

)

DON'T CARE

tCKS

COMMAND

tCMH

tCMS

PRECHARGE

NOP

ACTIVE

NOP

(

)

(

)

(

)

(

)

All banks idle

BA0, BA1

BANK

BANK(S)

(

)

(

)

(

)

(

)

High-Z

tAH

tAS

tCKH

tCKS

DQML, DQMU

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

A0-A9, A11

ROW

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

A10

ROW

(

)

(

)

(

)

(

)

Tn + 1

Tn + 2

SYMBOL

-8

-10

UNITS

SYMBOL*

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

CKH

2.5

CKS

2.5

CMH

CMS

2.5

CK (3)

MRD

CK (2)

RFC

100

CK (1)

NOTE:

1. CAS latency indicated in parentheses.

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Figure 35: Clock Suspend Mode

NOTE:

1. For this example, the burst length = 2, the CAS latency = 3, and auto precharge is disabled.
2. x16:A9 and A11 = "Don't Care"

x32:A8, A9 and A11 = "Don't Care"

tCH

tCL

tCK

tAC

tLZ

DQMU, DQML

CLK

A0-A9, A11

BA0, BA1

A10

tOH

OUT

tAH

tAS

tAH

tAS

tAH

tAS

BANK

tDH

OUT

tAC

tHZ

OUT

m + 1

COMMAND

tCMH

tCMS

NOP

READ

WRITE

DON'T CARE

UNDEFINED

CKE

tCKS tCKH

BANK

COLUMN m

tDS

OUT

e + 1

NOP

tCKH

tCKS

tCMH

tCMS

COLUMN e2

SYMBOL

-8

-10

UNITS

SYMBOL*

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKH

AC (2)

CKS

2.5

AC (1)

CMH

CMS

2.5

HZ (3)

CK (3)

HZ (2)

CK (2)

HZ (1)

CK (1)

2.5

NOTE:

1. CAS latency indicated in parentheses.

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Figure 36: Auto Refresh Mode

NOTE:

1. Each AUTO REFRESH command performs a refresh cycle. Back-to-back commands are not required.

tCH

tCL

tCK

CKE

CLK

tRFC

(

)

(

)

(

)

(

)

(

)

(

)

tRP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

COMMAND

tCMH

tCMS

NOP

(

)

(

)

(

)

(

)

BANK

ACTIVE

AUTO

REFRESH

(

)

(

)

(

)

(

)

NOP

PRECHARGE

Precharge all

active banks

AUTO

REFRESH

tRFC

High-Z

BA0, BA1

BANK(S)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tAH

tAS

tCKH

tCKS

(

)

(

)

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

DQMU, DQML

A0-A9, A11

ROW

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

A10

ROW

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Tn + 1

To + 1

DON'T CARE

SYMBOL

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

CKH

2.5

CKS

2.5

CMH

CMS

2.5

CK (3)

MRD

CK (2)

RFC

100

CK (1)

NOTE:

1. CAS latency indicated in parentheses.

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Figure 37: Self Refresh Mode

NOTE:

1. No maximum time limit for Self Refresh.

RAS (MAX) only applies to non-Self Refresh mode.

XSR requires a minimum of two clocks regardless of frequency or timing.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

CKH

2.5

CKS

2.5

CMH

CMS

2.5

CK (3)

RAS

120,000

CK (2)

CK (1)

XSR

100

DON'T CARE

tCH

tCL

tCK

tRP

CKE

CLK

Enter self refresh mode

Precharge all

active banks

tXSR

CLK stable prior to exiting

self refresh mode

Exit self refresh mode

(Restart refresh time base)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

COMMAND

tCMH

tCMS

AUTO

REFRESH

PRECHARGE

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

BA0, BA1

BANK(S)

High-Z

tCKS

AUTO

REFRESH

> tRAS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tCKH

tCKS

DQMU, DQML

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

A0-A9, A11

(

)

(

)

(

)

(

)

ALL BANKS

SINGLE BANK

A10

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Tn + 1

To + 1

To + 2

(

)

(

)

(

)

(

)

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Figure 38: READ Without Auto Precharge1

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRE-

CHARGE.

2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD

CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

BANK(S)

BANK

ROW

BANK

tHZ

tOH

OUT

m+3

tAC

tOH

tAC

tOH

tAC

OUT

m+2

OUT

m+1

tCMH

tCMS

PRECHARGE

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

DISABLE AUTO PRECHARGE

SINGLE BANKS

DON'T CARE

UNDEFINED

COLUMN m

tCKH

tCKS

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

COMMAND

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 39: Read With Auto Precharge

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2.
2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD

CAS Latency

tRC

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

ROW

BANK

DON'T CARE

UNDEFINED

tHZ

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2

OUT

m + 1

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

NOP

tCKH

tCKS

COLUMN m 2

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 40: Single Read Without Auto Precharge

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRE-

CHARGE.

2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

3. PRECHARGE command not allowed or tRAS would be violated.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

ALL BANKS

tCH

tCL

tCK

tAC

tLZ

tRP

tRAS

tRCD

CAS Latency

tRC

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

BANK(S)

BANK

ROW

BANK

tHZ

tCMH

tCMS

NOP

PRECHARGE

ACTIVE

NOP

READ

ACTIVE

NOP

DISABLE AUTO PRECHARGE

SINGLE BANKS

DON'T CARE

UNDEFINED

COLUMN m

tCKH

tCKS

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

COMMAND

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 41: Single Read With Auto Precharge

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2, and the READ burst is followed by a "manual" PRE-

CHARGE.

2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

3. PRECHARGE command not allowed or tRAS would be violated.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

CAS Latency

tRC

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

BANK

ROW

BANK

DON'T CARE

UNDEFINED

tHZ

t OH

OUT

tAC

COMMAND

tCMH

tCMS

NOP3

READ

ACTIVE

NOP

NOP3

ACTIVE

NOP

tCKH

tCKS

COLUMN m2

NOP

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 42: Alternating Bank Read Accesses

NOTE:

1. For this example, the burst length = 4, the CAS latency = 2.
2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care".

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

RRD

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tAC

tLZ

DQMU, DQML

CLK

A0-A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

DON'T CARE

UNDEFINED

tOH

OUT

m + 3

tAC

tOH

tAC

tOH

tAC

OUT

m + 2

OUT

m + 1

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

READ

NOP

ACTIVE

tOH

OUT

tAC

READ

ENABLE AUTO PRECHARGE

ROW

ACTIVE

ROW

BANK 0

BANK 3

BANK 0

CKE

tCKH

tCKS

COLUMN m 2

COLUMN b 2

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0

CAS Latency - BANK 0

tRCD - BANK 3

CAS Latency - BANK 3

RC - BANK 0

RRD

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 43: Read Full-page Burst

NOTE:

1. For this example, the CAS latency = 2.
2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

Page left open; no

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

RRD

tCH

tCL

tCK

tAC

tLZ

tRCD

CAS Latency

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tOH

OUT

tCMH

tCMS

tAH

tAS

tAH

tAS

tAC

tOH

OUT

m+1

ROW

tHZ

tAC

tOH

OUT

m+1

tAC

tOH

OUT

m+2

tAC

tOH

OUT

m-1

tAC

tOH

OUT

Full-page burst does not self-terminate.

Can use BURST TERMINATE command.

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Full page completed

512 (x16) locations within same row

DON'T CARE

UNDEFINED

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

READ

NOP

BURST TERM

NOP

(

)

(

)

(

)

(

)

NOP

(

)

(

)

(

)

(

)

tAH

tAS

BANK

(

)

(

)

(

)

(

)

BANK

tCKH

tCKS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

COLUMN m 2

Tn + 1

Tn + 2

Tn + 3

Tn + 4

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 44: Read DQM Operation

NOTE:

1. For this example, the CAS latency = 2.
2. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

HZ (3)

2.5

HZ (2)

HZ (1)

CK (3)

2.5

CK (2)

RAS

120,000

CK (1)

100

CKH

RCD

CKS

2.5

CMH

RRD

tCH

tCL

tCK

tRCD

CAS Latency

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMS

ROW

BANK

ROW

BANK

tAC

OUT

tOH

OUT

m + 3

OUT

m + 2

tHZ

tCMH

COMMAND

NOP

ACTIVE

NOP

READ

NOP

tHZ

tAC

tOH

tAC

tOH

tAH

tAS

tCMS tCMH

tAH

tAS

tAH

tAS

tCKH

tCKS

ENABLE AUTO PRECHARGE

DISABLE AUTO PRECHARGE

COLUMN m 2

DON'T CARE

UNDEFINED

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 45: Write Without Auto Precharge

NOTE:

1. For this example, the burst length = 4, and the WRITE burst is followed by a "manual" PRECHARGE.
2. 15ns is required between <DIN m + 3> and the PRECHARGE command, regardless of frequency.
3. x16: A9 and A11 = "Don't Care"

x32: A8, A9,and A11 = "Don't Care"

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

t WR

tDH

tDS

m + 1

m + 2

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

NOP

PRECHARGE

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tDH

tDS

tDH

tDS

SINGLE BANK

tCKH

tCKS

COLUMN m 3

DON'T CARE

NOP

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 46: Write With Auto Precharge

NOTE:

1. For this example, the burst length = 4.
2. x16: A9 and A11 = "Don't Care"

x32: A8, A9,and A11 = "Don't Care"

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

tWR

tDH

tDS

m + 1

m + 2

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tDH

tDS

tDH

tDS

tCKH

tCKS

NOP

COLUMN m 2

DON'T CARE

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 47: Single Write Without Auto Precharge

NOTE:

1. For this example, the burst length = 1, and the WRITE burst is followed by a "manual" PRECHARGE.
2. 15ns is required between <DIN m> and the PRECHARGE command, regardless of frequency.
3. x16:A9 and A11 = "Don't Care"

x32:A8, A9,and A11 = "Don't Care"

4. PRECHARGE command not allowed else

RAS would be violated.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

DISABLE AUTO PRECHARGE

ALL BANKS

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK BANK

BANK

ROW

BANK

t WR

tDH

tDS

COMMAND

tCMH

tCMS

NOP

PRECHARGE

ACTIVE

NOP

WRITE

ACTIVE

NOP

tAH

tAS

tAH

tAS

SINGLE BANK

tCKH

tCKS

COLUMN m 3

DON'T CARE

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 48: Single Write With Auto Precharge

NOTE:

x32:A8, A9,and A11 = "Don't Care"

4. WRITE command not allowed else

RAS would be violated.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

ENABLE AUTO PRECHARGE

tCH

tCL

tCK

tRP

tRAS

tRCD

tRC

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

tWR

COMMAND

tCMH

tCMS

NOP3

NOP

ACTIVE

NOP3

WRITE

NOP

ACTIVE

tAH

tAS

tAH

tAS

tDH

tDS

tCKH

tCKS

NOP

COLUMN m 2

DON'T CARE

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 49: Alternating Bank Write Accesses

NOTE:

1. For this example, the burst length = 4.
2. x16: A9 and A11 = "Don't Care"

x32: A8, A9,and A11 = "Don't Care"

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

DON'T CARE

tCH

tCL

tCK

CLK

tDH

tDS

m + 1

m + 2

m + 3

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

NOP

ACTIVE

tDH

tDS

tDH

tDS

tDH

tDS

ACTIVE

WRITE

tDH

tDS

b + 1

b + 3

tDH

tDS

tDH

tDS

ENABLE AUTO PRECHARGE

DQMU, DQML

A0-A9, A11

BA0, BA1

A10

tCMH

tCMS

tAH

tAS

tAH

tAS

tAH

tAS

ROW

ENABLE AUTO PRECHARGE

ROW

BANK 0

BANK 1

BANK 0

BANK 1

CKE

tCKH

tCKS

b + 2

tDH

tDS

COLUMN b 2

COLUMN m 2

tRP - BANK 0

tRAS - BANK 0

tRCD - BANK 0

RCD - BANK 0

tWR - BANK 0

WR - BANK 1

tRCD - BANK 1

RC - BANK 0

RRD

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 50: Write Full-page Burst

NOTE:

1. x16: A9 and A11 = "Don't Care"

x32: A8, A9,and A11 = "Don't Care"

WR must be satisfied prior to PRECHARGE command.

3. Page left open; no

RP.

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

tCH

tCL

tCK

tRCD

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMS

tAH

tAS

tAH

tAS

ROW

Full-page burst does not
self-terminate. Can use
BURST TERMINATE
command to stop.

2, 3

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

Full page completed

DON'T CARE

COMMAND

tCMH

tCMS

NOP

ACTIVE

NOP

WRITE

BURST TERM

NOP

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

tDH

tDS

m + 1

m + 2

m + 3

tDH

tDS

tDH

tDS

tDH

tDS

m - 1

tDH

tDS

tAH

tAS

BANK

(

)

(

)

(

)

(

)

BANK

tCMH

tCKH

tCKS

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

(

)

512 (x16) locations within same row

COLUMN m 1

Tn + 1

Tn + 2

Tn + 3

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

Figure 51: Write DQM Operation

NOTE:

1. For this example, the burst length = 4.
2. x16: A9 and A11 = "Don't Care"

x32: A8, A9,and A11 = "Don't Care".

SYMBOL

NOTE:

1. CAS latency indicated in parentheses.

-8

-10

UNITS

SYMBOL

-8

-10

UNITS

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

AC (3)

CKS

2.5

AC (2)

CMH

AC (1)

CMS

2.5

RAS

120,000

100

CK (3)

RCD

CK (2)

CK (1)

WR (a)

1 CLK

+7ns

1 CLK+

5ns

CKH

WR (m)

DON'T CARE

tCH

tCL

tCK

tRCD

DQMU, DQML

CKE

CLK

A0-A9, A11

BA0, BA1

A10

tCMS

tAH

tAS

ROW

BANK

ROW

BANK

ENABLE AUTO PRECHARGE

m + 3

tDH

tDS

m + 2

tCMH

COMMAND

NOP

ACTIVE

NOP

WRITE

NOP

tCMS tCMH

tDH

tDS

tDH

tDS

tAH

tAS

tAH

tAS

DISABLE AUTO PRECHARGE

tCKH

tCKS

COLUMN m 2

128Mb: x16, x32

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128Mbx16x32.fm - Rev. G 3/03 EN

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Figure 53: 90-Ball FBGA (11mm x 13mm)

NOTE:

1. All dimensions in millimeters.
2. Recommended pad size for PCB is 0.33mm±0.025mm.

BALL

A1 ID

SUBSTRATE: PLASTIC LAMINATE

ENCAPSULATION MATERIAL: EPOXY NOVOLAC

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb.
Or 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm

SEATING PLANE

.850 ±.075

BALL A9

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION.

THE PRE-REFLOW DIAMETER IS Ø 0.40mm

.10

13.00 ± .10

.80
TYP

11.20

1.20 MAX

5.60 ±.05

6.50 ±.05

BALL

A1 ID

BALL A1

.80

TYP

5.50 ±.05

3.20 ±.05

11.00 ±.10

6.40

0.45

90X Ø

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT48V8M16LF

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT48V8M16LF