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Электронный компонент: MT4LC4M16N3TG-6

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1
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
FEATURES
Single +3.3V 0.3V power supply
Industry-standard x16 pinout, timing, functions,
and package
12 row, 10 column addresses (R6)
13 row, 9 column addresses (N3)
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are LVTTL-compatible
Extended Data-Out (EDO) PAGE MODE access
4,096-cycle CAS#-BEFORE-RAS# (CBR) REFRESH
distributed across 64ms
Optional self refresh (S) for low-power data
retention
OPTIONS
MARKING
Plastic Package
50-pin TSOP (400 mil)
TG
Timing
50ns access
-5
60ns access
-6
Refresh Rates
4K
R6
8K
N3
Standard Refresh
None
Self Refresh
S*
Operating Temperature Range
Commercial (0C to +70C)
None
Extended (-40C to +85C)
IT**
NOTE: 1. The "#" symbol indicates signal is active LOW.
*Contact factory for availability.
**Available only on MT4LC4M16R6 standard refresh device.
Part Number Example:
MT4LC4M16R6TG-5
PIN ASSIGNMENT (Top View)
DRAM
MT4LC4M16R6, MT4LC4M16N3
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/mti/msp/html/datasheet.html
V
CC
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
NC
V
CC
WE#
RAS#
NC
NC
NC
NC
A0
A1
A2
A3
A4
A5
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
V
SS
DQ15
DQ14
DQ13
DQ12
V
SS
DQ11
DQ10
DQ9
DQ8
NC
V
SS
CASL#
CASH#
OE#
NC
NC
NC/
A12
A11
A10
A9
A8
A7
A6
V
SS
KEY TIMING PARAMETERS
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-5
84ns
50ns
20ns
25ns
13ns
8ns
-6
104ns
60ns
25ns
30ns
15ns
10ns
50-Pin TSOP
4 MEG x 16 EDO DRAM PART NUMBERS
REFRESH
PART NUMBER
ADDRESSING PACKAGE REFRESH
MT4LC4M16R6TG-x
4K
400-TSOP
Standard
MT4LC4M16R6TG-x S
4K
400-TSOP
Self
MT4LC4M16N3TG-x
8K
400-TSOP
Standard
MT4LC4M16N3TG-x S
8K
400-TSOP
Self
x = speed
MT4LC4M16R6
MT4LC4M16N3
Configuration
4 Meg x 16
4 Meg x 16
Refresh
4K
8K
Row Address
4K (A0-A11)
8K (A0-A12)
Column Addressing
1K (A0-A9)
512 (A0-A8)
A12 for N3 version, NC for R6 version.
2
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
A0-
A11
RAS#
12
12
10
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
V
DD
V
SS
12
10
COLUMN-
ADDRESS
BUFFER(10)
ROW-
ADDRESS
BUFFERS (12)
4,096
1,024
COLUMN
DECODER
16
REFRESH
COUNTER
ROW SELECT
ROW
DECODER
4,096 x 1,024 x 16
MEMORY
ARRAY
COMPLEMENT
SELECT
1,024 x 16
4,096 x 16
NO. 2 CLOCK
GENERATOR
WE#
OE#
DQ0-
DQ15
16
16
DATA-OUT
BUFFER
CASL#
CAS#
CASH#
DATA-IN BUFFER
16
SENSE AMPLIFIERS
I/O GATING
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M16R6 (12 row addresses)
A0-
A12
RAS#
13
13
9
NO. 2 CLOCK
GENERATOR
REFRESH
CONTROLLER
NO. 1 CLOCK
GENERATOR
Vcc
Vss
13
WE#
9
COLUMN-
ADDRESS
BUFFER(9)
ROW-
ADDRESS
BUFFERS (13)
8192
512
COLUMN
DECODER
OE#
DQ0-
DQ15
16
16
16
16
REFRESH
COUNTER
ROW SELECT
ROW
DECODER
SENSE AMPLIFIERS
I/O GATING
DATA-OUT
BUFFER
8192 x 512 x 16
MEMORY
ARRAY
COMPLEMENT
SELECT
512 x 16
8192 x 16
CASL#
CAS#
CASH#
DATA-IN BUFFER
FUNCTIONAL BLOCK DIAGRAM
MT4LC4M16N3 (13 row addresses)
3
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
Figure 1
WORD and BYTE WRITE Example
STORED
DATA
1
1
0
1
1
1
1
1
RAS#
CASL#
WE#
X = NOT EFFECTIVE (DON'T CARE)
ADDRESS 1
ADDRESS 0
0
1
0
1
0
0
0
0
WORD WRITE
LOWER BYTE WRITE
CASH#
INPUT
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
INPUT
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
1
1
0
1
1
1
1
1
INPUT
DATA
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
STORED
DATA
0
0
1
0
0
0
0
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
1
1
1
1
UPPER BYTE
(DQ8-DQ15)
OF WORD
LOWER BYTE
(DQ0-DQ7)
OF WORD
GENERAL DESCRIPTION
The 4 Meg x 16 DRAM is a high-speed CMOS,
dynamic random-access memory device containing
67,108,864 bits and designed to operate from 3V to
3.6V. The device is functionally organized as 4,194,304
locations containing 16 bits each. The 4,194,304
memory locations are arranged in 4,096 rows by 1,024
columns on the MT4LC4M16R6 or 8,192 rows by 512
columns on the MT4LC4M16N3. During READ or WRITE
cycles, each location is uniquely addressed via the
address bits: 12 row-address bits (A0-A11) and 10
column-address bits (A0-A9) on the MT4LC4M16R6 or
13 row-address bits (A0-A12) and 9 column-address bits
(A0-A8) on the MT4LC4M16N3 version. In addition,
both byte and word accesses are supported via the two
CAS# pins (CASL# and CASH#).
The CAS# functionality and timing related to ad-
dress and control functions (e.g., latching column
addresses or selecting CBR REFRESH) is such that the
internal CAS# signal is determined by the first external
CAS# signal (CASL# or CASH#) to transition LOW and
the last to transition back HIGH. The CAS# functional-
ity and timing related to driving or latching data is such
that each CAS# signal independently controls the asso-
ciated eight DQ pins.
The row address is latched by the RAS# signal, then
the column address is latched by CAS#. This device
provides EDO-PAGE-MODE operation, allowing for fast
successive data operations (READ, WRITE or READ-
MODIFY-WRITE) within a given row.
The 4 Meg x 16 DRAM must be refreshed periodi-
cally in order to retain stored data.
DRAM ACCESS
Each location in the DRAM is uniquely addressable,
as mentioned in the General Description. Use of both
CAS# signals results in a word access via the 16 I/O pins
(DQ0-DQ15). Using only one of the two signals results
in a BYTE access cycle. CASL# transitioning LOW se-
lects an access cycle for the lower byte (DQ0-DQ7), and
CASH# transitioning LOW selects an access cycle for
4
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
the upper byte (DQ8-DQ15). General byte and word
access timing is shown in Figures 1 and 2.
A logic HIGH on WE# dictates read mode, while a
logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE or CAS# (CASL# or CASH#), whichever occurs
last. An EARLY WRITE occurs when WE is taken LOW
prior to either CAS# falling. A LATE WRITE or READ-
MODIFY-WRITE occurs when WE falls after CAS# (CASL#
or CASH#) is taken LOW. During EARLY WRITE cycles,
the data outputs (Q) will remain High-Z, regardless of
the state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the
data outputs prior to applying input data. If a LATE
WRITE or READ-MODIFY-WRITE is attempted while
keeping OE# LOW, no write will occur, and the data
outputs will drive read data from the accessed location.
Additionally, both bytes must always be of the same
mode of operation if both bytes are active. A CAS#
precharge must be satisfied prior to changing modes of
operation between the upper and lower bytes. For
example, an EARLY WRITE on one byte and a LATE
Figure 2
WORD and BYTE READ Example
STORED
DATA
1
1
0
1
1
1
1
1
RAS#
CASL#
WE#
Z = High-Z
ADDRESS 1
ADDRESS 0
0
1
0
1
0
0
0
0
WORD READ
LOWER BYTE READ
STORED
DATA
1
1
0
1
1
1
1
1
CASH#
OUTPUT
DATA
1
1
0
1
1
1
1
1
STORED
DATA
1
1
0
1
1
1
1
1
Z
Z
Z
Z
Z
Z
Z
Z
OUTPUT
DATA
1
1
0
1
1
1
1
1
OUTPUT
DATA
1
1
0
1
1
1
1
1
OUTPUT
DATA
1
1
0
1
1
1
1
1
STORED
DATA
1
1
0
1
1
1
1
1
UPPER BYTE
(DQ8-DQ15)
OF WORD
LOWER BYTE
(DQ0-DQ7)
OF WORD
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
WRITE on the other byte are not allowed during the
same cycle. However, an EARLY WRITE on one byte and
a LATE WRITE on the other byte, after a CAS# precharge
has been satisfied, are permissible.
EDO PAGE MODE
DRAM READ cycles have traditionally turned the
output buffers off (High-Z) with the rising edge of
CAS#. If CAS# went HIGH and OE# was LOW (active),
the output buffers would be disabled. The 64Mb EDO
DRAM offers an accelerated page mode cycle by elimi-
nating output disable from CAS# HIGH. This option is
called EDO, and it allows CAS# precharge time (
t
CP) to
occur without the output data going invalid (see READ
and EDO-PAGE-MODE READ waveforms).
EDO operates like any DRAM READ or FAST-PAGE-
MODE READ, except data is held valid after CAS# goes
HIGH, as long as RAS# and OE# are held LOW and WE#
is held HIGH. OE# can be brought LOW or HIGH while
CAS# and RAS# are LOW, and the DQs will transition
between valid data and High-Z. Using OE#, there are
DRAM ACCESS (continued)
5
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
Figure 3
OE# Control of DQs
V
V
IH
IL
CAS#
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
ROW
COLUMN (A)
COLUMN (B)
V
V
IH
IL
OE#
V
V
IOH
IOL
OPEN
DQ
tOD
VALID DATA (B)
VALID DATA (A)
COLUMN (C)
VALID DATA (A)
tOE
VALID DATA (C)
COLUMN (D)
VALID DATA (D)
tOD
tOEHC
tOD
tOEP
tOES
The DQs go back to
Low-Z if
t
OES is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEHC is met.
The DQs remain High-Z
until the next CAS# cycle
if
t
OEP is met.
Figure 4
WE# Control of DQs
V
V
IH
IL
CAS#
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
ROW
COLUMN (A)
DON'T CARE
UNDEFINED
V
V
IH
IL
WE#
V
V
IOH
IOL
OPEN
DQ
tWPZ
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
V
V
IH
IL
OE#
VALID DATA (B)
t
WHZ
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
t
WHZ
COLUMN (D)
VALID DATA (A)
COLUMN (B)
COLUMN (C)
INPUT DATA (C)
6
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
two methods to disable the outputs and keep them
disabled during the CAS# HIGH time. The first method
is to have OE# HIGH when CAS# transitions HIGH and
keep OE# HIGH for
t
OEHC thereafter. This will disable
the DQs, and they will remain disabled (regardless of
the state of OE# after that point) until CAS# falls again.
The second method is to have OE# LOW when CAS#
transitions HIGH and then bring OE# HIGH for a
minimum of
t
OEP anytime during the CAS# HIGH
period. This will disable the DQs, and they will remain
disabled (regardless of the state of OE# after that point)
until CAS# falls again (see Figure 3). During other
cycles, the outputs are disabled at
t
OFF time after RAS#
and CAS# are HIGH or at
t
WHZ after WE# transitions
LOW. The
t
OFF time is referenced from the rising edge
of RAS# or CAS#, whichever occurs last. WE# can also
perform the function of disabling the output drivers
under certain conditions, as shown in Figure 4.
EDO-PAGE-MODE operations are always initiated
with a row address strobed in by the RAS# signal,
followed by a column address strobed in by CAS#, just
like for single location accesses. However, subsequent
column locations within the row may then be accessed
at the page mode cycle time. This is accomplished by
cycling CAS# while holding RAS# LOW and entering
new column addresses with each CAS# cycle. Returning
RAS# HIGH terminates the EDO-PAGE-MODE
operation.
DRAM REFRESH
The supply voltage must be maintained at the speci-
fied levels, and the refresh requirements must be met in
order to retain stored data in the DRAM. The refresh
requirements are met by refreshing all rows in the
4 Meg x 16 DRAM array at least once every 64ms (8,192
rows for N3 or 4,096 rows for R6). The recommended
procedure is to execute 4,096 CBR REFRESH cycles,
either uniformly spaced or grouped in bursts, every
64ms. The MT4LC4M16N3 internally refreshes two
rows for each CBR cycle, whereas the MT4LC4M16R6
refreshes one row for every CBR cycle. For either device,
executing 4,096 CBR cycles will refresh the entire de-
vice. The CBR REFRESH will invoke the internal refresh
counter for automatic RAS# addressing. Alternatively,
RAS#-ONLY REFRESH capability is inherently provided.
However, with this method, only one row is refreshed
on each cycle. Thus, 8,192 RAS-only REFRESH cycles are
needed every 64ms on the MT4LC4M16N3 in order to
refresh the entire device. JEDEC strongly recommends
the use of CBR REFRESH for this device.
An optional self refresh mode is also available on the
"S" version. The self refresh feature is initiated by
performing a CBR Refresh cycle and holding RAS# low
for the specified
t
RASS. The "S" option allows the user
the choice of a fully static, low-power data retention
mode or a dynamic refresh mode at the extended
refresh period of 128ms, or 31.25s per cycle, when
using a distributed CBR refresh. This refresh rate can be
applied during normal operation, as well as during a
standby or battery backup mode.
The self refresh mode is terminated by driving RAS#
HIGH for a minimum time of
t
RPS. This delay allows for
the completion of any internal refresh cycles that may
be in process at the time of the RAS# LOW-to-HIGH
transition. If the DRAM controller uses a distributed
CBR refresh sequence, a burst refresh is not required
upon exiting self refresh, however, if the controller is
using RAS# only or burst CBR refresh then a burst
refresh using
t
RC (MIN) is required.
EDO PAGE MODE (continued)
7
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
CC
Relative to V
SS
................ -1V to +4.6V
Voltage on NC, Inputs or I/O Pins
Relative to V
SS
....................................... -1V to +4.6V
Operating Temperature, T
A
(ambient)
Commercial ......................................... 0C to +70C
Extended (IT) ................................. -40C to +85C**
Storage Temperature (plastic) ............ -55C to +150C
Power Dissipation ................................................... 1W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
**Available only on MT4LC4M16R6 standard refresh
device.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Note: 1) (V
CC
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
CC
3
3.6
V
INPUT HIGH VOLTAGE:
Valid Logic 1; All inputs, I/Os and any NC
V
IH
2
V
CC
+ 0.3
V
35
INPUT LOW VOLTAGE:
Valid Logic 0; All inputs, I/Os and any NC
V
IL
-0.3
0.8
V
35
INPUT LEAKAGE CURRENT:
Any input at V
IN
(0V
V
IN
V
CC
+ 0.3V);
I
I
-2
2
A
36
All other pins not under test = 0V
OUTPUT HIGH VOLTAGE:
I
OUT
= -2mA
V
OH
2.4
V
OUTPUT LOW VOLTAGE:
I
OUT
= 2mA
V
OL
0.4
V
OUTPUT LEAKAGE CURRENT:
Any output at V
OUT
(0V
V
OUT
V
CC
+ 0.3V);
I
OZ
-5
5
A
DQ is disabled and in High-Z state
8
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
Icc OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 2, 3, 5, 6) (V
CC
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL SPEED
4K
8K
UNITS NOTES
STANDBY CURRENT: TTL
I
CC
1
ALL
1
1
mA
(RAS# = CAS# = V
IH
)
STANDBY CURRENT: CMOS
(RAS# = CAS#
V
CC
- 0.2V; DQs may be left open;
I
CC
2
ALL
500
500
A
Other inputs: V
IN
V
CC
- 0.2V or V
IN
0.2V)
OPERATING CURRENT: Random READ/WRITE
I
CC
3
-5
150
115
mA
26
Average power supply current
-6
165
130
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
OPERATING CURRENT: EDO PAGE MODE
I
CC
4
-5
120
120
mA
26
Average power supply current
-6
125
125
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
REFRESH CURRENT: RAS#-ONLY
I
CC
5
-5
150
115
mA
22
Average power supply current
-6
165
130
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
REFRESH CURRENT: CBR
I
CC
6
-5
150
150
mA
4, 7,
Average power supply current
-6
165
165
23
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
REFRESH CURRENT: Extended ("S" version only)
I
CC
7
ALL
400
400
A
4, 7,
Average power supply current: CAS# = 0.2V or CBR cycling;
23, 37
RAS# =
t
RAS (MIN); WE# = V
CC
- 0.2V; A0-A10, OE# and
D
IN
= V
CC
- 0.2V or 0.2V (D
IN
may be left open);
t
RC = 125s
REFRESH CURRENT: Self ("S" version only)
I
CC
8
ALL
350
350
A
4, 7,
Average power supply current: CBR with RAS#
t
RASS (MIN)
37
and CAS# held LOW; WE# = V
CC
- 0.2V; A0-A10, OE# and
D
IN
= V
CC
- 0.2V or 0.2V (D
IN
may be left open)
MAX
9
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (V
CC
= +3.3V 0.3V)
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
t
AA
25
30
ns
Column-address setup to CAS# precharge
t
ACH
12
15
ns
Column-address hold time (referenced to RAS#)
t
AR
38
45
ns
Column-address setup time
t
ASC
0
0
ns
28
Row-address setup time
t
ASR
0
0
ns
28
Column address to WE# delay time
t
AWD
42
49
ns
18
Access time from CAS#
t
CAC
13
15
ns
29
Column-address hold time
t
CAH
8
10
ns
28
CAS# pulse width
t
CAS
8
10,000
10
10,000
ns
30, 32
CAS# LOW to "Don't Care" during Self Refresh
t
CHD
15
15
ns
CAS# hold time (CBR Refresh)
t
CHR
8
10
ns
4, 31
Last CAS# going LOW to first CAS# to return HIGH
t
CLCH
5
5
ns
31
CAS# to output in Low-Z
t
CLZ
0
0
ns
29
Data output hold after CAS# LOW
t
COH
3
3
ns
CAS# precharge time
t
CP
8
10
ns
13, 33
Access time from CAS# precharge
t
CPA
28
35
ns
29
CAS# to RAS# precharge time
t
CRP
5
5
ns
31
CAS# hold time
t
CSH
38
45
ns
31
CAS# setup time (CBR Refresh)
t
CSR
5
5
ns
4, 28
CAS# to WE# delay time
t
CWD
28
35
ns
18, 28
WRITE command to CAS# lead time
t
CWL
8
10
ns
31
Data-in hold time
t
DH
8
10
ns
19, 29
Data-in setup time
t
DS
0
0
ns
19, 29
Output disable
t
OD
0
12
0
15
ns
24, 25
Output enable time
t
OE
12
15
ns
20
OE# hold time from WE# during
t
OEH
8
10
ns
25
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
t
OEHC
5
10
ns
OE# HIGH pulse width
t
OEP
5
5
ns
OE# LOW to CAS# HIGH setup time
t
OES
4
5
ns
Output buffer turn-off delay
t
OFF
0
12
0
15
ns
17, 24, 29
OE# setup prior to RAS# during HIDDEN REFRESH cycle
t
ORD
0
0
ns
CAPACITANCE
(Note: 2)
PARAMETER
SYMBOL
MAX
UNITS
Input Capacitance: Address pins
C
I
1
5
pF
Input Capacitance: RAS#, CAS#, WE#, OE#
C
I
2
7
pF
Input/Output Capacitance: DQ
C
IO
7
pF
10
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12) (V
CC
= +3.3V 0.3V)
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
EDO-PAGE-MODE READ or WRITE cycle time
t
PC
20
25
ns
34
EDO-PAGE-MODE READ-WRITE cycle time
t
PRWC
47
56
ns
34
Access time from RAS#
t
RAC
50
60
ns
RAS# to column-address delay time
t
RAD
9
12
ns
15
Row address hold time
t
RAH
7
10
ns
RAS# pulse width
t
RAS
50
10,000
60
10,000
ns
RAS# pulse width (EDO PAGE MODE)
t
RASP
50
125,000
60
125,000
ns
RAS# pulse width during Self Refresh
t
RASS
100
100
s
Random READ or WRITE cycle time
t
RC
84
104
ns
RAS# to CAS# delay time
t
RCD
11
14
ns
14, 28
READ command hold time (referenced to CAS#)
t
RCH
0
0
ns
16, 30
READ command setup time
t
RCS
0
0
ns
28
Refresh period
t
REF
64
64
ms
22, 23
Refresh period ("S" version)
t
REF
128
128
ms
23
RAS# precharge time
t
RP
30
40
ns
RAS# to CAS# precharge time
t
RPC
5
5
ns
RAS# precharge time exiting Self Refresh
t
RPS
90
105
ns
READ command hold time (referenced to RAS#)
t
RRH
0
0
ns
16
RAS# hold time
t
RSH
13
15
ns
35
READ-WRITE cycle time
t
RWC
116
140
ns
RAS# to WE# delay time
t
RWD
67
79
ns
18
WRITE command to RAS# lead time
t
RWL
13
15
ns
Transition time (rise or fall)
t
T
2
50
2
50
ns
WRITE command hold time
t
WCH
8
10
ns
35
WRITE command hold time (referenced to RAS#)
t
WCR
38
45
ns
WE# command setup time
t
WCS
0
0
ns
18, 28
WE# to outputs in High-Z
t
WHZ
12
15
ns
WRITE command pulse width
t
WP
5
5
ns
WE# pulse widths to disable outputs
t
WPZ
10
10
ns
WE# hold time (CBR Refresh)
t
WRH
8
10
ns
WE# setup time (CBR Refresh)
t
WRP
8
10
ns
11
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
CC
= +3.3V; f = 1
MHz; T
A
= 25C.
3.
I
CC
is dependent on output loading and cycle
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation
over the full temperature range is ensured.
6.
An initial pause of 100s is required after power-
up, followed by eight RAS# refresh cycles (RAS#-
ONLY or CBR with WE# HIGH), before proper
device operation is ensured. The eight RAS# cycle
wake-ups should be repeated any time the
t
REF
refresh requirement is exceeded.
7.
AC characteristics assume
t
T = 2.5ns.
8.
V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition
times are measured between V
IH
and V
IL
(or
between V
IL
and V
IH
).
9.
In addition to meeting the transition rate
specification, all input signals must transit
between V
IH
and V
IL
(or between V
IL
and V
IH
) in a
monotonic manner.
10. If CAS# and RAS# = V
IH
, data output is High-Z.
11. If CAS# = V
IL
, data output may contain data from
the last valid READ cycle.
12. Measured with a load equivalent to two TTL
gates and 100pF; and V
OL
= 0.8V and V
OH
= 2V.
13. If CAS# is LOW at the falling edge of RAS#,
output data will be maintained from the previous
cycle. To initiate a new cycle and clear the data-
out buffer, CAS# must be pulsed HIGH for
t
CP.
14. The
t
RCD (MAX) limit is no longer specified.
t
RCD (MAX) was specified as a reference point
only. If
t
RCD was greater than the specified
t
RCD
(MAX) limit, then access time was controlled
exclusively by
t
CAC (
t
RAC [MIN] no longer
applied). With or without the
t
RCD limit,
t
AA
and
t
CAC must always be met.
15. The
t
RAD (MAX) limit is no longer specified.
t
RAD (MAX) was specified as a reference point
only. If
t
RAD was greater than the specified
t
RAD
(MAX) limit, then access time was controlled
exclusively by
t
AA (
t
RAC and
t
CAC no longer
applied). With or without the
t
RAD (MAX) limit,
t
AA,
t
RAC, and
t
CAC must always be met.
16. Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
17.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
18.
t
WCS,
t
RWD,
t
AWD,
and
t
CWD
are
not
restrictive
operating
parameters.
t
WCS
applies
to
EARLY
WRITE
cycles.
If
t
WCS
>
t
WCS
(MIN),
the
cycle
is
an
EARLY
WRITE
cycle
and
the
data
output
will
remain
an
open
circuit
throughout
the
entire
cycle.
t
RWD,
t
AWD,
and
t
CWD
define
READ-
MODIFY-WRITE
cycles.
Meeting
these
limits
allows
for
reading
and
disabling
output
data
and
then
applying
input
data.
OE#
held
HIGH
and
WE#
taken
LOW
after
CAS#
goes
LOW
results
in
a
LATE
WRITE
(OE#-controlled)
cycle.
t
WCS,
t
RWD,
t
CWD,
and
t
AWD
are
not
applicable
in
a
LATE
WRITE
cycle.
19. These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
20. If OE# is tied permanently LOW, LATE WRITE, or
READ-MODIFY-WRITE operations are not
possible.
21. A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# is LOW and
OE# is HIGH.
22. RAS#-ONLY REFRESH requires that all 8,192 rows
of the MT4LC4M16N3 or all 4,096 rows of the
MT4LC4M16R6 be refreshed at least once every
64ms.
23. CBR REFRESH for either device requires that at
least 4,096 cycles be completed every 64ms.
24. The DQs go High-Z during READ cycles once
t
OD
or
t
OFF occur. If CAS# stays LOW while OE# is
brought HIGH, the DQs will go High-Z. If OE# is
brought back LOW (CAS# still LOW), the DQs
will provide the previously read data.
25. LATE WRITE and READ-MODIFY-WRITE cycles
must have both
t
OD and
t
OEH met (OE# HIGH
during WRITE cycle) in order to ensure that the
output buffers will be open during the WRITE
cycle. If OE# is taken back LOW while CAS#
remains LOW, the DQs will remain open.
26. Column address changed once each cycle.
27. The first CASx# edge to transition LOW.
12
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
NOTES (continued)
28. Output parameter (DQx) is referenced to
corresponding CAS# input; DQ0-DQ7 by CASL#
and DQ8-DQ15 by CASH#.
29. Each CASx# must meet minimum pulse width.
30. The last CASx# edge to transition HIGH.
31. Last falling CASx# edge to first rising CASx#
edge.
32. Last rising CASx# edge to first falling CASx#
edge.
33. Last rising CASx# edge to next cycle's last rising
CASx# edge.
34. Last CASx# to go LOW.
35. V
IH
overshoot: V
IH
(MAX) = V
CC
+ 2V for a pulse
width
3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
3ns, and the pulse width cannot be greater than
one third of the cycle rate.
36. NC pins are assumed to be left floating and are
not tested for leakage.
37. Self refresh and extended refresh for either device
requires that at least 4,096 cycles be completed
every 128ms.
13
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLCH
5
5
ns
t
CLZ
0
0
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
OD
0
12
0
15
ns
READ CYCLE
NOTE: 1.
t
OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
tRRH
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tOFF
tRCH
ROW
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tRSH
tCSH
tRP
tRC
tRAS
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
tOD
tOE
OE#
V
V
IH
IL
COLUMN
CAS#
WE#
NOTE 1
tACH
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
OFF
0
12
0
15
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC
84
104
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
14
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
EARLY WRITE CYCLE
DON'T CARE
UNDEFINED
V
V
IH
IL
VALID DATA
ROW
COLUMN
ROW
tDS
tWP
tWCH
tWCS
tWCR
tRWL
tCWL
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCAS
tRSH
tCSH
tRCD
tCRP
tRAS
tRC
tRP
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
tDH
WE#
CAS#
tACH
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC
84
104
ns
t
RCD
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR
38
45
ns
t
WCS
0
0
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLCH
5
5
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
15
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
VALID D
OUT
VALID D
IN
ROW
COLUMN
ROW
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OPEN
OPEN
tOE
tOD
tCAC
tRAC
tAA
tCLZ
tDS
tDH
tAWD
tWP
tRWL
tCWL
tCWD
tRWD
tRCS
tASC
tCAH
tAR
tASR
tRAD
tCRP
tRCD
tCAS
tRSH
tCSH
tRAS
tRWC
tRP
tRAH
OE#
tOEH
WE#
tACH
CAS#
DON' T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
DS
0
0
ns
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
OEH
8
10
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RCD
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWC
116
140
ns
t
RWD
67
79
ns
t
RWL
13
15
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLCH
5
5
ns
t
CLZ
0
0
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWD
28
35
ns
t
CWL
8
10
ns
t
DH
8
10
ns
16
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLCH
5
5
ns
t
CLZ
0
0
ns
t
COH
3
3
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
OD
0
12
0
15
ns
EDO-PAGE-MODE READ CYCLE
VALID
DATA
VALID
DATA
VALID
DATA
COLUMN
COLUMN
COLUMN
ROW
ROW
DON'T CARE
UNDEFINED
tOD
tCAH
tASC
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tCAC
tCPA
tAA
tCAC
tRAC
tAA
tCLZ
tOE
tOD
tOE
tOD
OPEN
OPEN
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
RAS#
OE#
tCAS
tCAS
CAS#
WE#
tCOH
tOEP
tOEHC
tOES
tOES
tACH
tACH
tACH
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
OEHC
5
10
ns
t
OEP
5
5
ns
t
OES
4
5
ns
t
OFF
0
12
0
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
17
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLCH
5
5
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWL
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
EDO-PAGE-MODE EARLY WRITE CYCLE
tDS
tDH
tDS
tDH
tDS
tDH
tWCR
VALID DATA
VALID DATA
VALID DATA
tRWL
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tRAD
tACH
tACH
tACH
tAR
COLUMN
COLUMN
COLUMN
ROW
ROW
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
t RP
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
RAS#
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
PC
20
25
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR
38
45
ns
t
WCS
0
0
ns
t
WP
5
5
ns
18
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
DON'T CARE
UNDEFINED
t
t
OD
tOE
tOD
tOE
tOD
tOE
OPEN
D OUT
VALID
D IN
VALID
D OUT
VALID
D IN
VALID
D OUT
VALID
D IN
VALID
OPEN
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCLZ
tCAC
tRAC
tWP
tCWL
tRWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tRCS
tRWD
tASR
tRAH
tASC
tRAD
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tRSH
tCP
tRP
tRASP
tCP
tRCD
tCSH
tPC
tCRP
ROW
COLUMN
COLUMN
COLUMN
ROW
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
tPRWC
OEH
tCAS
tCAS
tCAS
WE#
CASL#/CASH#
NOTE 1
NOTE: 1.
t
PC is for LATE WRITE cycles only.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
DS
0
0
ns
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
OEH
8
10
ns
t
PC
20
25
ns
t
PRWC
47
56
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWD
67
79
ns
t
RWL
13
15
ns
t
WP
5
5
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLCH
5
5
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
CWD
28
35
ns
t
CWL
8
10
ns
t
DH
8
10
ns
19
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
V
V
IH
IL
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
tRASP
tRP
ROW
COLUMN (A)
COLUMN (N)
ROW
V
V
IH
IL
OE#
V
V
IOH
IOL
tCRP
tCSH
tCAS
tRCD
tASR
tRAH
tRAD
tASC
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tRSH
VALID DATA
IN
tRCS
tRCH
tWCS
tOE
VALID
DATA (B)
VALID DATA (A)
tWHZ
tCAC
tCPA
tAA
tCAC
tAA
OPEN
DQ
tPC
RAC
t
tCOH
tWCH
tDS
tDH
tPC
COLUMN (B)
tACH
CAS#
tCAS
tCAS
tCP
tCP
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
WCH
8
10
ns
t
WCS
0
0
ns
t
WHZ
12
15
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
COH
3
3
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
DH
8
10
ns
t
DS
0
0
ns
20
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
READ CYCLE
(with WE#-controlled disable)
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tRCH
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tCSH
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
tOD
tOE
OE#
V
V
IH
IL
COLUMN
WE#
tWHZ
tWPZ
tCP
tASC
tRCS
COLUMN
tCLZ
CASL#/CASH#
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
WHZ
12
15
ns
t
WPZ
10
10
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
21
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
RAS#-ONLY REFRESH CYCLE
(OE# and WE# = DON'T CARE)
ROW
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
tRC
tRAS
tRP
tCRP
tASR
tRAH
ROW
OPEN
Q
V
V
OH
OL
tRPC
CASL#/CASH#
CBR REFRESH CYCLE
(Addresses and OE# = DON'T CARE)
tRP
V
V
IH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
V
IH
IL
CASL#/CASH#
DQ
tRP
tRAS
tRPC
tCSR
tRPC
tCHR
tCP
V
V
IH
IL
tWRP
tWRH
tWRP
tWRH
WE#
DON'T CARE
UNDEFINED
V
V
OH
OL
NOTE 1
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RAS
50
10,000
60
10,000
ns
t
RC
84
104
ns
t
RP
30
40
ns
t
RPC
5
5
ns
t
WRH
8
10
ns
t
WRP
8
10
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ASR
0
0
ns
t
CHR
8
10
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSR
5
5
ns
t
RAH
7
10
ns
NOTE: 1. End of first CBR REFRESH cycle.
22
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
HIDDEN REFRESH CYCLE
1
(WE# = HIGH; OE# = LOW)
DON'T CARE
UNDEFINED
tCLZ
tOFF
OPEN
VALID DATA
OPEN
COLUMN
ROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP
tRCD
tRSH
tRAS
tRC
tRP
tCHR
tRAS
DQx
V
V
IOH
IOL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
RAS#
V
V
IH
IL
tOE
tOD
OE#
tORD
CASL#/CASH#
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
OFF
0
12
0
15
ns
t
ORD
0
0
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
7
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RCD
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CHR
8
10
ns
t
CLZ
0
0
ns
t
CRP
5
5
ns
t
OD
0
12
0
15
ns
NOTE: 1. A HIDDEN REFRESH may also be performed after a WRITE cycle. In this case, WE# is LOW and OE# is HIGH.
23
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
SELF REFRESH CYCLE
(Addresses and OE# = DON'T CARE)
V
V
IH
IL
RAS#
tRASS
OPEN
V
V
IH
IL
V
V
OH
OL
DQ
tRPC
tCHD
tRPS
tRPC
tRP
tCP
CASL#/
CASH#
tWRH
tWRP
WE#
V
V
IH
IL
tWRH
tWRP
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
(
)
NOTE 1
tCSR
DON'T CARE
UNDEFINED
tCP
NOTE 2
(
)
(
)
(
)
(
)
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
CHD
15
15
ns
t
CLCH
5
5
ns
t
CP
8
10
ns
t
CSR
5
5
ns
t
RASS
100
100
ns
t
RP
30
40
ns
t
RPC
5
5
ns
t
RPS
90
105
ns
t
WRH
8
10
ns
t
WRP
8
10
ns
NOTE: 1. Once
t
RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
2. Once
t
RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
24
4 Meg x 16 EDO DRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
D29_2.p65 Rev. 5/00
2000, Micron Technology, Inc.
4 MEG x 16
EDO DRAM
50-PIN PLASTIC TSOP (400 mil)
.10
10.21
10.11
.45
.30
.80
TYP
50
1
25
SEE DETAIL A
1.2
MAX
.25
DETAIL A
GAGE PLANE
PIN #1 ID
.20
.25
.18
.13
21.04
20.88
11.86
11.66
.80
TYP
.60
.40
.88
TYP
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is .25mm per side.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.