09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

4MB, 8MB (x32)

SDRAM DIMMs

SYNCHRONOUS
DRAM MODULE

MT2LSDT132U - 4MB
MT4LSDT232UD - 8MB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· JEDEC pinout in a 100-pin, dual in-line memory

module (DIMM)

· 4MB (1 Meg x32) and 8MB (2 Meg x32)
· Utilizes 100 MHz and 125 MHz SDRAM components
· Single +3.3V power supply
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal SDRAM device pipelined operation,

compatible with 2n prefetch architecture, allows
column address changes every clock cycle

· Internal SDRAM device banks for hiding row

access/precharge

· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge and Auto Refresh Modes

64ms, 2,048-cycle refresh (31.25µs refresh interval for
power saving); or 64ms, 2,048-cycle refresh (15.625µs
refresh interval)

· LVTTL-compatible inputs and outputs
· Serial Presence-Detect (SPD

)

Figure 1: 100-Pin DIMM (MO161)

Table 1:

Timing Parameters

CL = CAS (READ) latency

MODULE

MARKING

CLOCK

FREQUENCY

ACCESS TIME

SETUP

TIME

HOLD

TIME

CL = 2 CL = 3

-8

125 MHz

6ns

2ns

1ns

-10

100 MHz

10ns

2ns

1ns

OPTIONS

MARKING

· Package

100-pin DIMM (Gold)

100-pin DIMM (Lead-free)

· Frequency / CAS Latency

125 MHz (8ns) / CL = 3

-8

100 MHz (10ns) / CL = 2

-10

Table 2:

Part Numbers

PART NUMBER

CONFIGURATION

SYSTEM BUS

SPEED

MT2LSDT132UG-8_

1 Meg x32

125 MHz

MT2LSDT132UY-8_

1 Meg x32

125 MHz

MT2LSDT132UG-10_

1 Meg x32

100 MHz

MT2LSDT132UY-10_

1 Meg x32

100 MHz

MT4LSDT232UDG-8_

2 Meg x32

125 MHz

MT4LSDT232UDY-8_

2 Meg x32

125 MHz

MT4LSDT232UDG-10_

2 Meg x32

100 MHz

MT4LSDT232UDY-10_

2 Meg x32

100 MHz

Table 3:

Address Table

MODULE DENSITY

4MB

8MB

Refresh Count

2K or 4K

Device Banks

2 (BA0)

Device Configuration

1 Meg x 16

Device Row Addressing

2K (A0 - A10)

Device Column Addressing

256 (A0 - A7)

Module Ranks

1 (S0#, S2#)

2 (S0#, S2#; S1#, S3#)

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Figure 2: Pin Locations (100-Pin DIMM)

Table 4:

Pin Assignment Front
(100-Pin DIMM)

PIN SYMBOL PIN

SYMBOL

PIN SYMBOL

Vss

DQ16

DQ0

CKE0

DQ17

DQ1

WE#

DQ18

DQ2

S0#

DQ19

DQ3

S2#

A10

DQ20

DQ4

DQ21

DQ5

DQ22

DQ6

DQ23

DQ7

Vss

DQMB0

RFU

Vss

SDA

Vss

RFU

DQMB2

SCL

CK0

Table 5:

Pin Assignment Back
(100-Pin DIMM)

PIN SYMBOL PIN

SYMBOL

PIN SYMBOL

Vss

DQ24

DQ8

CKE1

DQ25

DQ9

DQ26

DQ10

S1#

DQ27

DQ11

S3#

BA0

DQ28

DQ12

DQ29

DQ13

DQ30

DQ14

DQ31

DQ15

RAS#

Vss

DQMB1

CAS#

Vss

SA0

Vss

RFU

DQMB3

SA1

CK1

100

SA2

PIN 50

PIN 23

PIN 1

PIN100

PIN 51

PIN 73

Front View

Back View

Indicates a V

(Not populated for the 4MB module)

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Table 6:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to the Pin Assignment Tables on page 2 for more information.

PIN NUMBER

SYMBOL

TYPE

DESCRIPTION

28, 72, 73

WE#, RAS#,

CAS#

Input

Command Inputs: RAS#, CAS# and WE# (along with S#) define the command
being entered.

25, 75

CK0, CK1

Input

Clock: CK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge SDRAM input signals are sampled on the positive edge
of CK. CK also increments the internal burst counter and controls the output
registers.

27, 77

CKE0, CKE1

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
Deactivating the clock provides POWER-DOWN and SELF REFRESH operation
(all banks idle), or CLOCK SUSPEND operation (burst access in progress). CKE
is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CK, are disabled during power-down and self
refresh modes, providing low standby power.

29, 30, 79, 80

S0#-S3#

Input

Chip Select: S# enables (registered LOW) or disables (registered HIGH) the
the command decoder. All commands are masked when S# is registered
HIGH. S# is considered part of the command code.

11, 37, 61, 87

DQMB0-

DQMB3

Input

Input/Output Mask: DQMB is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQMB is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-
Z state (after a two-clock latency) when DQMB is sampled HIGH during a
READ cycle.

BA0

Input

Bank Address: BA0 defines to which bank the ACTIVE, READ, WRITE or
PRECHARGE command is being applied.

13, 14, 15, 16, 17,
18, 63, 64, 65, 66,

A0-A10

Input

Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank.
A10 is sampled during a PRECHARGE command to determines whether the
PRECHARGE applies to one device bank (A10 LOW, device bank selected by
BA0) or all device banks (A10 HIGH). The address inputs also provide the op-
code during a LOAD MODE REGISTER command.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.

98-100

SA0-SA2

Input

Presence-Detect Address Inputs: These pins are used to configure the
presence-detect device.

2-5, 7-10, 38-41,

43-46, 52-55, 57-

60, 88-91, 93-96

DQ0-DQ31

Input/

Output

Data I/Os: Data bus.

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of the
module.

6, 21, 31, 42, 50,

56, 71, 81, 92

Supply Power Supply: +3.3V ±0.3V.

1, 12, 26, 36, 47,

51, 62, 76, 86, 97

Supply Ground.

23, 24, 74

RFU

Reserved for Future Use: These pins should be left unconnected.

19, 20, 22, 32-35,

69, 70, 78, 82-85

Not connected.

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Figure 3: Functional Block Diagram ( MT2LSDT132U)

SPD

SCL

SDA

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQMB0

S0#

RAS#

CAS#

CKE0

WE#

RAS#: SDRAMs

CAS#: SDRAMs

CKE: SDRAMs

WE#: SDRAMs

A0-A10: SDRAMs

BA0: SDRAMs

A0-A10

BA0

SDRAMs

CK0

U1
U2

6.8pF

10pF

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML CS#

DQMB1

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQMH

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQMB2

S2#

DQML CS#

DQMB3

CK1

SA0 SA1 SA2

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as refer-

enced in the Module Part Numbering Guide at

www.micron.com/numberguide

SDRAMs = MT48LC1M16A1TG

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Figure 4: Functional Block Diagram (MT4LSDT232UD)

SPD

SCL

SDA

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQMB0

S0#

RAS#

CAS#

CKE0

CKE1

WE#

RAS#: SDRAMs

CAS#: SDRAMs

CKE: SDRAMs U1-U2

CKE: SDRAMs U3-U4

WE#: SDRAMs

A0-A10: SDRAMs

BA0: SDRAMs

A0-A10

BA0

SDRAMs

CK0

U1
U2

6.8pF

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML CS#

DQMB1

DQMH

DQML CS#

S1#

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQMH

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQMB2

S2#

DQML CS#

DQMB3

DQMH

DQML CS#

S3#

CK1

U3
U4

SA0 SA1 SA2

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

SDRAMs = MT48LC1M16A1TG

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed grades as

referenced in the Module Part Numbering Guide at

www.micron.com/

numberguide

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

General Description

The Micron MT2LSDT132U and MT4LSDT232UD

are high-speed CMOS, dynamic random-access, 4MB
and 8MB memory modules organized in a x32 configu-
ration. These modules use SDRAM devices which are
internally configured as dual-bank DRAMs with a syn-
chronous interface (all signals are registered on the
positive edge of the clock signal CK).

Read and write accesses to these SDRAM modules

are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0 selects the device bank, A0A10 for
device row). The address bits registered coincident
with the READ or WRITE command (BA0, A0A7) are
used to select the starting device bank and column
location for the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence. These modules use an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing the other device bank will hide
the PRECHARGE cycles and provide seamless, high-
speed, random access operation.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs, outputs, and clocks are LVTTL-compatible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between internal banks in order to hide
precharge time, and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 16Mb SDRAM component data sheet.

Serial Presence-Detect Operation

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device

contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I

C bus

using the DIMM's SCL (clock) and SDA (data) signals.
Write protect (WP) is tied to ground on the module,
permanently disabling hardware write protect.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V

and V

Q (simulta-

neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Figure 5, Mode Register Definition
Diagram, on page 7. The mode register is programmed
via the LOAD MODE REGISTER command and will
retain the stored information until it is programmed
again or the device loses power.

Mode register bits M0M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4M6 specify the CAS latency, M7 and M8

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Figure 5, Mode Register Definition Diagram.
The burst length determines the maximum number of
column locations that can be accessed for a given
READ or WRITE command. Burst lengths of 1, 2, 4, or 8
locations are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in Table 7,
Burst Definition Table, on page 8. The block is
uniquely selected by A1A7 when the burst length is
set to two; by A2A7 when the burst length is set to
four; and by A3A7 when the burst length is set to
eight. The remaining (least significant) address bit(s) is
(are) used to select the starting location within the
block. Full-page bursts wrap within the page if the
boundary is reached, as shown in Table 7, Burst Defini-
tion Table, on page 8.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 7, Burst
Definition Table, on page 8.

Figure 5: Mode Register Definition

Diagram

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleave

CAS Latency

Reserved

0 0 0

0 0 1

0 1 0

0 1 1

1 0 0

1 0 1

1 1 0

1 1 1

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6 - M0

Op Mode

A10

Reserved* WB

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M11, M10 = 0, 0

to ensure compatibility

with future devices.

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

NOTE:

1. For a burst length of two, A1A7 select the block-

of-two burst; A0 selects the starting column within
the block.

2. For a burst length of four, A2A7 select the block-

of-four burst; A0A1 select the starting column
within the block.

3. For a burst length of eight, A3A7 select the block-

of-eight burst; A0A2 select the starting column
within the block.

4. For a full-page burst, the full row is selected and

A0A7 select the starting column.

5. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

6. For a burst length of one, A0A7 select the unique

column to be accessed, and mode register bit M3 is
ignored.

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in Figure 6, CAS Latency
Diagram. Table 8, CAS Latency Table, on page 9, indi-
cates the operating frequencies at which each CAS
latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Figure 6: CAS Latency Diagram

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.

TABLE 7:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WTHIN A

BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page
(256)

n = A0-A7

(location 0-

255)

Cn, Cn + 1,

Cn + 2, Cn + 3, Cn

+ 4. . . Cn - 1,

Cn . . .

Not supported

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Commands

Table 9, Truth Table Commands and DQMB Oper-

ation, provides a general reference of available com-
mands. For a more detailed description of commands

and operations, refer to the 16Mb SDRAM component
data sheets.

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0A10 define the op-code written to the Mode Register.
3. A0A10 provide row address and BA0 determine which bank is made active.
4. A0A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW dis-

ables the auto precharge feature; BA0 determine which bank is being read from or written to.

5. A10 LOW: BA0 determine which bank is being precharged. A10 HIGH: both banks are precharged and BA0 is "Don't

Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQ during WRITE (zero-clock delay) and READ (two-clock delay).

Table 9:

Truth Table Commands and DQMB Operation

Note: 1

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

DQMB

ADDR

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/

Row

READ (Select bank and column, and start
READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start
WRITE burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or
banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self
refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature

(ambient) . . . . . . . . . . . . . . . . . . . . . 0

°C to +70°C

Storage Temperature (plastic) . . . . . .-55

°C to +125°C

Power Dissipation

Single Rank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2W
Dual Rank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W

Table 10: DC Electrical Characteristics and Operating Conditions (4MB)

Note: 1; notes appear on page 16; V

= +3.3V ±0.3V

PARAMETER/CONDITION

SYM

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

3.0

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

2.2

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

£ V

(All other pins not under test = 0V)

WE#, RAS#, CAS#, A0-A10,
BA0, CK, CKE

-10

µA

-5

µA

DQMB

-5

µA

4, 30

OUTPUT LEAKAGE CURRENT:
DQ disabled; 0V

£ V

OUT

£ V

-10

µA

4, 30

OUTPUT LEVELS:
Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4

0.4

Table 11: DC Electrical Characteristics and Operating Conditions (8MB)

Note: 1; notes appear on page 16; V

= +3.3V ±0.3V

PARAMETER/CONDITION

SYM

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

3.0

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

2.2

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

£ V

(All other pins not under test = 0V)

WE#, RAS#, CAS#, A0-A10, BA0

-20

µA

CK, CKE

-10

µA

-5

µA

DQMB

-10

µA

4, 30

OUTPUT LEAKAGE CURRENT:
DQ disabled; 0V

£ V

OUT

£ V

-20

µA

4, 30

OUTPUT LEVELS:
Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4

0.4

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Table 12: I

Specifications and Conditions (4MB)

DRAM components only
Notes: 1,

, 11, 13; notes appear on page 16; V

= V

Q = +3.3V ±0.3V

MAX

PARAMETER/CONDITION

SYMBOL

-8

-10

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;

RC =

RC (MIN)

270

260

3, 18, 19, 27

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All

device banks active after

RCD met; No accesses in progress

3, 12, 19, 27

OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active

200

160

3, 18, 19, 27

AUTO REFRESH CURRENT:

RC = 15.625

s; CAS latency = 3;

CS# = HIGH; CKE = HIGH;

CK = 15

s (10

s for -8)

3, 12, 18, 19, 27

SELF REFRESH CURRENT: CKE

£ 0.2V

Table 13: I

Specifications and Conditions (8MB)

DRAM components only
Notes: 1, 5,

, 11, 13; notes appear on page 16; V

= V

Q = +3.3V ±0.3V

MAX

PARAMETER/CONDITION

SYMBOL

-8

-10

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE;

RC =

RC (MIN)

274

264

3, 18, 19, 27

STANDBY CURRENT: Power-Down Mode; All device device banks
idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All

device banks active after

RCD met; No accesses in progress

3, 12, 19, 27

OPERATING CURRENT: Burst Mode; Continuous burst; READ or
WRITE; All device banks active

204

164

3, 18, 19, 27

AUTO REFRESH CURRENT:

RC = 15.625

s; CAS latency = 3;

CS# = HIGH; CKE = HIGH;

CK = 15

s (10

s for -8)

140

120

3, 12, 18, 19, 27

SELF REFRESH CURRENT: CKE

£ 0.2V

NOTE:

a - Value calculated as one module rank in this operating condition, and all other module ranks in Power-Down Mode.
b - Value calculated reflects all module ranks in this operating condition.

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Table 14: Capacitance (4MB)

Notes:

; t

his parameter is sampled; notes appear on page 16; V

= +3.3V; f = 1 MHz

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: A0-A10, BA0, RAS#, CAS#, WE#, CKE

Input Capacitance: CK

11.8

14.8

Input Capacitance: S#

2.5

Input Capacitance: DQMB

2.5

Input Capacitance: SCL, SA0-SA2, SDA

Input/Output Capacitance: DQ

6.5

Table 15: Capacitance (8MB)

Notes:

; t

his parameter is sampled; notes appear on page 16; V

= +3.3V; f = 1 MHz

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: A0-A10, BA0, RAS#, CAS#, WE#

Input Capacitance: CKE

Input Capacitance: CK

11.8

14.8

Input Capacitance: S#

2.5

Input Capacitance: DQMB

Input Capacitance: SCL, SA0-SA2, SDA

Input/Output Capacitance: DQ

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Table 16: SDRAM Component AC Electrical Characteristics

Notes: 15, 29; notes appear on page 16; SDRAM component specifications

PARAMETER

SYMBOL

-8

-10

UNITS

NOTES

MIN

MAX

MIN

MAX

Access time from CLK (positive edge)

CL = 3

7.5

CL = 2

CL = 1

Address hold time

Address setup time

CLK high-level width

3.5

CLK low-level width

3.5

Clock cycle time

CL = 3

CL = 2

22, 23

CL = 1

CKE hold time

CKH

CKE setup time

CKS

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

Data-in hold time

Data-in setup time

Data-out high-impedance time

CL = 3

CL = 2

CL = 1

Data-out low-impedance time

Data-out hold time (load)

2.5

ACTIVE to PRECHARGE command period

RAS

120,000

ACTIVE to ACTIVE command period

AUTO REFRESH period

REF

ACTIVE to READ or WRITE delay

RCD

Refresh period (4,096 cycles)

REF

PRECHARGE command period

ACTIVE bank A to ACTIVE bank B command period

RRD

Transition time

0.3

WRITE recovery time

1 CLK +

2ns

1 CLK

Exit SELF REFRESH to ACTIVE command

XSR

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Table 17: AC Functional Characteristics

Notes: 5 9, 11; notes appear on page 16

PARAMETER

SYMBOL

-8

-10

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVATE command

CL = 3

DAL

15, 21

CL = 2

DAL

15, 21

CL = 1

DAL

15, 21

Data-in to precharge

DPL

Last data-in to BURST STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

21, 26

LOAD MODE REGISTER command to ACTIVE or REFRESH
command

MRD

Data-out to high-impedance from
PRECHARGE command

CL = 3

ROH

CL = 2

ROH

CL = 1

ROH

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Notes

1. All voltages referenced to V

2. This parameter is sampled. V

, V

Q = +3.3V;

f = 1 MHz; T

= 25°C; pin under test biased at 1.4V.

3. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to

indicate cycle time at which proper operation
over the full temperature range is ensured (0°C

£ +70°C).

6. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

and V

Q must be at same potential.) The two

AUTO REFRESH command wake-ups should be
repeated any time the

REF refresh requirement is

exceeded.

7. AC characteristics assume

T = 1ns.

8. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

9. Outputs measured at 1.5V with equivalent load:

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V,

with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V

(MAX) and V

(MIN) and no longer at the ISV crossover point.

12. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

13. I

specifications are tested after the device is

properly initialized.

14. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 100 MHz for -10;

CK = 125 MHz

for -8.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

£ 3ns, and the pulse width cannot be

greater than one third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

£ 3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7.5ns for -10; and 7ns for -8

after the first clock delay, after the last WRITE is
executed. May not exceed limit set for precharge
mode.

25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. For -8, CL = 3 and

CK = 7.5ns; for -10, CL = 2 and

CK = 10ns.

28. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

limit is

actually a nominal value and does not result in a
fail value.

29. Refer to device data sheet for timing waveforms.
30. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

50pF

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 7, Data Validity, and Figure 8, Defini-
tion of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 9, Acknowledge Response from Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 7: Data Validity

Figure 8: Definition of Start and Stop

Figure 9: Acknowledge Response from Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Figure 10: SPD EEPROM

Table 18: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 19: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

Start, Device Select, RW = 1

RandomAddressRead

or V

Start, Device Select, RW= 0, Address

or V

RESTART, Device Select, RW= 1

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

£ 16

START, Device Select, RW = 0

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

NOTE:

The SPD EEPROM WRITE cycle time

(

WRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains
HIGH due to the pull-up resistor, and the EEPROM does not respond to its slave address.

Table 20: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V

; V

= +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT:
SCL = SDA = V

- 0.3V; All other inputs = V

DD or

µA

POWER SUPPLY CURRENT:
SCL clock frequency = 100 KHz

Table 21: Serial Presence-Detect EEPROM AC Electrical Characteristics

All voltages referenced to V

; V

= +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

µs

Time the bus must be free before a new transition can start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

Clock HIGH period

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Table 22: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY

(VERSION)

MT2LSDT132U

MT4LSDT232UD

Number of Bytes Used by Micron

128

Total Number of SPD Memory Bytes

256

Memory Type

SDRAM

Number of Row Addresses

Number of Column Addresses

Number of Module Ranks

1or 2

Module Data Width

Module Data Width (continued)

Module Voltage Interface Levels

LVTTL

SDRAM Cycle Time,

(CAS Latency = 3)

10ns (-10)

8ns (-8)

SDRAM Access From Clock,

(CAS Latency = 3)

7.5ns (-10)

6ns (-8)

75
60

Module Configuration Type

None

Refresh Rate/Type

15.62µs / Self

SDRAM Width (Primary SDRAM)

Error-checking SDRAM Data Width

Minimum Clock Delay,

CCD

Burst Lengths Supported

1, 2, 4, 8,

Page

Number of Banks on SDRAM Device

CAS Latencies Supported

1, 2, 3

CS Latency

WE Latency

SDRAM Module Attributes

Unbuffered

SDRAM Device Attributes: General

Attributes

SDRAM Cycle Time,

(CAS Latency = 2)

15ns (-10)

10ns (-8)

SDRAM Access From Clock,

AC, (CAS Latency = 2)

9ns

SDRAM Cycle Time,

(CAS Latency = 1)

30ns (-10)

25ns (-8)

78
64

SDRAM Access From Clock,

AC, (CAS Latency = 1)

27ns (-10)

22ns (-8)

6C
58

Minimum Row Precharge Time,

30ns (-10)

20ns (-8)

1E
14

Minimum Row Active to Row Active,

RRD

20ns

Minimum RAS# to CAS# Delay,

RCD

30ns (-10)

20ns (-8)

1E
14

Minimum RAS# Pulse Width,

RAS

60ns (-10)

50ns (-8)

3C
32

Module Rank Density

4MB

Command/Address Setup,

3ns (-10)

2ns (-8)

30
20

Command/Address Hold,

1ns

Data Signal Input Setup,

3ns (-10)

2ns (-8)

30
20

Data Signal Input Hold,

1ns

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

4MB, 8MB (x32)

SDRAM DIMMs

09005aef80948ad4

SD2_4C1_2x32UDG_A.fm - Rev. A 2/03 EN

Figure 12: 100-Pin DIMM Dimensions (MT4LSDT232UD)

NOTE:

All dimensions in inches (millimeters)

or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete
power supply and temperature range for production
devices.

Although considered final, these specifications are

subject to change, as further product development and
data characterization sometimes occur.

0.700 (17.78)

TYP

0.118 (3.00)

(2X)

0.118 (3.00) TYP

0.079 (2.00) R

(2X)

PIN 1

0.250 (6.35) TYP

0.050 (1.27)

TYP

0.118 (3.00)

TYP

0.039 (1.00)

TYP

0.039 (1.00) R(2X)

PIN 50

2.850 (72.39)

0.157 (4.00)

MAX

0.054 (1.37)
0.046 (1.17)

1.005 (25.53)
0.995 (25.27)

3.557 (90.34)
3.545 (90.04)

0.128 (3.25)
0.118 (3.00)

(2X)

Front View

Back View

PIN 100

PIN 51

MAX

MIN

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4LSDT232UDG-8_

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4LSDT232UDG-8_