4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev. 8/02

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

SMALL-OUTLINE
SDRAM MODULE

MT4LSDT464(L)H(I) - 32MB
MT4LSDT864(L)H(I) - 64MB
MT4LSDT1664(L)H(I) - 128MB

For the latest data sheet, please refer to the Micron Web
site:

www.micron.com/moduleds

FEATURES

· JEDEC-standard PC100 and PC133 compliant 144-pin,

small-outline, dual in-line memory module (SODIMM)

· Unbuffered
· 32MB (4Meg x 64), 64MB (8 Meg x 64), and 128MB

(16 Meg x 64)

· Single +3.3V ±0.3V power supply
· Fully synchronous; all signals registered on positive

edge of system clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal SDRAM banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge and Auto Refresh Modes
· Self Refresh Mode: Standard and Low Power
· 32MB and 64MB: 64ms, 4,096-cycle refresh

(15.625µs refresh interval); 128MB: 64ms, 8,192-
cycle refresh (7.81µs refresh interval)

· LVTTL-compatible inputs and outputs
· Serial Presence-Detect (SPD)

OPTIONS

MARKING

· Self Refresh Current

Standard

None

Low-Power

· Operating Temperature Range

Commercial (0

°C to

+ 70

°C

)

Industrial (-40

°C to +85°C)

None

· Package

144-pin SODIMM (gold)

· Memory Clock/CAS Latency

7.5ns (133 MHz)/CL = 2

-13E

7.5ns (133 MHz)/CL = 3

-133

10ns (100 MHz)/CL = 2

-10E

NOTE:

1. Low Power and Industrial Temperature options not avail-

able concurrently. Consult Micron for available option
combinations.

2. Consult Micron for availability; Industrial Temperature

option available in -133 speed only.

ADDRESS TABLE

32MB

MODULE

64MB

MODULE

128MB

MODULE

Refresh Count

Device Banks

4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Device Conf.

4 Meg x16

8 Meg x 16

16 Meg x 16

Row Addr.

4K (A0A11) 4K (A0A11)

8K (A0A12)

Column Addr. 256 (A0A7) 512 (A0A8)

512 (A0A8)

ModuleBanks

1(S0)

TIMING PARAMETERS

MODULE

MARKINGS

PC100

CL -

RCD -

PC133

CL -

RCD -

-13E

2 - 2 - 2

-133

2 - 2 - 2

3 - 3 - 3

-10E

2 - 2 - 2

144-Pin SODIMM (MO 190)

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

NOTE:

1. Pin 70 is No Connect for 32MB and 64MB modules, or A12 for 128MB modules.

PIN Locations (144-PIN SODIMM)

PART NUMBERS

PART NUMBER

CONFIGURA-

TION

SYSTEM

BUS SPEED

PART NUMBER

CONFIGURA-

TION

SYSTEM

BUS SPEED

MT4LSDT464(L)H(I)G-13E_

4 Meg x 64

133 MHz

MT4LSDT864(L)HG-10E_

8 Meg x 64

100 MHz

MT4LSDT464(L)H(I)G-133_

4 Meg x 64

133 MHz

MT4LSDT1664(L)H(I)G-13E_

16 Meg x 64

133 MHz

MT4LSDT464(L)HG-10E_

4 Meg x 64

100 MHz

MT4LSDT1664(L)H(I)G-133_

16 Meg x 64

133 MHz

MT4LSDT864(L)H(I)G-13E_

8 Meg x 64

133 MHz

MT4LSDT1664(L)HG-10E_

16 Meg x 64

100 MHz

MT4LSDT864(L)H(I)G-133_

8 Meg x 64

133 MHz

NOTE:

1. The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revi-

sion codes. Example: MT4LSDT1664HG-133B1

PIN ASSIGNMENT
(144-PIN SODIMM FRONT)

SYMB

DQ8

109

DQ0

DQ9

111

A10

DQ1

DQ10

DNU

113

DQ2

DQ11

DNU

115 DQMB2

DQ3

117 DQMB3

DQ12

DQ16

119

Vss

DQ4

DQ13

DQ17

121

DQ24

DQ5

DQ14

DQ18

123

DQ25

DQ6

DQ15

DQ19

125

DQ26

DQ7

127

DQ27

Vss

DNU

DQ20

129

DQMB0

DNU

DQ21

131

DQ28

DQMB1

CK0

DQ22

133

DQ29

DQ23

135

DQ30

RAS#

101

137

DQ31

WE#

103

139

S0#

105

141

SDA

DNU

107

Vss

143

PIN ASSIGNMENT
(144-PIN SODIMM BACK)

SYMBO

DQ40

DNU

110

BA1

DQ32

DQ41

112

A11

DQ33

DQ42

DNU

114

DQ34

DQ43

DNU

116 DQMB6

DQ35

118 DQMB7

DQ44

DQ48

120

DQ36

DQ45

DQ49

122

DQ56

DQ37

DQ46

DQ50

124

DQ57

DQ38

DQ47

DQ51

126

DQ58

DQ39

128

DQ59

DNU

DQ52

130

DQMB4

DNU

DQ53

132

DQ60

DQMB5

CKE0

DQ54

134

DQ61

100

DQ55

136

DQ62

CAS#

102

138

DQ63

DNU

104

140

70 NC/

A12

106

BA0

142

SCL

108

144

(all even pins)

PIN 144

PIN 2

Back View

PIN 1

PIN 143

(all odd pins)

Front View

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

PIN DESCRIPTIONS

Pin numbers may not correlate with symbols. Refer to the Pin Assignment table for pin number and symbol information.

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

65, 66, 67

RAS#, CAS#, WE#

Input

Command Inputs: RAS#, CAS#, and WE# (along with S#)
define the command being entered.

CK0

Input

Clock: CK is driven by the system clock. All SDRAM input
signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.

CKE0

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the
CK signal. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device banks
idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank)
or CLOCK SUSPEND operation (burst access in progress). CKE
is synchronous except after the device enters power-down
and self refresh modes, where CKE becomes asynchronous
until after exiting the same mode. The input buffers,
including CK, are disabled during power-down and self
refresh modes, providing low standby power.

S0#

Input

Chip Select: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.

23, 24, 25, 26, 115, 116, 117,

118

DQMB0-DQMB7

Input

Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.

106, 110

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.

29, 30, 31,32, 33, 34,

(128MB)

, 103, 104, 105,

109, 111, 112

A0-A11

(32MB, 64MB)

A0-A12

(128MB)

Input

Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command.

142

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.

141

SDA

Input/

Output

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

3, 4, 5, 6, 7, 8, 9, 10, 13, 14,

15, 16, 17, 18, 19, 20, 37, 38,
39, 40, 41, 43, 44, 47, 48, 49,
50, 51, 52, 53, 54, 83, 84, 85,
86, 87, 88, 89, 90, 93, 94, 95,
96, 97, 98, 99, 100, 121, 122,
123, 124, 125, 126, 127, 128,
131, 132, 133, 134, 135, 136,

137, 138

DQ0-DQ63

Input/

Output

Data I/O: Data bus.

11, 12, 27, 28, 45, 46, 63, 64,

81, 82, 101, 102, 113, 114,

129, 130, 143, 144

Supply

Power Supply: +3.3V ±0.3V.

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

Functional Block Diagram

SPD

SCL

SDA

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQMB0

S0#

RAS#

CAS#

CKE0

WE#

CAS#: SDRAMs

CKE0: SDRAMs

WE#: SDRAMs

A0-A11: SDRAMs

A0-A12: SDRAMs

BA0-BA1: SDRAMs

A0-A11 (32MB, 64MB)

A0-A12 (128MB)

BA0-BA1

SDRAMs

U1, U2, U3, U4

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML SO#

DQMB1

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQMB4

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML SO#

DQMB5

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ7

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQMB2

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML SO#

DQMB3

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQMH

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQMB6

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQML SO#

DQMB7

CK0

RAS#: SDRAMs

10 pf

CK1

SDRAMs = MT48LC4M16A2TG for 32MB module, comm. temp.
SDRAMs = MT48LC8M16A2TG for 64MB module, comm. temp.
SDRAMs = MT48LC16M16A2TG for 128MB module, comm. temp.
SDRAMs = MT48LC4M16A2TG IT for 32MB module, indust. temp.
SDRAMs = MT48LC8M16A2TG IT for 64MB module, indust. temp.
SDRAMs = MT48LC16M16A2TG IT for 128MB module, indust. temp.

Industrial Temperature modules use -75-speed components only.

Notes:
All resistor values are 10

unless otherwise specified.

Per industry standard, Micron modules use various
component speed grades as referenced in the module
part numbering guide at:

www.micron.com/numberguide

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

GENERAL DESCRIPTION

The MT4LSDT464H, MT4LSDT864H, and

MT4LSDT1664H are high-speed CMOS, dynamic ran-
dom-access 32MB, 64MB, and 128MB unbuffered
memory modules, organized in x64 configurations.

These modules use internally configured quad-

bank SDRAMs with a synchronous interface (all signals
are registered on the positive edge of the clock signal
CK). The four banks of a x16, 64Mb device (for the
32MB modules) are each configured as 4,096 bit-rows,
by 256 bit-columns, by 16 input/output bits. The four
banks of a x16, 128Mb device (for the 64MB modules)
are configured as 4,096 bit-rows, by 512 bit columns,
by 16 input/output bits

The four banks of a x16,

256Mb device (for the 128MB modules) are configured
as 8,192 bit-rows, by 512 bit columns, by 16 input/out-
put bits

Read and write accesses to the SDRAM modules are

burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0-A11
[32MB and 64MB], or A0-A12 [128MB] select the device
row). The address bits A0A7 (32MB), or A0-A8 (64MB
and 128MB), registered coincident with the READ or
WRITE command, are used to select the starting
device column location for the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed row
precharge that is initiated at the end of the burst
sequence.

These modules use an internal pipelined architec-

ture to achieve high-speed operation. This architec-
ture is compatible with the 2n rule of prefetch
architectures, but it also allows the column address to
be changed on every clock cycle to achieve a high-
speed, fully random access. Precharging one device
bank while accessing one of the other three device
banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.

SDRAM modules offer substantial advances in

DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-

matic column-address generation, the ability to inter-
leave between internal banks in order to hide
precharge time and the capability to randomly change
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM oper-
ation, refer to the 64Mb, 128Mb, or 256Mb SDRAM
component data sheets.

Serial Presence Detect Operation

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes are pro-
grammed by Micron to identify the module type,
SDRAM characteristics and module timing parame-
ters. The remaining 128 bytes of storage are available
for use by the customer. System READ/WRITE opera-
tions between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM's SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique
DIMM/EEPROM addresses.

Prior to normal operation, the SDRAM must be ini-

tialized. The following sections provide detailed infor-
mation covering device initialization, register
definition, command descriptions and device opera-
tion.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V

and V

Q (simul-

taneously) and the clock is stable (stable clock is
defined as a signal cycling within timing constraints
specified for the clock pin), the SDRAM requires a
100µs delay prior to issuing any command other than a
COMMAND INHIBIT or NOP. Starting at some point
during this 100µs period and continuing at least
through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be
applied. All device banks must then be precharged,
thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.

Mode Register

The mode register is used to define the specific

mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode, and a write burst
mode, as shown in the Mode Register Definition Dia-
gram. The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.

Mode register bits M0M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
burst mode, and M10 and M11 are reserved for future
use. For the 128MB module, M12 (A12) is undefined,
but should be driven LOW during loading of the mode
register.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Mode Register Definition Diagram

Reserved*

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

A11

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = "0, 0, 0"

to ensure compatibility

with future devices.

A12

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

Op Mode

A10

A11

Reserved* WB

*Should program

M11, M10 = "0, 0"

to ensure compatibility

with future devices.

32MB and 64MB Module

128MB Module

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

BURST LENGTH

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as
shown in Mode Register Definition Diagram. The
burst length determines the maximum number of col-
umn locations that can be accessed for a given READ
or WRITE command. Burst lengths of 1, 2, 4, or 8 loca-
tions are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is
used in conjunction with the BURST TERMINATE
command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1
Ai (where i is the most significant column address bit
for a given device configuration) when the burst length
is set to two; by A2Ai when the burst length is set to
four; and by A3Ai when the burst length is set to eight.
The remaining (least significant) address bit(s) is (are)
used to select the starting location within the block.
Full-page bursts wrap within the page if the boundary
is reached, as shown in the Burst Definition Table.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.

BURST DEFINITION TABLE

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

Page

(y)

n = i*

(location 0-

Cn, Cn + 1,

Cn + 2

Cn + 3, Cn + 4...

...Cn - 1,

Cn...

Not supported

*i = 7 for 32MB modules

i = 8 for 64MB and 128MB modules

NOTE:

1. For full-page accesses: y = 256 (32MB), y= 512 (64MB and

128MB)

2. For a burst length of two, A1-Ai select the block-of-two

burst; A0 selects the starting column within the block.

3. For a burst length of four, A2-Ai select the block-of-four

burst; A0-A1 select the starting column within the block.

4. For a burst length of eight, A3-Ai select the block-of-

eight burst; A0-A2 select the starting column within the
block.

5. For a full-page burst, the full row is selected and A0-Ai

select the starting column.

6. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

7. For a burst length of one, A0-Ai select the unique col-

umn to be accessed, and mode register bit M3 is
ignored.

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

CAS Latency

The CAS latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a READ command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in the CAS Latency Dia-
gram. The CAS Latency Table indicates the operating
frequencies at which each CAS latency setting can be
used.

Reserved states should not be used, because un-

known operation or incompatibility with future ver-
sions may result.

CAS Latency Diagram

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.

Test modes and reserved states should not be used,

because unknown operation or incompatibility with
future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via M0-

M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (non-
burst) accesses.

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

CAS LATENCY TABLE

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHz)

SPEED

CAS LATENCY = 2

CAS LATENCY = 3

-13E

133

143

-133

100

133

-10E

100

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

COMMANDS

The Truth Table provides a quick reference of avail-

able commands. This is followed by written descrip-
tion of each command. For a more detailed des-

cription of commands and operations, refer to the
64Mb, 128Mb, or 256Mb SDRAM component data
sheet.

TRUTH TABLE SDRAM COMMANDS AND DQMB OPERATION

NOTE:

1. CKE is HIGH for all commands shown except SELF REFRESH.

NAME (FUNCTION)

CS#

RAS# CAS# WE# DQMB

ADDR

NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/

Row

2. A0-A11 (32MB and 64MB) , or A0-A12 (128MB) provide device row address, and BA0, BA1 determine which device bank is made

active.

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

3. A0-A7 (32MB) or A0-A8 (64MB and 128MB) provide device column address; A10 HIGH enables the auto precharge feature (nonper-

sistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written
to.

WRITE (Select bank and column, and start WRITE
burst)

L/H

Bank/Col

Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

4. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1

are "Don't Care."

AUTO REFRESH or SELF REFRESH
(Enter self refresh mode)

5. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
6. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.

LOAD MODE REGISTER

Op-code

7. A0-A11 define the op-code written to the mode register, and for the 128MB module, A12 should be driven low.

Write Enable/Output Enable

Active

8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

Write Inhibit/Output High-Z

High-Z

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

, V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Voltage on Inputs NC or I/O Pins

Relative to V

. . . . . . . . . . . . . . . . . . . . -1V to +4.6V

Operating Temperature

(Ambient). . . . . . . . . . . . . . . . . . . . .. 0°C to +70°C

(Industrial Temperature) . . . . .. -40°C to +85°C

Storage Temperature (plastic) . . . . . .-55°C to +150°C
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4W
Short Circuit Output Current . . . . . . . . . . . . . . . .50mA

*Stresses greater than those listed under "Absolute

Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

Notes: 2, 6, 7; notes appear following parameter tables; V

, V

Q = +3.3V ±0.3V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SUPPLY VOLTAGE

, V

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

(All other pins not under test = 0V)

Command and
Address Inputs

-20

µA

CK, S#

-20

µA

DQ, DQMB

-5

µA

OUTPUT LEAKAGE CURRENT: DQ pins are
disabled; 0V

OUT

-5

µA

OUTPUT LEVELS:
Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

2.4

0.4

SPECIFICATIONS AND CONDITIONS 32MB MODULE

Notes: 1, 2, 6, 7, 12, 14; notes appear following parameter tables; V

, V

Q = +3.3V ±0.3V

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133 -10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or
WRITE;

RC =

RC (MIN)

500

460

380

4, 19, 20, 31

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH;
All device banks active after

RCD met; No accesses in

progress

180

140

4, 13, 20, 31

OPERATING CURRENT: Burst Mode; Continuous burst; READ
or WRITE; All device banks active

600

560

480

4, 19, 20, 31

AUTO REFRESH CURRENT

RFC =

RFC

(MIN)

920

840

760

4, 13, 19,
20, 31,32

CKE = HIGH; S# = HIGH

RFC = 15.625µs

SELF REFRESH CURRENT: CKE

0.2V

(Low power not available with industrial
temperature option)

Standard

Low Power

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

SPECIFICATIONS AND CONDITIONS 64MB MODULE

Notes: 1, 2, 6, 7, 12, 14; notes appear following parameter tables; V

, V

Q = +3.3V ±0.3V

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133 -10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or
WRITE;

RC =

RC (MIN)

640

600

560

4, 19, 20, 31

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode;
CKE = HIGH; CS# = HIGH; All device banks active after

RCD

met; No accesses in progress

200

160

4, 13, 20, 31

OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All device banks active

660

600

560

4, 19, 20, 31

AUTO REFRESH CURRENT

RFC =

RFC

(MIN)

1,320

1,240 1,080

4, 13, 19,

20, 31, 32

CKE = HIGH; S# = HIGH

RFC = 15.625µs

SELF REFRESH CURRENT: CKE

0.2V

(Low power not available with industrial
temperature option)

Standard

Low Power

SPECIFICATIONS AND CONDITIONS 128MB MODULE

Notes: 1, 2, 6, 7, 12, 14; notes appear following parameter tables; V

, V

Q = +3.3V ±0.3V

MAX

PARAMETER/CONDITION

SYMBOL

-13E

-133 -10E

UNITS

NOTES

OPERATING CURRENT: Active Mode; Burst = 2; READ or
WRITE;

RC =

RC (MIN)

540

500

4, 19, 20, 31

STANDBY CURRENT: Power-Down Mode; All device device
banks idle; CKE = LOW

STANDBY CURRENT: Active Mode;
CKE = HIGH; CS# = HIGH; All device banks active after

RCD

met; No accesses in progress

160

4, 13, 20, 31

OPERATING CURRENT: Burst Mode; Continuous burst;
READ or WRITE; All device banks active

540

4, 19, 20, 31

AUTO REFRESH CURRENT

RFC =

RFC

(MIN)

1,140

1,080 1,080

4, 13, 19,

20, 31, 32

CKE = HIGH; S# = HIGH

RFC = 7.8125µs

SELF REFRESH CURRENT: CKE

0.2V

(Low power not available with industrial
temperature option)

Standard

Low Power

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

CAPACITANCE

Notes: 1, 2; notes appear following parameter tables.

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#,
WE#, S0#, CKE0, DQMB0-DQMB7

15.2

Input Capacitance: CK0

CI2

Input/Output Capacitance: SCL, SA0-SA2, SDA

Input/Output Capacitance: DQ0-DQ63

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS

Notes: 1, 6, 7, 9, 10, 12; notes appear following parameter tables.
Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters.

AC CHARACTERISTICS

SYMBOL

-13E

-133

-10E

UNITS

NOTES

PARAMETER

MIN

MAX

MIN

MAX

MIN

MAX

Access time from CLK
(positive edge)

CL = 3

AC(3)

5.4

CL = 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL = 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load)

OHN

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK

+ 7ns

1 CLK +

7.5ns

1 CLK

+ 7ns

Exit SELF REFRESH to ACTIVE command

XSR

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

AC FUNCTIONAL CHARACTERISTICS

Notes: 6, 7, 8, 9, 10, 12; notes appear following parameter tables.

PARAMETER

SYMBOL

-13E

-133

-10E

UNITS

NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

16, 22

Data-in to PRECHARGE command

DPL

17, 22

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

17, 22

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE
command

CL=3

ROH(3)

CL = 2

ROH(2)

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

NOTES

1. Module AC timing parameters comply with PC100

and PC133 Design Specs, based on component
parameters.

2. All voltages referenced to V

3. This parameter is sampled. V

, V

Q = +3.3V;

f = 1 MHz; T

= 25°C; pin under test biased at

1.4V.

4. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time and the outputs open.

5. Enables on-chip refresh and address counters.
6. The minimum specifications are used only to

indicate cycle time at which proper operation
over the full temperature range is ensured (Com-
mercial temperature: 0°C

+70°C and Indus-

trial Temperature: -40°C

+85°C).

7. An initial pause of 100µs is required after power-

up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V

and V

Q must be powered up simultaneously.

and V

Q must be at the same potential.) The

two AUTO REFRESH command wake-ups should
be repeated any time the

REF refresh require-

ment is exceeded.

8. AC characteristics assume

T = 1ns.

9. In addition to meeting the transition rate specifi-

cation, the clock and CKE must transit between
V

and V

(or between V

and V

) in a mono-

tonic manner.

10. Outputs measured at 1.5V with equivalent load:

11.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

12. AC timing and I

tests have V

= 0V and V

= 3V,

with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1ns, then
the timing is referenced at V

(MAX) and V

(MIN)

and no longer at the 1.5V crossover point.

13. Other input signals are allowed to transition no

more than once every two clocks and are other-
wise at valid V

or V

levels.

14. IDD specifications are tested after the device is

properly initialized.

15. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

16. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle
rate.

17. Timing actually specified by

WR.

18. Required clocks are specified by JEDEC function-

ality and are not dependent on any timing param-
eter.

19. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

20. Address transitions average one transition every

two clocks.

21. CLK must be toggled a minimum of two times

during this period.

22. Based on

CK = 10ns for -10E, and

CK = 7.5ns for

-133 and -13E.

23. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

3ns, and the pulse width cannot be

greater than one third of the cycle rate. V

under-

shoot: V

(MIN) = -2V for a pulse width

3ns.

24. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing

WR, and PRECHARGE commands). CKE may

be used to reduce the data rate.

25. Auto precharge mode only. The precharge timing

budget (

RP) begins 7ns for -13E; 7.5ns for -133

and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.

26. Precharge mode only.
27. JEDEC and PC100 specify three clocks.
28.

AC for -133/-13E at CL = 3 with no load is 4.6ns

and is guaranteed by design.

29. Parameter guaranteed by design.

30. The value of

RAS used in -13E speed grade mod-

ule SPDs is calculated from

RC -

RP = 45ns.

31. For -10E, CL= 2 and

CK = 10ns; for -133, CL = 3

and

CK = 7.5ns; for -13E, CL = 2 and

CK = 7.5ns.

32. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

33. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

50pF

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (Fig-
ures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD STOP CONDITION

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 1

Data Validity

Figure 2

Definition of Start and Stop

Figure 3

Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

EEPROM DEVICE SELECT CODE

Note: The most significant bit (b7) is sent first.

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

Protection Register Select Code

EEPROM OPERATING MODES

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = 1

Random Address Read

or V

START, Device Select, RW = 0, Address

or V

reSTART, Device Select, RW= 1

Sequential Read

or V

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

START, Device Select, RW = 0

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

Notes: 1, 2; notes appear following EEPROM AC and DC operating conditions tables.

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT:
SCL = SDA = V

- 0.3V; All other inputs = GND or 3.3V ±10%

µA

POWER SUPPLY CURRENT:

SCL clock frequency = 100 KHz

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

SPD EEPROM TIMING DIAGRAM

NOTE:

1. V

= +3.3V ±0.3V

2. All voltages referenced to V

3. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM

internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-
up resistor, and the EEPROM does not respond to its slave address.

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS

Notes: 1, 2; notes appear following EEPROM AC and DC operating conditions tables.

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

µs

Time the bus must be free before a new transition can
start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

Clock HIGH period

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

SERIAL PRESENCE-DETECT MATRIX

Notes: 1, 2; notes appear at end of Serial Presence-Detect Matrix

BYTE DESCRIPTION

ENTRY

(VERSION)

MT4LSDT464(L)H(I)

MT4LSDT864(L)H(I)

MT4LSDT1664(L)H(I)

NUMBER OF BYTES USED BY MICRON

128

TOTAL NUMBER OF SPD MEMORY BYTES

256

MEMORY TYPE

SDRAM

NUMBER OF ROWADDRESSES

12 or 13

NUMBER OF COLUMN ADDRESSES

8 or9

NUMBER OF MODULE BANKS

1 01

MODULE DATA WIDTH

MODULE DATA WIDTH (continued)

MODULE VOLTAGE INTERFACE LEVELS

LVTTL

SDRAM CYCLE TIME,

(CAS LATENCY = 3)

7ns (-13E)

7.5ns (-133)

8ns (-10E)

70
75
80

SDRAM ACCESS FROM CLK,

(CAS LATENCY = 3)

5.4ns (-13E/-133)

6ns (-10E)

54
60

MODULE CONFIGURATION TYPE

NONE

REFRESH RATE/TYPE

15.6µs or

7.81µs/SELF

SDRAM WIDTH (PRIMARY SDRAM)

ERROR-CHECKING SDRAM DATA WIDTH

MINIMUM CLOCK DELAY FROM BACK-TO-
BACK RANDOM COLUMN ADDRESSES,

CCD

BURST LENGTHS SUPPORTED

1, 2, 4, 8, PAGE

NUMBER OF BANKS ON SDRAM DEVICE

CAS LATENCIES SUPPORTED

2, 3

CS LATENCY

WE LATENCY

SDRAM MODULE ATTRIBUTES

UNBUFFERED

SDRAM DEVICE ATTRIBUTES: GENERAL

SDRAM CYCLE TIME ,

(CAS LATENCY = 2)

7.5ns (13E)

10ns (-133/-10E)

SDRAM ACCESS FROM CLK,

(CAS LATENCY = 2)

54ns (-13E)

6ns (-133/-10E)

54
60

SDRAM CYCLE TIME,

(CAS LATENCY = 1)

SDRAM ACCESS FROM CLK,

(CAS LATENCY = 1)

MINIMUM ROW PRECHARGE TIME,

15ns (-13E)

20ns (-133/-10E)

0F
14

MINIMUM ROW ACTIVE TO ROW
ACTIVE,

RRD

14ns (-13E)
15ns (-133)
20ns (-10E)

0E
0F
14

MINIMUM RAS# TO CAS# DELAY,

RCD

15ns (-13E)20ns

(-133/-10E)

0F
14

MINIMUM RAS# PULSE WIDTH,

RAS

(Note 3)

45ns (-13E)

44ns (133)

50ns (-10E)

2C
32

32MB / 64MB / 128MB (x64)

144-PIN SDRAM SODIMMs

4, 8, and 16Meg x 64 SDRAM SODIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C4_8_16X64HG_B.fm - Rev 8/02

NOTE:

1. V

= +3.3V ±0.3V.

2. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."

3. The value of

RAS used for -13E modules is calculated from

RC -

RP. Actual device spec. value is 37ns.

MODULE BANK DENSITY

32MB, 64MB,

or 128MB

COMMAND AND ADDRESS SETUP TIME,

AS,

CMS

1.5ns (-13E/-133)

2ns (-10E)

15
20

COMMAND AND ADDRESS HOLD TIME,

AH,

CMH

0.8ns (-13E/-133)

1ns (-10E)

08
10

DATA SIGNAL INPUT SETUP TIME,

1.5ns (-13E/-133)

2ns (-10E)

15
20

DATA SIGNAL INPUT HOLD TIME,

0.8ns (-13E/-133)

1ns (-10E)

08
10

36-61 RESERVED

SPD REVISION

REV. 1.2

CHECKSUM FOR BYTES 0-62

(-13E)
(-133)
(-10E)

56
9C
E4

A5
ED

72
B8
00

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71 MANUFACTURER'S JEDEC ID CODE (CONT.)

MANUFACTURING LOCATION

1 - 11

01 - 0B

73-90 MODULE PART NUMBER (ASCII)

Variable Data

PCB IDENTIFICATION CODE

1 - 9

01-09

01 - 09

01-09

IDENTIFICATION CODE (CONT.)

YEAR OF MANUFACTURE IN BCD

Variable Data

WEEK OF MANUFACTURE IN BCD

Variable Data

95-98 MODULE SERIAL NUMBER

Variable Data

99-125 MANUFACTURER-SPECIFIC DATA (RSVD)

Variable Data

126 SYSTEM FREQUENCY

100 MHz

(-13E/-133/-10E)

127 SDRAM COMPONENT AND CLOCK DETAIL

SERIAL PRESENCE-DETECT MATRIX (CONTINUED)

Notes: 1, 2; notes appear at end of Serial Presence-Detect Matrix

BYTE DESCRIPTION

ENTRY

(VERSION)

MT4LSDT464(L)H(I)

MT4LSDT864(L)H(I)

MT4LSDT1664(L)H(I)

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4LSDT864LHG-10E_

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT4LSDT864LHG-10E_