Document Outline

Features
Options
Device Timing
Address Table
Pin Assignment, Front View
Part Numbers
General Description
Serial Presence-Detect Operation
Functional Block Diagram
Pin Descriptions
SDRAM Functional Description
Initialization
Mode Register Definition
- Mode Register
- Burst Length
- Burst Type
- CAS Latency
- Operating Mode
- Write Burst Mode
Mode Register Definition Diagram
Burst Definition Table
CAS Latency Diagram
CAS Latency Table
Commands
Truth Table - SDRAM Commands and DQMB Operation
Absolute Maximum Ratings
DC Electrical Characteristics and Operating Conditions
IDD Specifications and Conditions: 64MB Module
IDD Specifications and Conditions: 128MB Module
Capacitance (64MB, 128MB)
Electrical Characteristics and Recommended AC Operating Conditions
AC Functional Characteristics
Notes
SPD Clock and Data Conventions
SPD Start Condition
SPD Stop Condition
SPD Acknowledge
Figure 1 Data Validity
Figure 2 Definition of Start and Stop
Figure 3 Acknowledge Response from Receiver
EEPROM Device Select Code
EEPROM Operating Modes
SPD EEPROM Timing Diagram
Serial Presence-Detect EEPROM Timing Parameters
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Serial Presence-Detect Matrix
144-Pin Micro DIMM

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

FEATURES

· JEDEC-standard, PC100, PC133, 144-pin, MICRO

DIMM

· Utilizes 125 MHz and 133 MHz SDRAM compo-

nents

· 64MB (8 Meg x 64), 128MB (16 Meg x 64)
· Single +3.3V ±0.3V power supply
· Fully synchronous; all signals registered on

positive edge of system clock

· Internal pipelined operation; column address can

be changed every clock cycle

· Internal banks for hiding row access/precharge
· Programmable burst lengths: 1, 2, 4, 8, or full page
· Auto Precharge and Auto Refresh Modes
· Self Refresh Mode: Standard and Low Power
· 64MB module: 64ms, 4,096-cycle refresh; 128MB

module: 64ms, 8,192-cycle refresh.

· LVTTL-compatible inputs and outputs
· Serial Presence-Detect (SPD)

OPTIONS

MARKING

· Self Refresh Current

Standard

None

Low power

· Package

144-pin MICRO DIMM (gold)

· Frequency/CAS Latency

133 MHz/CL = 2

-13E

133 MHz/CL = 3

-133

100 MHz/CL = 2

-10E

MICRO DIMM
SDRAM MODULE

MT4LSDT864W
MT4LSDT1664W

For the latest data sheet, please refer to the Micron Web site:

www.micron.com/datasheets

PIN ASSIGNMENT

(Front View)

144-Pin MICRO DIMM

FRONT

BACK

FRONT

BACK

DQ0

DQ32

DQ1

DQ33

DQ2

DQ34

DQ3

DQ35

DQ16

DQ48

DQ4

DQ36

DQ17

DQ49

DQ5

DQ37

DQ18

DQ50

DQ6

DQ38

DQ19

DQ51

DQ7

DQ39

DQ20

DQ52

DQM0

DQM4

DQ21

DQ53

DQM1

DQM5

DQ22

DQ54

DQ23

100

DQ55

101

102

103

104

105

106

BA0

107

108

DQ8

DQ40

109

110

BA1

DQ9

DQ41

111

A10

112

A11

DQ10

DQ42

113

114

DQ11

DQ43

115

DQM2

116

DQM6

117

DQM3

118

DQM7

DQ12

DQ44

119

120

DQ13

DQ45

121

DQ24

122

DQ56

DQ14

DQ46

123

DQ25

124

DQ57

DQ15

DQ47

125

DQ26

126

DQ58

127

DQ27

128

DQ59

129

130

131

DQ28

132

DQ60

CK0

CKE0

133

DQ29

134

DQ61

135

DQ30

136

DQ62

RAS#

CAS#

137

DQ31

138

DQ63

WE#

139

140

S0#

NC /

A12

141

SDA

142

SCL

143

144

NOTE: Pin 70 is a no connect (NC) for MT4LSDT864W. For

MT4LSDT1664W, pin 70 is address input A12.

DEVICE TIMING

Module

PC100

PC133

Markings

CL -

RCD -

CL -

RCD -

-13E

2 - 2 - 2

-133

2 - 2 - 2

3 - 3 - 3

-10E

2 - 2 - 2

ADDRESS TABLE

MT4LSDT864W

MT4LSDT1664W

Refresh Count

Device Banks

4 (BA0, BA1)

Row Addressing

4K (A0A11)

8K (A0A12)

Column Addressing

512 (A0A8)

Module Banks

1 (S0)

Base Part Configuration

8 Meg x 16

16 Meg x 16

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

GENERAL DESCRIPTION

The Micron

MT4LSDT864(L)W and

MT4LSDT1664(L)W are high-speed CMOS, dynamic
random-access, 64MB and 128MB memory modules,
organized in a x64 configuration. These modules use
SDRAMs that are internally configured as quad-bank
DRAMs with a synchronous interface (all signals are
registered on the positive edge of the clock signal CK0).
Read and write accesses to the SDRAM modules is burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the device bank and row to be accessed
(BA0, BA1 select the device bank, A0-A11 select the
device row for the 64MB module; A0-A12 for the 128MB
module). The address bits registered coincident with
the READ or WRITE command are used to select the
starting column location for the burst access.

These modules provide for programmable READ or

WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed device
row precharge that is initiated at the end of the burst
sequence. These modules use an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the device column
address to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one

device bank while accessing the alternate device bank
will hide the PRECHARGE cycles and provide seamless,
high-speed, random-access operation.

These modules are designed to operate in 3.3V, low-

power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs, outputs and clocks are LVTTL-compatible.

SDRAM modules offer substantial advances in DRAM

operating performance, including the ability to syn-
chronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between device banks in order to hide precharge
time, and the capability to randomly change device
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 128Mb and 256Mb data sheets.

SERIAL PRESENCE-DETECT OPERATION

These modules incorporate serial presence-detect

(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM's
SCL (clock) and SDA (data) signals.

PART NUMBERS

PART NUMBER

CONFIGURATION

VERSION

MT4LSDT864WG-13E__

8 Meg x 64

133 MHz, CL = 2

MT4LSDT864WG-133__

8 Meg x 64

133 MHz, CL = 3

MT4LSDT864WG-10E__

8 Meg x 64

100 MHz, CL = 2

MT4LSDT864LWG-13E__

8 Meg x 64*

133 MHz, CL = 2

MT4LSDT864LWG-133__

8 Meg x 64*

133 MHz, CL = 3

MT4LSDT864LWG-10E__

8 Meg x 64*

100 MHz, CL = 2

MT4LSDT1664WG-13E__

16 Meg x 64

133 MHz, CL = 2

MT4LSDT1664WG-133__

16 Meg x 64

133 MHz, CL = 3

MT4LSDT1664WG-10E__

16 Meg x 64

100 MHz, CL = 2

MT4LSDT1664LWG-13E_

16 Meg x 64*

133 MHz, CL = 2

MT4LSDT1664LWG-133_

16 Meg x 64*

133 MHz, CL = 3

MT4LSDT1664LWG-10E_

16 Meg x 64*

100 MHz, CL = 2

NOTE: The designators for component and PCB revision are

the last two characters of each part number. Consult
factory for current revision codes. Example:
MT4LSDT864LG-10EB1.

*Low power option.

PIN 1

PRIMARY SIDE

SECONDARY SIDE

PIN 143

PIN 144

PIN 2

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

FUNCTIONAL BLOCK DIAGRAM

MT4LSDT864(L)W and MT4LSDT1664(L)W

NOTE:

All resistor values are 10 ohms

U1, U2, U3, U4

= MT48LC8M16A2TG SDRAMs for 64MB module

unless otherwise noted.

SPD

SCL

SDA

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQML

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQM0

S0#

RAS#

CAS#

CKE0

WE#

CAS#: SDRAMs

U1, U2, U3, U4

CKE0: SDRAMs

U1, U2, U3, U4

WE#: SDRAMs

U1, U2, U3, U4

A0-A11: SDRAMs

U1, U2, U3, U4

A0-A12: SDRAMs

U1, U2, U3, U4

BA0-1: SDRAMs

U1, U2, U3, U4

A0-A11 (64MB)

A0-A12 (128MB)

BA0-1

SDRAMs

U1, U2, U3, U4

SDRAMs

U1, U2, U3, U4

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

DQMH SO#

DQM1

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQMH

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQM4

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQML SO#

DQM5

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQML

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQM2

DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

DQMH SO#

DQM3

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQMH

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQM6

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQML SO#

DQM7

CK0

RAS#: SDRAMs U1, U2, U3, U4

10 pF

CK1

U1, U2, U3, U4

= MT48LC16M16A2TG SDRAMs for 128MB module

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

PIN DESCRIPTIONS

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

RAS#, CAS#,

Input

Command Inputs: RAS#, CAS#, and WE# (along with

WE#

S0#) define the command being entered.

CK0

Input

Clock: CK0 is driven by the system clock. All SDRAM
input signals are sampled on the positive edge of CK.
CK also increments the internal burst counter and
controls the output registers.

CKE0

Input

Clock Enable: CKE0 activates (HIGH) and deactivates
(LOW) the CK0 signal. Deactivating the clock provides
POWER-DOWN and SELF REFRESH operation (all device
banks idle) or CLOCK SUSPEND operation (burst access
in progress). CKE0 is synchronous except after the
device enters power-down and self refresh modes,
where CKE0 becomes asynchronous until after exiting
the same mode. The input buffers, including CK0, are
disabled during power-down and self refresh modes,
providing low standby power.

S0#

Input

Chip Select: S0# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands
are masked when S0# is registered HIGH. S0# is
considered part of the command code.

DQMB0-DQMB7

Input

Input Mask: DQMB is an input mask signal for write
accesses. Input data is masked when DQMB is sampled
HIGH during a WRITE cycle. The output buffers are
placed in a High-Z state (after a two-clock latency)
when DQMB is sampled HIGH during a READ cycle.

BA0, BA1

Input

Bank Address: BA0 and BA1 define to which device
bank the ACTIVE, READ, WRITE, or PRECHARGE
command is being applied. BA0 is also used to program
the twelfth bit of the Mode Register.

A0-A11

(64MB)

Input

Address Inputs: A0-A11/A12 are sampled during the

A0-A12

(128MB)

ACTIVE command (row-address A0-A11/A12) and READ/
WRITE command (column-address A0-A8, with A10
defining auto precharge) to select one location out of
the memory array in the respective devices bank. A10 is
sampled during a PRECHARGE command to determine
if all device banks are to be precharged (A10 HIGH). The
address inputs also provide the op-code during a LOAD
MODE REGISTER command.

SCL

Input

Serial Clock for Presence-Detect: SCL is used to synchro-
nize the presence-detect data transfer to and from the
module.

DQ0-DQ63

Input/Output

Data I/Os: Data bus.

SDA

Input/Output

Serial Presence-Detect Data: SDA is a bidirectional pin

used to transfer addresses and data into and data out
of the presence-detect portion of the module.

Supply

Power Supply: +3.3V ±0.3V.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SDRAM FUNCTIONAL DESCRIPTION

In general, the 128Mb (8 Meg x 16) and 256Mb

SDRAM (16 Meg x 16) memory devices used for these
modules are quad-bank DRAMs, that operate at 3.3V
and include a synchronous interface (all signals are
registered on the positive edge of the clock signal, CLK).
The four banks of a x16, 128Mb device are each config-
ured as 4,096 bit-rows, by 512 bit-columns, by 16 input/
output bits. The four banks of a x16, 256Mb device are
configured as 8,192 bit-rows by 512 bit columns, by 16
input/output bits.

Read and write accesses to the SDRAM are burst

oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the device bank and row to be accessed
BA0 and BA1 select the device bank, A0-A11 (for 64MB),
or A0-A12 (for 128MB), select the device row. The
address bits A0-A8, registered coincident with the READ
or WRITE command are used to select the starting
device column location for the burst access.

Prior to normal operation, the SDRAM must be

initialized. The following sections provide detailed
information covering device initialization, register defi-
nition, command descriptions and device operation.

Initialization

SDRAMs must be powered up and initialized in a

predefined manner. Operational procedures other than
those specified may result in undefined operation.
Once power is applied to V

and V

Q (simulta-

neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP. Starting at some point during
this 100µs period and continuing at least through the
end of this period, COMMAND INHIBIT or NOP com-
mands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having
been applied, a PRECHARGE command should be ap-
plied. All device banks must then be precharged,
thereby placing the device in the all device banks idle
state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles are
complete, the SDRAM is ready for mode register pro-
gramming. Because the mode register will power up in
an unknown state, it should be loaded prior to applying
any operational command.

Mode Register Definition

MODE REGISTER

The mode register is used to define the specific mode

of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in Mode Register Definition Diagram. The
mode register is programmed via the LOAD MODE
REGISTER command and will retain the stored infor-
mation until it is programmed again or the device loses
power.

Mode register bits M0-M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.

Address A12 (M12) is undefined but should be driven

LOW during loading of the mode register.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst

oriented, with the burst length being programmable, as
shown in Mode Register Definition Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available for
the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table The block is uniquely selected by A1-
A8 when the burst length is set to two; A2-A8 when the
burst length is set to four; and by A3-A8 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting location
within the block. Full-page bursts wrap within the page
if the boundary is reached, as shown in the Burst
Definition Table.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

NOTE: 1. For full-page accesses: y = 512

2. For a burst length of two, A1-A8 select the block

of two burst; A0 selects the starting column
within the block.

3. For a burst length of four, A2-A8 select the block

of four burst; A0-A1 select the starting column
within the block.

4. For a burst length of eight, A3-A8 select the

block of eight burst; A0-A2 select the starting
column within the block.

5. For a full-page burst, the full row is selected and

A0-A8 select the starting column.

6. Whenever a boundary of the block is reached

within a given sequence above, the following
access wraps within the block.

7. For a burst length of one, A0-A8 select the unique

column to be accessed, and Mode Register bit M3
is ignored.

Burst Definition Table

Burst

Starting Column

Order of Accesses Within a Burst

Length

Address

Type = Sequential

Type = Interleaved

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A2 A1 A0

0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0

1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1

2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2

3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4

5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5

6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6

7-6-5-4-3-2-1-0

Full

n = A0-A8

Cn, Cn+1, Cn+2

Page

(location 0-y)

Cn+3, Cn+4...

Not supported

(y)

...Cn-1,

Cn...

Mode Register Definition Diagram

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the
starting column address, as shown in the Burst Defini-
tion Table.

Reserved*

M3 = 0

Reserved

Full Page

M3 = 1

Reserved

Operating Mode

Standard Operation

All other states reserved

Defined

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Burst Length

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

M6-M0

Op Mode

A10

A11

Write Burst Mode

Programmed Burst Length

Single Location Access

*Should program

M12, M11, M10 = "0, 0, 0"

to ensure compatibility

with future devices.

A12

Burst Length

CAS Latency

Mode Register (Mx)

Address Bus

Op Mode

A10

A11

Reserved* WB

*Should program

M11, M10 = "0, 0"

to ensure compatibility

with future devices.

64MB Module

128MB Module

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

Operating Mode

The normal operating mode is selected by setting

M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.

Test modes and reserved states should not be used

because unknown operation or incompatibility with
future versions may result.

Write Burst Mode

When M9 = 0, the burst length programmed via

M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to READ
bursts, but write accesses are single-location (nonburst)
accesses.

CAS Latency

The CAS latency is the delay, in clock cycles, be-

tween the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.

If a READ command is registered at clock edge n, and

the latency is m clocks, the data will be available by
clock edge n + m. The DQ will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQ will start
driving after T1 and the data will be valid by T2, as
shown in the CAS Latency Diagram. The CAS Latency
Table indicates the operating frequencies at which each
CAS latency setting can be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

CAS Latency

Diagram

CLK

CAS Latency = 3

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

DON'T CARE

UNDEFINED

CLK

CAS Latency = 2

OUT

tOH

COMMAND

NOP

READ

tAC

NOP

CAS Latency

Table

ALLOWABLE OPERATING

FREQUENCY (MHz)

CAS

SPEED

LATENCY = 2

LATENCY = 3

-13E

133

143

-133

100

133

-10E

100

125

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.

2. A0-A11 (64MB), A0-A12 (128MB) define the op-code written to the Mode Register, and should be driven low.
3. A0-A11 (64MB), A0-A12 (128MB) provide device row address. BA0, BA1 determine which device bank is made active.
4. A0-A8 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW

disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.

5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged

and BA0, BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).

TRUTH TABLE SDRAM Commands and DQMB Operation

(Note: 1, notes appear below table)

NAME (FUNCTION)

CS# RAS# CAS# WE# DQMB

ADDR

DQs NOTES

COMMAND INHIBIT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

L/H

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

L/H

Bank/Col Valid

BURST TERMINATE

Active

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or

6, 7

SELF REFRESH (Enter self refresh mode)

LOAD MODE REGISTER

Op-Code

Write Enable/Output Enable

Active

Write Inhibit/Output High-Z

High-Z

Commands

The Truth Table provides a quick reference of avail-

able commands. This is followed by a written descrip-
tion of each command. For a more detailed description

of commands and operations refer to the 128Mb or
256Mb SDRAM datasheets.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

ABSOLUTE MAXIMUM RATINGS*

Voltage on V

, V

Q Supply

Relative to V

.................................. -1V to +4.6V

Voltage on Inputs, NC or I/O Pins

Relative to V

.................................. -1V to +4.6V

Operating Temperature,

A ..........................................................................

0°C to +70°C

Storage Temperature (plastic) ............ -55°C to +150°C
Power Dissipation ................................................... 4W

*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.

DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS

(Notes: 1, 5, 6; notes appear following parameter tables); (V

, V

Q = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS NOTES

SUPPLY VOLTAGE

, V

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

+ 0.3

INPUT LOW VOLTAGE: Logic 0; All inputs

-0.3

0.8

INPUT LEAKAGE CURRENT:
Any input 0V

-20

µA

(All other pins not under test = 0V)

OUTPUT LEAKAGE CURRENT: DQ pins are disabled;

-5

µA

OUT

OUTPUT LEVELS:

2.4

Output High Voltage (I

OUT

= -4mA)

Output Low Voltage (I

OUT

= 4mA)

0.4

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SPECIFICATIONS AND CONDITIONS*: 64MB MODULE

(Notes: 1, 6, 11, 13; notes appear following parameter tables)
(V

, V

Q = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL -13E -133 -10E

UNITS NOTES

OPERATING CURRENT: Active Mode;

640

600

560

3, 18,

Burst = 2; READ or WRITE;

RC =

RC (MIN)

19, 30

STANDBY CURRENT: Power-Down Mode;

All device banks idle; CKE = LOW

STANDBY CURRENT: Active Mode;

200

160

3, 12,

CKE = HIGH; CS# = HIGH; All device banks active after

RCD met;

19, 30

No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst;

660

600

560

3, 18,

READ or WRITE; All device banks active

19, 30

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

1,320 1,240 1,080

3, 12,

CS# = HIGH; CKE = HIGH

RFC = 15.6 µs

18, 19,

30, 31

SELF REFRESH CURRENT: CKE

0.2V

Standard

Low Power

MAX

*DRAM components only.

SPECIFICATIONS AND CONDITIONS*: 128MB MODULE

(Notes: 1, 6, 11, 13; notes appear following parameter tables)
(V

, V

Q = +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL -13E -133

-10E

UNITS NOTES

OPERATING CURRENT: Active Mode;

540

500

3, 18,

Burst = 2; READ or WRITE;

RC =

RC (MIN)

19, 30

STANDBY CURRENT: Power-Down Mode;

All device banks idle; CKE = LOW

STANDBY CURRENT: Active Mode;

160

3, 12,

CKE = HIGH; CS# = HIGH; All device banks active after

RCD met;

19, 30

No accesses in progress

OPERATING CURRENT: Burst Mode; Continuous burst;

540

3, 18,

READ or WRITE; All device banks active

19, 30

AUTO REFRESH CURRENT

RFC =

RFC (MIN)

1,140 1,080 1,080

3, 12,

CS# = HIGH; CKE = HIGH

RFC = 7.81 µs

18, 19,

30, 31

SELF REFRESH CURRENT: CKE

0.2V

Standard

Low Power

MAX

*DRAM components only.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

*Module AC timing parameters comply with PC133 Design Specs, based on component parameters.

ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS*

(Notes: 5, 6, 8, 9, 11; notes appear following parameter tables)

AC CHARACTERISTICS

-13E

-133

-10E

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

NOTES

Access time from

CL = 3

AC(3)

5.4

CLK (pos. edge)

CL = 2

AC(2)

5.4

Address hold time

0.8

Address setup time

1.5

CLK high-level width

2.5

CLK low-level width

2.5

Clock cycle time

CL = 3

CK(3)

7.5

CL = 2

CK(2)

7.5

CKE hold time

CKH

0.8

CKE setup time

CKS

1.5

CS#, RAS#, CAS#, WE#, DQM hold time

CMH

0.8

CS#, RAS#, CAS#, WE#, DQM setup time

CMS

1.5

Data-in hold time

0.8

Data-in setup time

1.5

Data-out high-impedance time

CL = 3

HZ(3)

5.4

CL = 2 (64MB)

HZ(2)

5.4

CL = 2 (128MB)

HZ(2)

5.4

Data-out low-impedance time

Data-out hold time (load)

Data-out hold time (no load)

1.8

ACTIVE to PRECHARGE command

RAS

120,000

ACTIVE to ACTIVE command period

ACTIVE to READ or WRITE delay

RCD

Refresh period

REF

AUTO REFRESH period

RFC

PRECHARGE command period

ACTIVE bank a to ACTIVE bank b command

RRD

Transition time

0.3

1.2

0.3

1.2

0.3

1.2

WRITE recovery time

1 CLK +

7ns

7.5ns

7ns

Exit SELF REFRESH to ACTIVE command

XSR

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

AC FUNCTIONAL CHARACTERISTICS

(Notes: 5, 6, 7, 8, 9, 11; notes appear following parameter tables)

PARAMETER

SYMBOL -13E

-133

-10E UNITS NOTES

READ/WRITE command to READ/WRITE command

CCD

CKE to clock disable or power-down entry mode

CKED

CKE to clock enable or power-down exit setup mode

PED

DQM to input data delay

DQD

DQM to data mask during WRITEs

DQM

DQM to data high-impedance during READs

DQZ

WRITE command to input data delay

DWD

Data-in to ACTIVE command

DAL

15, 21

Data-in to PRECHARGE command

DPL

16, 21

Last data-in to burst STOP command

BDL

Last data-in to new READ/WRITE command

CDL

Last data-in to PRECHARGE command

RDL

16, 21

LOAD MODE REGISTER command to ACTIVE or REFRESH command

MRD

Data-out to high-impedance from PRECHARGE command

CL = 3

ROH(3)

CL = 2

ROH(2)

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

14. Timing actually specified by

CKS; clock(s) speci-

fied as a reference only at minimum cycle rate.

15. Timing actually specified by

WR plus

RP; clock(s)

specified as a reference only at minimum cycle rate.

16. Timing actually specified by

WR.

17. Required clocks are specified by JEDEC functional-

ity and are not dependent on any timing param-
eter.

18. The I

current will increase or decrease propor-

tionally according to the amount of frequency
alteration for the test condition.

19. Address transitions average one transition every

two clocks.

20. CLK must be toggled a minimum of two times

during this period.

21. Based on

CK = 10ns for -10E, and

CK = 7.5ns for

-133 and -13E.

22. V

overshoot: V

(MAX) = V

Q + 2V for a pulse

width

3ns, and the pulse width cannot be greater

than one third of the cycle rate. V

undershoot: V

(MIN) = -2V for a pulse width

3ns.

23. The clock frequency must remain constant (stable

clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including

WR, and PRECHARGE commands). CKE may be

used to reduce the data rate.

24. Auto precharge mode only. The precharge timing

budget (

RP) begins 7ns for -13E; 7.5ns for -133 and

7ns for -10E after the first clock delay, after the last
WRITE is executed. May not exceed limit set for
precharge mode.

25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.

AC for -133/-13E at CL = 3 with no load is 4.6ns and

is guaranteed by design.

28. Parameter guaranteed by design.
29. The value of

RAS in -13E speed grade module SPDs

is calculated from

RC -

RP = 45ns.

30. For -10E, CL= 2 and

CK = 10ns; for -133, CL = 3 and

CK = 7.5ns; for -13E, CL = 2 and

CK = 7.5ns.

31. CKE is HIGH during refresh command period

RFC (MIN) else CKE is LOW. The I

6 limit is

actually a nominal value and does not result in a
fail value.

NOTES

All voltages referenced to V

This parameter is sampled. V

, V

Q = +3.3V;

f = 1 MHz, T

= 25°C; pin under test biased at 1.4V.

is dependent on output loading and cycle rates.

Specified values are obtained with minimum cycle
time and the outputs open.

Enables on-chip refresh and address counters.

The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured (0°C

+70°C).

An initial pause of 100µs is required after power-up,
followed by two AUTO REFRESH commands, be-
fore proper device operation is ensured. (V

and

Q must be powered up simultaneously. V

and

Q must be at same potential.) The two AUTO

REFRESH command wake-ups should be repeated
any time the

REF refresh requirement is exceeded.

AC characteristics assume

T = 1ns.

In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between V

and V

(or between V

and V

) in a monotonic

manner.

Outputs measured at 1.5V with equivalent load:

50pF

10.

HZ defines the time at which the output achieves

the open circuit condition; it is not a reference to
V

or V

. The last valid data element will meet

OH before going High-Z.

11. AC timing and I

tests have V

= 0V and V

= 3V,

with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V

(MAX) and V

(MIN)

and no longer at the 1.5V crossover point.

12. Other input signals are allowed to transition no

more than once every two clocks and are otherwise
at valid V

or V

levels.

13. I

specifications are tested after the device is

properly initialized.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SCL

SDA

DATA STABLE

DATA
CHANGE

Figure 1

Data Validity

SCL

SDA

START
BIT

STOP
BIT

Figure 2

Definition of Start and Stop

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

Figure 3

Acknowledge Response From Receiver

SPD CLOCK AND DATA CONVENTIONS

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figures 1 and 2).

SPD START CONDITION

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors
the SDA and SCL lines for the start condition and will
not respond to any command until this condition has
been met.

SPD STOP CONDITION

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD ACKNOWLEDGE

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).

The SPD device will always respond with an ac-

knowledge after recognition of a start condition and its
slave address. If both the device and a WRITE operation
have been selected, the SPD device will respond with an
acknowledge after the receipt of each subsequent eight-
bit word. In the read mode the SPD device will transmit
eight bits of data, release the SDA line and monitor the
line for an acknowledge. If an acknowledge is detected
and no stop condition is generated by the master, the
slave will continue to transmit data. If an acknowledgeis
not detected, the slave will terminate further data
transmissions and await the stop condition to return to
standby power mode.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

SPD EEPROM TIMING DIAGRAM

SYMBOL

MIN

MAX

UNITS

0.3

3.5

µs

BUF

4.7

µs

300

HD:DAT

µs

HD:STA

µs

SYMBOL

MIN

MAX

UNITS

HIGH

µs

LOW

4.7

µs

SU:DAT

250

SU:STA

4.7

µs

SU:STO

4.7

µs

SERIAL PRESENCE-DETECT EEPROM TIMING PARAMETERS

EEPROM Device Select Code

(The most significant bit (b7) is sent first)

Device Type Identifier

Chip Enable

Memory Area Select Code (two arrays)

Protection Register Select Code

EEPROM Operating Modes

(X = V

or V

)

MODE

RW Bit

BYTES

Initial Sequence

Current Address Read

Start, Device Select, RW = 1

Random Address Read

Start, Device Select, RW = 0, Address

reSTART, Device Select, RW = 1

Sequential Read

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = 0

Page Write

START, Device Select, RW = 0

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

x 0.7

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

x 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT:

µA

SCL = SDA = V

- 0.3V; All other inputs = GND or 3.3V +10%

POWER SUPPLY CURRENT:

SCL clock frequency = 100 KHz

SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS

(Notes: 1) (V

= +3.3V ±0.3V)

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.3

3.5

µs

Time the bus must be free before a new transition can start

BUF

4.7

µs

Data-out hold time

300

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

µs

Clock HIGH period

HIGH

µs

Noise suppression time constant at SCL, SDA inputs

100

Clock LOW period

LOW

4.7

µs

SDA and SCL rise time

µs

SCL clock frequency

SCL

100

KHz

Data-in setup time

SU:DAT

250

Start condition setup time

SU:STA

4.7

µs

Stop condition setup time

SU:STO

4.7

µs

WRITE cycle time

WRC

NOTE: 1. All voltages referenced to V

2. Timing actually specified by

WR.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SERIAL PRESENCE-DETECT MATRIX

(Note: 1)

BYTE

DESCRIPTION

ENTRY (VERSION)

MT4LSDT864(L)W

MT4LSDT1664(L)W

NUMBER OF BYTES USED BY MICRON

128

TOTAL NUMBER OF SPD MEMORY BYTES

256

MEMORY TYPE

SDRAM

NUMBER OF ROW ADDRESSES

12 or 13

NUMBER OF COLUMN ADDRESSES

NUMBER OF MODULE BANKS

MODULE DATA WIDTH

MODULE DATA WIDTH (continued)

MODULE VOLTAGE INTERFACE LEVELS

LVTTL

SDRAM CYCLE TIME,

7 (-13E)

(CAS LATENCY = 3)

7.5 (-133)

8 (-10E)

SDRAM ACCESS FROM CLK,

5.4 (-13E/-133)

(CAS LATENCY = 3)

6 (-10E)

MODULE CONFIGURATION TYPE

NONPARITY

REFRESH RATE/TYPE

15.6µs or 7.81µs/SELF

SDRAM WIDTH (PRIMARY SDRAM)

ERROR-CHECKING SDRAM DATA WIDTH

NONE

MINIMUM CLOCK DELAY FROM BACK-TO-BACK

RANDOM COLUMN ADDRESSES,

CCD

BURST LENGTHS SUPPORTED

1, 2, 4, 8, PAGE

NUMBER OF BANKS ON SDRAM DEVICE

CAS LATENCIES SUPPORTED

2, 3

CS LATENCY

WE LATENCY

SDRAM MODULE ATTRIBUTES

UNBUFFERED

SDRAM DEVICE ATTRIBUTES: GENERAL

SDRAM CYCLE TIME ,

7.5 (13E)

(CAS LATENCY = 2)

10 (-133/-10E)

SDRAM ACCESS FROM CLK,

54 (-13E)

(CAS LATENCY = 2)

6 (-133/-10E)

SDRAM CYCLE TIME,

(CAS LATENCY = 1)

SDRAM ACCESS FROM CLK,

(CAS LATENCY = 1)

MINIMUM ROW PRECHARGE TIME,

15 (-13E)

20 (-133/-10E)

MINIMUM ROW ACTIVE TO ROW ACTIVE,

RRD

14 (-13E)

15 (-133)

20 (-10E)

MINIMUM RAS# TO CAS# DELAY,

RCD

15 (-13E)

20 (-133/-10E)

MINIMUM RAS# PULSE WIDTH,

RAS

45 (-13E)

(Note 2)

44 (133)

50 (-10E)

NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."

2. The value of

RAS used for -13E modules is calculated from

RC -

RP. Acutal device spec. value is 37ns.

8, 16 Meg x 64 SDRAM MICRDIMM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD4C8_16x64WG_A.p65 Rev. A; Pub. 6/01

64MB, 128MB (x64)

144-PIN SDRAM MICRO DIMM

SERIAL PRESENCE-DETECT MATRIX (continued)

(Note: 1, 2)

BYTE

DESCRIPTION

ENTRY (VERSION)

MT4LSDT864(L)W

MT4LSDT1664(L)W

MODULE BANK DENSITY

64MB or 128MB

COMMAND AND ADDRESS SETUP TIME,

AS,

1.5 (-13E/-133)

CMS

2 (-10E)

COMMAND AND ADDRESS HOLD TIME,

AH,

0.8 (-13E/-133)

CMH

1 (-10E)

DATA SIGNAL INPUT SETUP TIME,

1.5 (-13E/-133)

2 (-10E)

DATA SIGNAL INPUT HOLD TIME,

0.8 (-13E/-133)

1 (-10E)

36-61

RESERVED

SPD REVISION

REV. 1.2

CHECKSUM FOR BYTES 0-62

(-13E)

(-133)

(-10E)

MANUFACTURER'S JEDEC ID CODE

MICRON

65-71

MANUFACTURER'S JEDEC ID CODE (CONT.)

MANUFACTURING LOCATION

73-90

MODULE PART NUMBER (ASCII)

PCB IDENTIFICATION CODE

IDENTIFICATION CODE (CONT.)

YEAR OF MANUFACTURE IN BCD

WEEK OF MANUFACTURE IN BCD

95-98

MODULE SERIAL NUMBER

99-125 MANUFACTURER-SPECIFIC DATA (RSVD)

126

SYSTEM FREQUENCY

100 MHz (-13E/-133/-10E)

127

SDRAM COMPONENT & CLOCK DETAIL

NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."

2. x = Variable Data.

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