PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb ZBT

SRAM

MT55L1MY18F, MT55V1MV18F,
MT55L512Y32F, MT55V512V32F,
MT55L512Y36F, MT55V512V36F

3.3V V

, 3.3V or 2.5V I/O; 2.5V V

, 2.5V I/O

Features

· High frequency and 100 percent bus utilization
· Single 3.3V ±5 percent or 2.5V ±5 percent power

supply

· Separate 3.3V ±5 percent or 2.5V ±5 percent isolated

output buffer supply (V

· Advanced control logic for minimum control signal

interface

· Individual byte write controls may be tied LOW
· Single R/W# (read/write) control pin/ball
· CKE# pin/ball to enable clock and suspend

operations

· Three chip enables for simple depth expansion
· Clock-controlled and registered addresses, data

I/Os, and control signals

· Internally self-timed, fully coherent write
· Internally self-timed, registered outputs to

eliminate the need to control OE#

· SNOOZE MODE for reduced-power standby
· Common data inputs and data outputs
· Linear or Interleaved Burst Modes
· Burst feature (optional)
· Pin and ball/function compatibility with 2Mb, 4Mb,

and 8Mb ZBT SRAM

Part Number Example:

MT55L512Y36FT-11

General Description

The Micron

Zero Bus Turnaround

(ZBT

) SRAM

family employs high-speed, low-power CMOS designs
using an advanced CMOS process.

Micron's 18Mb ZBT SRAMs integrate a 1 Meg x 18,

512K x 32, or 512K x 36 SRAM core with advanced syn-
chronous peripheral circuitry and a 2-bit burst
counter. These SRAMs are optimized for 100 percent
bus utilization, eliminating any turnaround cycles for
READ to WRITE, or WRITE to READ, transitions. All
synchronous inputs pass through registers controlled
by a positive-edge-triggered single clock input (CLK).
The synchronous inputs include all addresses, all data
inputs, chip enable (CE#), two additional chip enables

Options

TQFP

Marking

· Timing (Access/Cycle/MHz)

6.5ns/8.8ns/113 MHz

-8.8

7.5ns/10ns/100 MHz

-10

8.5ns/11ns/90 MHz

-11

· Configurations

3.3V V

, 3.3V or 2.5V I/O

1 Meg x 18

MT55L1MY18F

512K x 32

MT55L512Y32F

512K x 36

MT55L512Y36F

2.5V V

, 2.5V I/O

1 Meg x 18

MT55V1MV18F

512K x 32

MT55V512V32F

512K x 36

MT55V512V36F

· Packages

100-pin TQFP

165-ball, 13mm x 15mm FBGA

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron's Web site--

http://www.micron.com/numberguide.

· Operating Temperature Range

Commercial (0ºC

£ T

£ +70ºC)

None

Industrial (-40ºC

£ T

£ +85ºC)

2. Contact Factory for availability of Industrual Temperature

devices.

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

Figure 2: 165-Ball FBGA

JEDEC-Standard MS-216 (Var. CAB-1)

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

for easy depth expansion (CE2, CE2#), cycle start input
(ADV/LD#), synchronous clock enable (CKE#), byte
write enables (BWa#, BWb#, BWc#, and BWd#), and
read/write (R/W#).

Asynchronous inputs include the output enable

(OE#, which may be tied LOW for control signal mini-
mization), clock (CLK) and snooze enable (ZZ, which
may be tied LOW if unused). There is also a burst mode
pin/ball (MODE) that selects between interleaved and
linear burst modes. MODE may be tied HIGH, LOW or
left unconnected if burst is unused. The data out (Q) is
enabled by OE#. WRITE cycles can be from one to four
bytes wide as controlled by the write control inputs.

All READ, WRITE, and DESELECT cycles are initi-

ated by the ADV/LD# input. Subsequent burst
addresses can be internally generated as controlled by
the burst advance pin/ball (ADV/LD#). Use of burst
mode is optional. It is allowable to give an address for
each individual READ and WRITE cycle. BURST cycles
wrap around after the fourth access from a base
address.

To allow for continuous, 100 percent use of the data

bus, the flow-through ZBT SRAM uses a LATE WRITE
cycle. For example, if a WRITE cycle begins in clock

cycle one, the address is present on rising edge one.
BYTE WRITEs need to be asserted on the same cycle as
the address. The write data associated with the address
is required one cycle later, or on the rising edge of
clock cycle two.

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes
to be written. During a BYTE WRITE cycle, BWa# con-
trols DQa pins/balls; BWb# controls DQb pins/balls;
BWc# controls DQc pins/balls; and BWd# controls
DQd pins/balls. Cycle types can only be defined when
an address is loaded, i.e., when ADV/LD# is LOW. Par-
ity/ECC bits are only available on the x 18 and x36 ver-
sions.

The device is ideally suited for systems requiring

high bandwidth and zero bus turnaround delays.

Please refer to Micron's Web site (

www.micron.com/

sramds

) for the latest data sheet.

Dual Voltage I/O

The 3.3V V

device is tested for 3.3V and 2.5V I/O

function. The 2.5V V

device is tested for only 2.5V

I/O function.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 3: Functional Block Diagram

1 Meg x 18

Figure 4: Functional Block Diagram

512K x 32/36

NOTE:

Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and tim-
ing diagrams for detailed information.

DQs
DQPa
DQPb

SA0, SA1, SA

MODE

BWa#

BWb#

R/W#

CE#
CE2

CE2#

OE#

READ LOGIC

D
A

S
T
E
E

N
G

O
U

T
P

F
F
E

1 Meg x 9 x 2

MEMORY

ARRAY

ADDRESS
REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

SA0'

SA1'

D1
D0

Q1
Q0

SA0

SA1

ADV/LD#

S
E

P
S

CLK

CKE#

WRITE

DRIVERS

WRITE ADDRESS

INPUT

MODE

BWa#

BWb#

R/W#

CE#
CE2

CE2#

OE#

READ LOGIC

DQs
DQPa
DQPb
DQPc
DQPd

512K x 8 x 4

(x32)

512K x 9 x 4

(x36)

MEMORY

ARRAY

INPUT

BWc#

BWd#

ADDRESS
REGISTER

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

BURST

LOGIC

SA0'

SA1'

D1
D0

Q1
Q0

SA0

SA1

ADV/LD#

CLK

CKE#

WRITE

DRIVERS

D
A

S
T
E
E

N
G

O
U

T
P

F
F
E

S
E

P
S

WRITE ADDRESS

SA0, SA1, SA

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 5: Pin Layout (Top View)

100-Pin TQFP

NOTE:

1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Pins 14 and 66 do not have to be connected directly to V

if the input voltage is

£ V

3. Pin 16 does not have to be connected directly to V

if the input voltage is

³ V

4. Pins 43 and 42 are reserved for address expansion; 36Mb and 72Mb, respectively.

SA
SA
SA
SA

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

CE2#

BWa#

BWb#

NC
NC

CE2
CE#

SA
SA

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

DQPa

DQa

SA
SA
SA
SA
SA
SA
SA

DNU

DNU
DNU

SA0
SA1
SA
SA
SA
SA

MODE
(LBO#)

DQb

DQPb

x18

SA
SA
SA
SA

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

CE2#

BWa#

BWb#

BWc#

BWd#

CE2
CE#

SA
SA

81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NF/

DQPb

DQb

DQa

NF/

DQPa

SA
SA
SA
SA
SA
SA
SA

DNU

DNU
DNU

SA0
SA1
SA
SA
SA
SA

MODE
(LBO#)

NF/

DQPc

DQc

DQd

NF/

DQPd

x32/x36

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 1:

TQFP Pin Descriptions

SYMBOL

TYPE

DESCRIPTION

ADV/LD#

Input

Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.

BWa#

BWb#

BWc#

BWd#

Input

Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written when a WRITE cycle is active and must meet the setup and hold times around the
rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb#
controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW).

CE2#

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.

CKE#

Input

Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the
device. When CKE is HIGH, the device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet setup and hold times around the rising
edge of CLK.

CLK

Input

Clock: This signal registers the address, data, chip enables, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock's rising edge.

MODE (LBO#)

Input

Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or
HIGH on this pin selects interleaved burst. Do not alter input state while device is operating.
LBO# is the JEDEC-standard term for MODE.

OE# (G#)

Input

Output Enable: This

active LOW, asynchronous input enables the data I/O output drivers. G#

is the JEDEC-standard term for OE#.

R/W#

Input

Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only
means for determining READs and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE
operations and must meet the setup and hold times around the rising edge of CLK. Full bus-
width WRITEs occur if all byte write enables are LOW.

SA0
SA1

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold
times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of
the address field and set the internal burst counter if burst is desired.

Input

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This pin has an internal pull-down and can be left unconnected.

DQa
DQb

DQc

DQd

Input/

Output

SRAM Data I/Os: Byte "a" is associated with DQa pins; byte "b" is associated with DQb pins;
byte "c" is associated with DQc pins; byte "d" is associated with DQd pins. Input data must
meet setup and hold times around the rising edge CLK.

NF/

DQPa

NF/

DQPb

NF/

DQPc

NF/

DQPd

I/O

No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18
version, byte "a" parity is DQPa; byte "b" parity is DQPb. On the x36 version, byte "a" parity
is DQPa; byte "b" parity is DQPb; byte "c" parity is DQPc; byte "d" parity is DQPd.

Supply

Power Supply:

See DC Electrical Characteristics and Operating Conditions for range.

Supply

Isolated Output Buffer Supply:

See DC Electrical Characteristics and Operating Conditions for

range.

Supply

Ground:

GND.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 6: Ball Layout (Top View)

165-Ball FBGA

x18

x32/x36

NOTE:

1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.
2. Balls 2R and 2P are reserved for address expansion; 36Mb and 72Mb, respectively.

CE#

CE2

DQb

DQPb

MODE

(LBO#)

BWb#

BWa#

TDI

TMS

CE2#

CLK

SA1

SA0

CKE#

R/W#

TDO

TCK

ADV/LD#

OE# (G#)

DQa

DQPa

DQa

TOP VIEW

CE#

CE2

DQc

DQd

NF/

DQPc

DQc

DQd

NF/

DQPd

MODE

(LBO#)

BWc#

BWd#

BWb#

BWa#

TDI

TMS

CE2#

CLK

SA1

SA0

CKE#

R/W#

TDO

TCK

ADV/LD#

OE# (G#)

DQb

DQa

NF/

DQPb

DQb

DQa

/DQPa

TOP VIEW

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 2:

FBGA Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

ADV/LD#

Input

Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. When ADV/LD# is
HIGH, R/W# is ingored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.

BWa#

BWb#

BWc#

BWd#

Input

Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written when a WRITE cycle is active and must meet the setup and hold times around the
rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are
associated with addresses and apply to subsequent data. BWa# controls DQa balls; BWb#
controls DQb balls; BWc# controls DQc balls; BWd# controls DQd balls.

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW).

CE2#

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled
only when a new external address is loaded (ADV/LD# LOW). This input can be used for
memory depth expansion.

CE2

Input

CKE#

Input

Synchronous Clock Enable: This active LOW input permits CLK to propogate throughout the
device. When CKE# is HIGH, the device ignores the CLK input and effectively internally
extends the previous CLK cycle. This input must meet the setup and hold times around the
rising edge of CLK.

CLK

Input

Clock: This signal registers the address, data, chip enable, byte write enables, and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock's rising edge.

MODE (LB0#)

Input

Mode: This input selects the burst sequence. A LOW on this input selects "linear burst." NC or
HIGH on this input selects "interleaved burst." Do not alter input state while device is
operating. LBO# is the JEDEC-standard term for MODE.

OE#(G#)

Input

Output Enable: This

active LOW, asynchronous input enables the data I/O output drivers. G#

is the JEDEC-standard term for OE#.

R/W#

Input

Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only
means for determining READs and WRITEs. READ cycles may not be converted into WRITEs
(and vice versa) other than by loading a new address. A LOW on this ball permits BYTE WRITE
operations to meet the setup and hold times around the rising edge of CLK. Full bus-width
WRITEs occur if all byte write enables are LOW.

SA0
SA1

Input

TMS

TDI

TCK

Input

IEEE 1149.1 Test Inputs: JEDEC-standard 3.3V and 2.5V I/O levels. These balls may be left not
connected if the JTAG function is not used in the circuit.

Input

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power
standby mode in which all data in the memory array is retained. When ZZ is active, all other
inputs are ignored. This ball has an internal pull-down and can be left unconnected.

DQa
DQb

DQc

DQd

Input/

Output

SRAM Data I/Os: For the x18 version, byte "a" is associated with DQa balls; byte "b" is
associated with DQb balls. For the x32 and x36 versions, byte "a" is associated with DQa
balls; byte "b" is associated with DQb balls; byte "c" is associated with DQc balls; byte "d" is
associated with DQd balls. Input data must meet setup and hold times around the rising
edge of CLK.

NF/

DQPa

NF/

DQPb

NF/

DQPc

NF/

DQPd

I/O

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

TDO

Output

IEEE 1149.1 Test Output: JEDEC-standard 3.3V and 2.5V I/O levels.

Supply

Power Supply:

See DC Electrical Characteristics and Operating Conditions for range.

Supply

Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for
range.

Supply

Ground:

GND.

No Connect: These balls are not internally connected to the die. They may be left floating,
driven by signals, or connected to ground to improve package heat dissipation.

No Function: These balls are internally connected to the die and have the capacitance of an
input pin. They may be left floating, driven by signals, or connected to ground to improve
package heat dissipation.

Table 2:

FBGA Ball Descriptions (continued)

SYMBOL

TYPE

DESCRIPTION

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

NOTE:

Using R/W# and byte write(s), any one or more bytes may be written.

NOTE:

Using R/W# and byte write(s), any one or more bytes may be written.

Table 3:

Interleaved Burst Address Table (Mode = NC or HIGH)

FIRST ADDRESS

(EXTERNAL)

SECOND ADDRESS

(INTERNAL)

THIRD ADDRESS

(INTERNAL)

FOURTH ADDRESS

(INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

Table 4:

Linear Burst Address Table (Mode = LOW)

FIRST ADDRESS

(EXTERNAL)

SECOND ADDRESS

(INTERNAL)

THIRD ADDRESS

(INTERNAL)

FOURTH ADDRESS

(INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

Table 5:

Partial Truth Table for READ/WRITE Commands (x18)

FUNCTION

R/W#

BWa#

BWb#

READ

WRITE Byte "a"

WRITE Byte "b"

WRITE All Byte

WRITE ABORT/NOP

Table 6:

Partial Truth Table for READ/WRITE Commands (x32/x36)

FUNCTION

R/W#

BWa#

BWb#

BWc#

BWd#

READ

WRITE Byte "a"

WRITE Byte "b"

WRITE Byte "c"

WRITE Byte "d"

WRITE All Byte

WRITE ABORT/NOP

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 7:

State Diagram For ZBT SRAM

NOTE:

1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the

clock (CLK) input and does not change the state of the device.

2. States change on the rising edge of the clock (CLK).

DESELECT

BEGIN

READ

BURST

READ

BEGIN

WRITE

BURST

WRITE

READ

WRITE

BURST

READ

WRITE

READ

BURST

READ

BURST

WRITE

KEY:

COMMAND
DS
READ
WRITE
BURST

OPERATION
DESELECT
New READ
New WRITE
BURST READ,
BURST WRITE, or
CONTINUE DESELECT

BURST

READ

WRITE

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

NOTE:

1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ

or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT
cycle is executed first.

2. DUMMY READ and WRITE ABORT can be considered NOPs because the device performs no external operation. A

WRITE ABORT means a WRITE command is given, but no operation is performed.

3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn

off the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet
an application's requirements.

4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it

occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the
IGNORE CLOCK EDGE cycle.

5. X means "Don't Care." H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,

BWc#, and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.

6. BWa# enables WRITEs to byte "a" (DQa pins/balls); BWb# enables WRITEs to byte "b" (DQb pins/balls); BWc#

enables WRITEs to byte "

" (DQc pins/balls); BWd# enables WRITEs to byte "d" (DQd pins/balls).

7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
8. Wait states are inserted by setting CKE# HIGH.
9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.
11. The address counter is incremented for all CONTINUE BURST CYCLES.

Table 7:

Truth Table

Notes: 510

OPERATION

ADDRESS

USED

CE#

CE2#

CE2

ADV/

LD#

R/W# BWx

OE#

CKE#

CLK

NOTES

DESELECT CYCLE

None

®H High-Z

DESELECT Cycle

None

®H High-Z

DESELECT Cycle

None

®H High-Z

CONTINUE
DESELECT Cycle

None

®H High-Z

READ Cycle (Begin
Burst)

External

®H

READ Cycle
(Continue Burst)

®H

1, 11

NOP/DUMMY READ
(Begin Burst)

External

®H High-Z

DUMMY READ
(Continue Burst)

®H High-Z 1, 2, 11

WRITE Cycle (Begin
Burst)

External

®H

WRITE Cycle
(Continue Burst)

®H

1, 3, 11

NOP/WRITE ABORT
(Begin Burst)

None

®H High-Z

2, 3

WRITE ABORT
(Continue Burst)

®H High-Z 1, 2, 3,

IGNORE CLOCK
EDGE (Stall)

Current

®H

SNOOZE MODE

None

High-Z

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Absolute Maximum Ratings
3.3V V

Voltage on V

Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . . . -0.5V to +4.6V

Voltage on V

Q Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . . . . .-0.5V to V

(DQs) . . . . . . . . . . . . . . . . . . . . . -0.5V to V

Q + 0.5V

(Inputs) . . . . . . . . . . . . . . . . . . . . -0.5V to V

+ 0.5V

Storage Temperature (TQFP) . . . . . . . . .-55°C to +150°C
Storage Temperature (FBGA) . . . . . . . . .-55°C to +125°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Short Circuit Output Current . . . . . . . . . . . . . . . . .100mA

2.5V V

Voltage on V

Supply

Relative to V

. . . . . . . . . . . . . . . . . . . . . . . -0.3V to +3.6V

Voltage on V

Q Supply Relative

to V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +3.6V

(DQs) . . . . . . . . . . . . . . . . . . . . . -0.3V to V

Q + 0.3V

(Inputs) . . . . . . . . . . . . . . . . . . . . -0.3V to V

+ 0.3V

Storage Temperature (TQFP) . . . . . . . . .-55°C to +150°C
Storage Temperature (FBGA)

-55°C to +125°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
Short Circuit Output Current . . . . . . . . . . . . . . . . .100mA

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Junction temperature depends upon package type,

cycle time, loading, ambient temperature, and airflow.

Table 8:

3.3V V

, 3.3V I/0 DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 18; 0ºC

£ T

£ +70ºC; V

and V

Q = 3.3V ±0.165V unless otherwise

noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

2.0

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.8

1, 2

Input Leakage Current

£ V

-1.0

1.0

µA

Output Leakage Current

Output(s) disabled,

£ V

-1.0

1.0

µA

Output High Voltage

= -4.0mA

2.4

Output Low Voltage

= 8.0mA

0.4

Supply Voltage

3.135

3.465

Isolated Output Buffer Supply

3.135

1, 5

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 9:

3.3V V

, 2.5V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 18; 0ºC

£ T

£ +70ºC; V

= 3.3V ±0.165V and V

Q = 2.5V ±0.125V unless

otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Data bus (DQx)

1.7

Q + 0.3

1, 2

Inputs

1.7

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.7

1, 2

Input Leakage Current

£ V

-1.0

1.0

µA

Output Leakage Current

Output(s) disabled,

£ V

Q (DQ

)

-1.0

1.0

µA

Output High Voltage

= -2.0mA

1.7

= -1.0mA

2.0

Output Low Voltage

= 2.0mA

0.7

= 1.0mA

0.4

Supply Voltage

3.135

3.465

Isolated Output Buffer Supply

2.375

2.625

1, 5

Table 10: 2.5V V

, 2.5V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 18; 0ºC

£ T

£ +70ºC; V

and V

Q = 2.5V ±0.125V unless otherwise

noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Data bus (DQx)

1.7

Q + 0.3

1, 3

Inputs

1.7

+ 0.3

1, 3

Input Low (Logic 0) Voltage

-0.3

0.7

1, 3

Input Leakage Current

£ V

-1.0

1.0

µA

Output Leakage Current

Output(s) disabled,

£ V

Q (DQ

)

-1.0

1.0

µA

Output High Voltage

= -2.0mA

1.7

= -1.0mA

2.0

Output Low Voltage

= 2.0mA

0.7

= 1.0mA

0.4

Supply Voltage

2.375

2.625

Isolated Output Buffer Supply

2.375

2.625

1, 5

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 11: TQFP Capacitance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

Control Input Capacitance

= 25°C; f = 1 MHz

= 3.3V

4.2

Input/Output Capacitance (DQ)

3.5

Address Input Capacitance

Clock Capacitance

4.2

Table 12: FBGA Capacitance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

Control Input Capacitance

= 25°C; f = 1 MHz

= 3.3V

Input/Output Capacitance (DQ)

4.5

Address Input Capacitance

Clock Capacitance

5.5

Table 13: TQFP Thermal Resistance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

Junction to Ambient
(Airflow if 1m/s, two-layer
board)

Test conditions follow standard test methods

and procedures for measuring thermal impedance, per

EIA/JESD51.

28.9

°C/W

Junction to Case (Top)

4.2

°C/W

Table 14: FBGA Thermal Resistance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

Junction to Ambient
(Airflow if 1m/s, two-layer
board)

Test conditions follow standard test methods

and procedures for measuring thermal impedance, per

EIA/JESD51.

°C/W

Junction to Case (Top)

1.7

°C/W

Junction to Board (Bottom)

10.4

°C/W

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 15: 3.3V V

, I

Operating Conditions and Maximum Limits

(1 Meg x 18 and 512K x 32/36)

Notes appear following parameter tables on page 18; 0ºC

£ T

£ +70ºC; V

and V

Q = 3.3V ±0.165V or 2.5V ±0.125V

unless otherwise noted

MAX

DESCRIPTION

CONDITIONS

SYM

TYP

-8.8

-10

-11

UNITS NOTES

Power Supply
Current: Operating

Device selected; All inputs

£ V

³ V

; Cycle time

KC (MIN);

= MAX; Outputs open

280

330

315

300

6, 7, 8

Power Supply
Current: Idle

Device selected; V

= MAX;

CKE#

³ V

; All inputs

£ V

+ 0.2

³ V

- 0.2; Cycle time

KC (MIN)

DD1

100

150

140

130

6, 7, 8

CMOS Standby

Device deselected; V

= MAX;

All inputs

£ V

+ 0.2 or

³ V

- 0.2;

All inputs static; CLK frequency = 0

SB2

7, 8

Clock Running

Device deselected; V

= MAX;

ADV/LD#

³ V

; All inputs

£ V

+ 0.2

³ V

- 0.2; Cycle time

KC (MIN)

SB4

100

150

140

130

7, 8

Snooze Mode

³ V

SB2Z

Table 16: 2.5V V

, I

Operating Conditions and Maximum Limits

(1 Meg x 18 and 512K x 32/36)

Notes appear following parameter tables on page 18; 0ºC

£ T

£ +70ºC; V

and V

Q = 2.5V ±0.125V unless otherwise

noted

MAX

DESCRIPTION

CONDITIONS

SYM

TYP

-8.8

-10

-11

UNITS NOTES

Power Supply
Current: Operating

Device selected; All inputs

£ V

³ V

; Cycle time

KC (MIN);

= MAX; Outputs open

180

220

210

200

6, 7, 9

Power Supply
Current: Idle

Device selected; V

= MAX;

CKE#

³ V

; All inputs

£ V

+ 0.2

³ V

- 0.2; Cycle time

KC (MIN)

DD1

120

110

100

6, 7, 9

CMOS Standby

Device deselected; V

= MAX;

All inputs

£ V

+ 0.2 or

³ V

- 0.2;

All inputs static; CLK frequency = 0

SB2

7, 9

Clock Running

Device deselected; V

= MAX;

ADV/LD#

³ V

; All inputs

£ V

+ 0.2 or

³ V

- 0.2; Cycle time

KC (MIN)

SB4

120

110

100

7, 9

Snooze Mode

³ V

SB2Z

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 17: AC Electrical Characteristics and Recommended Operating Conditions

Notes 1113; notes appear following parameter tables on page 18; 0ºC

£ T

£ +70ºC; T

£ 95ºC (commercial); T

£ 110ºC

(industrial); V

= 3.3V ±0.165V unless otherwise noted

DESCRIPTION

SYMBOL

-8.8

-10

-11

UNITS

NOTES

MIN

MAX

MIN

MAX

MIN

MAX

Clock

Clock cycle time

KHKH

8.8

10.0

11.0

Clock frequency

113

100

MHz

Clock HIGH time

KHKL

2.5

3.0

Clock LOW time

KLKH

2.5

3.0

Output Times

Clock to output valid

KHQV

6.5

7.5

8.5

Clock to output invalid

KHQX

2.5

3.0

Clock to output in Low-Z

KHQX1

2.5

3.0

10, 15, 16

Clock to output in High-Z

KHQZ

4.0

5.0

10, 15, 16

OE# to output valid

GLQV

3.5

4.0

5.0

OE# to output in Low-Z

GLQX

10, 15, 16

OE# to output in High-Z

GHQZ

3.5

4.0

5.0

10, 15, 16

Setup Times

Address

AVKH

2.0

Clock enable (CKE#)

EVKH

2.0

Control signals

CVKH

2.0

Data-in

DVKH

2.0

Hold Times

Address

KHAX

0.5

Clock enable (CKE#)

KHEX

0.5

Control signals

KHCX

0.5

Data-in

KHDX

0.5

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Notes

1. All voltages referenced to V

(GND).

2. For 3.3V V

Overshoot: V

£ +4.6V for t £

KHKH/2 for

£ 20mA

Undershoot:V

³ -0.7V for t £

KHKH/2 for

£ 20mA

Power-up:

£ +3.6V and V

£ 3.135V for

£ 200ms

3. For 2.5V V

Overshoot: V

£ +3.6V for t £

KHKH/2 for

£ 20mA

Undershoot:V

³ -0.5V for t £

KHKH/2 for

£ 20mA

Power-up:

£ +2.65V and V

£ 2.375V for

£ 200ms

4. The MODE and ZZ pins/balls have internal pull-

up/pull-down and input leakage = ±10µA.

5. V

Q should never exceed V

. V

and V

can be externally wired together to the same
power supply.

6. I

is specified with no output current and

increases with faster cycle times. I

Q increases

with faster cycle times and greater output loading.

7. "Device deselected" means device is in power-

down mode as defined in the truth table. "Device
selected" means device is active (not in power-
down mode).

8. Typical values are measured at 3.3V, 25

C, and

12ns cycle time.

9. Typical values are measured at 2.5V, 25

C, and

12ns cycle time.

10. This parameter is sampled.
11. OE# can be considered a "Don't Care" during

WRITEs; however, controlling OE# can help fine-
tune a system for turnaround timing.

12. Test conditions as specified with the output load-

ing shown in Figures 11 and 12 for 3.3V I/O and
Figures 13 and 14 for 2.5V I/O unless otherwise
noted.

13. A WRITE cycle is defined by R/W# LOW, having

been registered into the device at ADV/LD# LOW.
A READ cycle is defined by R/W# HIGH with ADV/
LD# LOW. Both cases must meet setup and hold
times.

14. Measured as HIGH above V

and LOW below V

15. Refer to Technical Note TN-55-01, "Designing

with ZBT SRAMs," for a more thorough discussion
of these parameters.

16. This parameter is measure with the output load-

ing shown in Figure 12 for 3.3V I/O and Figure 14
for 2.5V I/O.

17. This is a synchronous device. All addresses must

meet the specified setup and hold times with sta-
ble logic levels for all rising edges of CLK when the
chip is enabled. To remain enabled, chip enable
must be valid at each rising edge of CLK when
ADV/LD# is LOW.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 8:

READ/WRITE Timing

NOTE:

1. For these waveforms, ZZ is tied LOW.
2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

WRITE

D(A1)

CLK

tKHKH

tKLKH

tKHKL

CE#

tKHCX

tCVKH

R/W#

CKE#

tKHEX

tEVKH

BWx#

ADV/LD#

tKHAX

tAVKH

ADDRESS

tKHDX

tDVKH

COMMAND

tKHQX1

D(A1)

D(A2)

Q(A4)

Q(A3)

D(A2+1)

tKHQX

tKHQZ

tKHQV

WRITE

D(A2)

BURST
WRITE

D(A2+1)

READ

Q(A3)

READ

Q(A4)

BURST

READ

Q(A4+1)

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

OE#

tGLQV

tGLQX

tGHQZ

DON'T CARE

UNDEFINED

D(A5)

tKHQX

Q(A4+1)

D(A7)

Q(A6)

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 9:

NOP, STALL, AND DESELECT Cycles

NOTE:

1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a "pause." A WRITE is not

performed during this cycle.

2. For these waveforms, ZZ and OE# are tied LOW.
3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.
4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

READ

Q(A3)

D(A4)

CLK

CE#

R/W#

CKE#

BWx#

ADV/LD#

ADDRESS

COMMAND

WRITE

D(A4)

STALL

WRITE

D(A1)

READ

Q(A2)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON'T CARE

UNDEFINED

tKHQZ

Q(A2)

D(A1)

Q(A3)

tKHQX

Q(A5)

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

SNOOZE MODE

SNOOZE MODE is a low-current, power-down

mode in which the device is deselected and current is
reduced to I

. The duration of SNOOZE MODE is

dictated by the length of time the ZZ is in a HIGH state.
After the device enters SNOOZE MODE, all inputs
except ZZ become disabled and all outputs go
to High-Z.

The ZZ is an asynchronous, active HIGH input that

causes the device to enter SNOOZE MODE. When the
ZZ becomes a logic HIGH, I

is guaranteed after the

time

ZZI is met. Any READ or WRITE operation pend-

ing when the device enters SNOOZE MODE is not
guaranteed to complete successfully. Therefore,
SNOOZE MODE must not be initiated until valid pend-
ing operations are completed. Similarly, when exiting
SNOOZE MODE during

RZZ, only a DESELECT or

READ cycle should be given.

NOTE:

1. This parameter is sampled.

Figure 10:

SNOOZE MODE Waveform

Table 18: SNOOZE MODE Electrical Characteristics

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Current during SNOOZE MODE

³ V

SB2Z

ZZ active to input ignored

KHKH

ZZ inactive to input sampled

RZZ

KHKH

ZZ active to snooze current

ZZI

KHKH

ZZ inactive to exit snooze current

RZZI

SUPPLY

CLK

RZZ

ALL INPUTS

(except ZZ)

DON'T CARE

ISB2Z

ZZI

RZZI

Outputs (Q)

High-Z

DESELECT or READ Only

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

3.3V V

, 3.3V I/O AC Test Conditions

Input pulse levels ....................... V

= (V

/2.2) + 1.5V

..........................V

= (V

/2.2) - 1.5V

Input rise and fall times ..............................................1ns
Input timing reference levels..............................V

/2.2

Output reference levels ....................................V

Q/2.2

Output load................................... See Figures 11 and 12

3.3V V

, 2.5V I/O AC Test Conditions

Input pulse levels ....................V

= (V

/2.64) + 1.25V

...................... V

= (V

/2.64) - 1.25V

Input rise and fall times ..............................................1ns
Input timing reference levels............................V

/2.64

Output reference levels .......................................V

Q/2

Output load................................... See Figures 13 and 14

3.3V I/O Output Load Equivalents

Figure 11:

Figure 12:

2.5V V

, 2.5V I/O AC Test Conditions

Input pulse levels..........................V

= (V

/2) + 1.25V

........................... V

= (V

/2) - 1.25V

Input rise and fall times ............................................. 1ns
Input timing reference levels.................................V

Output reference levels .......................................V

Q/2

Output load................................... See Figures 13 and 14

2.5V I/O Output Load Equivalents

Figure 13:

Figure 14:

NOTE:

For Figures 11 and 13, 30pF = distributive test jig capacitance.

= V

Q/2.2

30pF

Z = 50

351

317

5pF

+3.3V

= V

Q/2

30pF

Z = 50

225

5pF

+2.5V

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

IEEE 1149.1 Serial Boundary Scan
(JTAG)

The SRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance
with IEEE Standard 1149.1-1990 but does not have the
set of functions required for full 1149.1 compliance.
These functions from the IEEE specification are
excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 3.3V or 2.5V I/O logic levels.

The SRAM contains a TAP controller, instruction

Disabling the JTAG Feature

These balls can be left floating (unconnected), if the

JTAG function is not to be implemented. Upon pow-
erup, the device will come up in a reset state which will
not interfere with the operation of the device.

Figure 15:

TAP Controller State Diagram

NOTE:

The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.

Test Access Port (Tap)
Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.

Test Data-In (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 15. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register. (See Figure 16.)

Test Data-Out (TDO)

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending
upon the current state of the TAP state machine. (See
Figure 15.) The output changes on the falling edge of
TCK. TDO is connected to the least significant bit
(LSB) of any register. (See Figure 16.)

Figure 16:

TAP Controller Block Diagram

NOTE:

X = 74 for all configurations.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register*

Selection

Circuitry

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI

TDO

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (V

)

for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected
at a time through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it
is placed between the TDI and TDO balls as shown in
Figure 16. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two LSBs are loaded with a binary "01" pattern to
allow for fault isolation of the board-level serial test
data path.

Bypass Register

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (V

) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. The SRAM
has a 75-bit-long register.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift-DR state. The EXTEST, SAMPLE/PRELOAD and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to

one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.

TAP Instruction Set
Overview

Eight different instructions are possible with the

three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.

Instructions are loaded into the TAP controller dur-

ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
ter through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller, and therefore this device is not
compliant to 1149.1.

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAM-
PLE/PRELOAD instruction has been loaded. There is
one difference between the two instructions. Unlike

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

the SAMPLE/PRELOAD instruction, EXTEST places
the SRAM outputs in a High-Z state.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bidirectional balls is captured in the boundary
scan register.

The user must be aware that the TAP controller

clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a

transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.

o guarantee that the boundary scan register will

capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-

troller's capture setup plus hold time (

CS plus

CH).

The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CLK captured in the
boundary scan register.

Once the data is captured, it is possible to shift out

the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruc-
tion will have the same effect as the Pause-DR com-
mand.

BYPASS

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruc-
tion is that it shortens the boundary scan path when
multiple devices are connected together on a board.

Reserved

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 17:

TAP Timing

NOTE:

CS and

CH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the loads in Figures 18 and 19.

TLTH

Test Clock

(TCK)

Test Mode Select

(TMS)

tTHTL

Test Data-Out

(TDO)

tTHTH

Test Data-In

(TDI)

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

DON'T CARE

UNDEFINED

Table 19: TAP AC Electrical Characteristics

Notes 1, 2; 0ºC

£ T

£ +70ºC; V

= 3.3V ±0.165V or 2.5V ±0.125V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

Clock cycle time

THTH

100

Clock frequency

MHz

Clock HIGH time

THTL

Clock LOW time

TLTH

Output Times

TCK LOW to TDO unknown

TLOX

TCK LOW to TDO valid

TLOV

TDI valid to TCK HIGH

DVTH

TCK HIGH to TDI invalid

THDX

Setup Times

TMS setup

MVTH

Capture setup

Hold Times

TMS hold

THMX

Capture hold

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

3.3V TAP AC Test Conditions

Input Pulse Levels .......................................... Vss to 3.0V
Input rise and fall times ..............................................1ns
Input timing reference levels.................................... 1.5V
Output reference levels ............................................. 1.5V
Test load termination supply voltage ...................... 1.5V

Figure 18:

3.3V TAP AC Output Load Equivalent

2.5V TAP AC Test Conditions

Input Pulse Levels........................................... Vss to 2.5V
Input rise and fall times ............................................. 1ns
Input timing reference levels.................................. 1.25V
Output reference levels ........................................... 1.25V
Test load termination supply voltage .................... 1.25V

Figure 19:

2.5V TAP AC Output Load Equivalent

NOTE:

1. All voltages referenced to V

(GND).

2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and

Operation Conditions tables.

TDO

1.5V

20pF

Z = 50

TDO

1.25V

20pF

Z = 50

Table 20: 3.3V V

, TAP DC Electrical Characteristics and Operating Conditions

0ºC

£ T

£ +70ºC; V

= 3.3V ±0.165V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

2.0

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.8

1, 2

Input Leakage Current

£ V

-10

µA

Output Leakage Current

Output(s) disabled,

£ V

(TDO)

-10

µA

Output Low Voltage

OLC

= 100µA

OL1

0.7

1, 2

OLT

= 2mA

OL2

0.8

1, 2

Output High Voltage

OHC

= -100µA

OH1

2.9

1, 2

OHT

= -2mA

OH2

2.0

1, 2

Table 21: 2.5V V

, TAP DC Electrical Characteristics and Operating Conditions

0ºC

£ T

£ +70ºC; V

= 2.5V ±0.125V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

1.7

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.7

1, 2

Input Leakage Current

£ V

-10

µA

Output Leakage Current

Output(s) disabled,

£ V

(TDO)

-10

µA

Output Low Voltage

OLC

= 100µA

OL1

0.2

1, 2

OLT

= 2mA

OL2

0.7

1, 2

Output High Voltage

OHC

= -100µA

OH1

2.1

1, 2

OHT

= -2mA

OH2

1.7

1, 2

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 22: Identification Register Definitions

INSTRUCTION FIELD

BIT CONFIGURATION

DESCRIPTION

Revision Number
(31:28)

0000

Reserved for version number.

Device Depth
(27:23)

00111
00110

Defines depth of 1Mb.
Defines depth of 512K.

Device Width
(22:18)

00011
00100

Defines width of x18 bits.
Defines width of x32 or x 36 bits.

Micron Device ID
(17:12)

xxxxxx

Reserved for future use.

Micron JEDEC ID Code
(11:1)

00000101100

Allows unique identification of SRAM vendor.

ID Register Presence
Indicator (0)

Indicates the presence of an ID register.

Table 23: Scan Register Sizes

BIT SIZE

Instruction

Bypass

Boundary Scan: x18, x32, x36

Table 24: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and
TDO. This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 25: 165-Ball FBGA Boundary Scan Order (x18)

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

MODE (LBO#)

CLK

11B

11P

CE2#

BWa#

BWb#

10R

10P

CE2

11R

CE#

11H

11N

11M

11L

11K

11J

DQa

10M

DQa

10L

DQa

10K

DQb

DQa

10J

DQb

DQa

11G

DQb

DQa

11F

DQb

DQa

11E

DQb

DQa

11D

DQb

DQPa

11C

DQb

10F

DQb

10E

DQPb

10D

10G

11A

10B

10A

ADV/LD#

OE# (G#)

SA1

CKE#

SA0

R/W#

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 26: 165-Ball FBGA Boundary Scan Order (x32)

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

MODE (LB0#)

CLK

11B

11P

CE2#

BWa#

BWb#

BWc#

10R

BWd#

10P

CE2

11R

CE#

11H

11N

DQa

11M

DQa

11L

DQa

11K

DQc

DQa

11J

DQc

DQa

10M

DQc

DQa

10L

DQc

DQa

10K

DQc

DQa

10J

DQc

DQb

11G

DQc

DQb

11F

DQc

DQb

11E

DQd

DQb

11D

DQd

DQb

10G

DQd

DQb

10F

DQd

DQb

10E

DQd

DQb

10D

DQd

11C

DQd

11A

DQd

10B

10A

ADV/LD#

OE# (G#)

SA1

CKE#

SA0

R/W#

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Table 27: 165-Ball FBGA Boundary Scan Order (x36)

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

MODE (LB0#)

CLK

11B

11P

CE2#

BWa#

BWb#

BWc#

10R

BWd#

10P

CE2

11R

CE#

11H

DQPa

11N

DQa

11M

DQa

11L

DQPc

DQa

11K

DQc

DQa

11J

DQc

DQa

10M

DQc

DQa

10L

DQc

DQa

10K

DQc

DQa

10J

DQc

DQb

11G

DQc

DQb

11F

DQc

DQb

11E

DQd

DQb

11D

DQd

DQb

10G

DQd

DQb

10F

DQd

DQb

10E

DQd

DQb

10D

DQd

DQPb

11C

DQd

11A

DQd

10B

DQPd

10A

ADV/LD#

OE# (G#)

SA1

CKE#

SA0

R/W#

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc.,

and Motorola, Inc.

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Figure 21:

165-Ball FBGA

NOTE:

1. All dimensions in inches (millimeters)

or typical where noted.

Data Sheet Designation

No Marking: This data sheet contains minimum and maximum limits specified over the complete power

supply and temperature range for production devices. Although considered final, these specifications are sub-
ject to change, as further product development and data characterization sometimes occur.

10.00

14.00

15.00 ±0.10

1.00

TYP

1.00

TYP

5.00 ±0.05

13.00 ±0.10

PIN A1 ID

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 ±0.05

7.00 ±0.05

7.50 ±0.05

1.20 MAX

SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36% Pb, 2% Ag
SOLDER BALL PAD: Ø .33mm

SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40

SEATING PLANE

0.85 ±0.075

0.12 C

165X Ø 0.45

BALL A11

MAX

MIN

--------------

18Mb: 1 MEG x 18, 512K x 32/36

FLOW-THROUGH ZBT SRAM

18Mb: 1 Meg x 18, 512K x 32/36 Flow-through ZBT SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT55L1MY18F_16_D.fm Rev. D, Pub. 2/03

Document Revision History

· Rev D; Pub. 2/03..........................................................................................................................................................2/03

Changed designation from Preliminary to Production

· Rev C; Pub. 12/02 ......................................................................................................................................................12/02

Added T

specifications to the AC Electrical Characteristics table

Corrected Boundary Scan
Updated TQFP and FBGA Thermal Resistance values
Corrected grammatical errors

· Rev B; PRELIMINARY ...............................................................................................................................................11/02

Changed designation from ADVANCE to PRELIMINARY
Corrected grammatical errors

· New ADVANCE data sheet for 0.16µm process; Rev A; Pub. 6/02 ...........................................................................6/02

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