PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

9Mb
DDR SRAM

MT57V256H36E

FEATURES

· Fast cycle times: 5ns and 6ns
· 256K x 36 configuration
· Pipelined, double data rate operation
· Single +2.5V ±0.1V power supply (V

)

· Separate isolated output buffer supply (V

· JEDEC-standard HSTL I/O
· User-selectable trip point with V

REF

· HSTL programmable impedance outputs

synchronized to optional dual-data clocks

· Echo clock outputs
· JTAG boundary scan
· Fully-static design for reduced-power standby
· Clock-stop capability
· Common data inputs and data outputs
· Low-control ball count
· Internally self-timed, registered LATE WRITE cycles
· Linear burst order with four-tick burst counter
· 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

package

· Full data coherency, providing most current data

General Description

The Micron

DDR synchronous SRAM employs

high-speed, low-power CMOS designs using an
advanced 6T CMOS process.

The DDR SRAM integrates a 9Mb SRAM core with

advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by an input clock pair (K and K#)
and are latched on the rising edge of K and K#. The
synchronous inputs include all addresses, all data
inputs, active LOW load (LD#) and read/write (R/W#).
Write data is registered on the rising edges of both K
and K#. Read data is driven on the rising edge of C and
C# if provided, or on the rising edge of K and K#, if C
and C# are not provided.

Asynchronous inputs include impedance match

(ZQ). Synchronous data outputs (Q) are closely
matched to the two echo clocks (CQ and CQ#), which
can be used as data receive clocks. Output data clocks
(C, C#) are also provided for maximum system clock-
ing and data synchronization flexibility.

OPTIONS

MARKING

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron's Web site--

http://www.micron.com/numberguide.

· Clock Cycle Timing

5ns (200 MHz)

-5

6ns (167 MHz)

-6

· Configurations

256K x 36

MT57V256H36E

· Package

165-ball, 13mm x 15mm FBGA

Table 1:

Valid Part Numbers

PART NUMBER

DESCRIPTION

MT57V256H36EF-xx

256K x 36, HSTL, DDR, Pipelined

Figure 1:

165-Ball FBGA

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Additional write registers are incorporated to

enhance pipelined WRITE cycles and reduce READ-to-
WRITE turnaround time. WRITE cycles are self-timed.

The device does not utilize internal phase-locked

loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.

Four balls are used to implement JTAG test capabili-

ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.

The device can be used in HSTL systems by supply-

ing an appropriate reference voltage (V

REF

The

device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.

The SRAM operates from a +2.5V power supply, and

all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP, and other applications that benefit from a very
wide, high-speed data bus.

Please refer to Micron's Web site (

www.micron.com/

sramds

) for the latest data sheet.

DDR Operation

The DDR SRAM enables high performance opera-

tion through high-clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
NO OPERATION (NOP) cycle when transitioning from
a READ to a WRITE cycle. At higher frequencies, a sec-
ond NOP cycle may be required to prevent bus conten-
tion. NOP cycles

re not required when switching from

a WRITE to a READ.

If a READ occurs after a WRITE cycle, address and

data for the WRITE are stored in registers. The write
information must be stored because the SRAM cannot
perform the last WORD WRITE to the array without
conflicting with the READ. The data stays in this regis-
ter until the next WRITE cycle occurs. On the first
WRITE cycle after the READ(s), the stored data from
the earlier WRITE will be written into the SRAM array.
This is called a POSTED WRITE.

Figure 2:

Functional Block Diagram: 256K x 36

NOTE:

1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge.
2. The compare width is a 16-bits. The compare is performed only if a WRITE is pending and a READ cycle is requested.

If the address matches, data is routed directly to the device outputs, bypassing the memory array.

3. The functional block diagram illustrates simplified device operation. See truth tables, ball descriptions, and timing

diagrams for detailed information.

4. CQ and CQ# do not tri-state except during some JTAG test modes.

SA0, SA1, SA

LD#

ADDRESS
REGISTER

WRITE

ADDRESS
REGISTER

OUTPUT

BUFFER

BURST

LOGIC

SA0'

SA1'

D1
D0

Q1
Q0

SA0

SA1

(NOTE 1)

INPUT

(NOTE 2)

R/W#

COMPARE

CLK

WRITE#

INPUT

SA0'''

WRITE#

READ

SA0''

SA0'''

SA1'-SA17'

SA0#'

SA0'

SA0#'

SA0'

OUTPUT

CONTROL

LOGIC

OUTPUT

WRITE

SENSE

AMPS

128K x 72
MEMORY

ARRAY

WRITE

DRIVER

CLK

2:1

MUX

CQ, CQ#

(Note 4)

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

A READ can be made immediately to an address

even if that address was written in the previous cycle.
During this READ cycle, the SRAM array is bypassed,
and data is read instead from the data register storing
the recently written data. This is transparent to the
user. This feature facilitates system data coherency.

The DDR SRAM differs in some ways from its prede-

cessor, the Claymore DDR SRAM. Single data rate
operation is not supported, hence, no SD/DD# ball is
provided. Only bursts of four are supported. In addi-
tion to the echo clocks, two single-ended input clocks
are available (C and C#). The SRAM synchronizes its
output data to these data clock rising edges if pro-
vided. If not present, C and C# must be tied HIGH and
output timing is derived from K and K#. No differential
clocks are used in this device. This clocking scheme
provides greater system tuning capability than Clay-
more SRAMs and reduces the number of input clocks
required by the bus master.

Programmable Impedance Output
Buffer

The DDR SRAM is equipped with programmable

impedance output buffers. This allows a user to match
the driver impedance to the system. To adjust the
impedance, an external precision resistor (RQ) is con-
nected between the ZQ ball and V

. The value of the

resistor must be five times the desired impedance. For
example, a 350

W resistor is required for an output

impedance of 70

W. To ensure that output impedance is

one-fifth the value of RQ (within 10 percent), the range

of RQ is 175

W to 350W. Alternately, the ZQ ball can be

connected directly to V

Q, which will place the

device in a minimum impedance mode.

Output impedance updates may be required

because variations may occur in supply voltage and
temperature over time. The device samples the value
of RQ. An update

f the impedance is transparent to

the system. Impedance updates do not affect device
operation, and all data sheet timing and current speci-
fications are met during an update.

The device will power up with an output impedance

set at 50

W. To guarantee optimum output driver

impedance after power-up, the SRAM needs 1,024
cycles to update the impedance. The user can operate
the part with fewer than 1,024 clock cycles, but optimal
output impedance is not guaranteed.

Clocking

The DDR SRAM supports flexible clocking

approaches. C and C# may be supplied to the SRAM to
synchronize data output across multiple devices,
enabling the bus master to receive all data simulta-
neously. If C and C# are not provided (tied HIGH) K
and K# are used as the output timing reference. The
echo clocks (CQ and CQ#) provide another alternative
for data synchronization. The echo clocks are con-
trolled exactly like the DQ signals except that CQ and
CQ# have an additional small delay for easier data cap-
ture by the bus master. Echo clocks must be separately
received for each SRAM in the system. Use of echo
clocks maximizes the available data window for each
SRAM in the system.

Figure 3:

Application Example

LD#

Vterm = 0.75V

C C#

R/W#

DQn
SAn

LD#

C C#

R/W#

DQn
SAn

BUS

MASTER

(CPU

ASIC)

SRAM

Addresses

Cycle Start#

R/W#

Return CLK

Source CLK

Return CLK#

Source CLK#

R = 50

R = 250

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Table 2:

Ball Assignment (Top View)
165-BAll FBGA

CQ#

SS/

NC/

R/W#

LD#

NC/

SS/

DQ19

DQ18

DQ17

DQ20

SA0

SA1

DQ15

DQ16

DQ22

DQ21

DQ14

DQ23

DQ12

DQ13

DQ25

DQ24

DQ11

DQ26

DQ27

DQ10

REF

DQ28

DQ9

DQ8

DQ29

DQ6

DQ7

DQ31

DQ30

DQ5

DQ32

DQ3

DQ4

DQ34

DQ33

DQ2

DQ35

DQ0

DQ1

TDO

TCK

TMS

TDI

NOTE:

1. Expansion address: 2A for 144Mb
2. Expansion address: 3A for 36Mb
3. Expansion address: 9A for 18Mb
4. Expansion address: 10A for 72Mb

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Table 3:

Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

SA0
SA1

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times
around the rising edge of K. See Ball Assignment figures for address expansion inputs. SA0 and SA1
are used as the lowest two address bits for BURST READ and BURST WRITE operations. These inputs
are ignored when device is deselected or once BURST operation is in progress.

LD#

Input

Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This
definition includes address and read/write direction. All transactions operate on a burst of four data
(two clock periods of bus activity).

R/W#

Input

Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when
R/W# is HIGH, WRITE when R/W# is LOW) for the loaded address. R/W# must meet the setup and
hold times around the rising edge of K.

Input

Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and
registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of
phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges.

Input

Output Clock: This clock pair provides a user-controlled means of tuning device output data. The
rising edge of C# is used as the output reference for second and fourth output data. The rising edge
of C is used as the output timing reference for first and third output data. Ideally, C# is 180 degrees
out of phase with C. C and C# may be tied HIGH to force the use of K and K# as the output reference
clocks instead of having to provide C and C# clocks. If tied HIGH, C and C# must remain HIGH and not
be toggled during device operation.

TMS

TDI

Input

IEEE 1149.1 Test Inputs: JEDEC-standard 2.5V I/O levels. These balls may be left as No Connects if the
JTAG function is not used in the circuit.

TCK

Input

IEEE 1149.1 Clock Input: JEDEC-standard 2.5V I/O levels. This ball must be tied to V

if the JTAG

function is not used in the circuit.

REF

Input

HSTL Input Reference Voltage: Nominally V

Q/2. Provides a reference voltage for the input buffers.

Input

Output Impedance Matching Input: This input is used to tune the device outputs to the system data
bus impedance. DQ and CQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this ball
to ground. Alternately, this ball can be connected directly to V

Q, which enables the minimum

impedance mode. This ball cannot be connected directly to GND or left unconnected.

DQ_

Input/

Output

Synchronous Data I/Os: Input data must meet setup and hold times around the rising edges of K and
K#. Output data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are
tied HIGH. See Ball Assignment figures for ball site location of individual signals.

TDO

Output

IEEE 1149.1 Test Output: JEDEC-standard 2.5V I/O level.

Supply

Power Supply: 2.5V nominal. See DC Electrical Characteristics and Operating Conditions for range.

Supply

Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC Electrical Characteristics and
Operating Conditions for range.

Supply

Power Supply: GND.

No Connect: These signals may be connected to ground to improve package heat dissipation.
For upgrade to 18, 36, 72, and 144Mb DDR devices, balls 2A, 3A, 9A, and 10A are reserved for
higher-order address bits, respectively.

NC/

These balls are reserved for higher-order address bits, respectively.

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Figure 4:

Bus Cycle State Diagram

NOTE:

1. SA0 and SA1 are internally advanced in accordance with the burst order table. Bus cycle is terminated after burst

count = 4.

2. State transitions: L = (LD# = LOW); L# = (LD# = HIGH); R = (R/W# = HIGH); W = (R/W# = LOW).
3. State machine control timing sequence is controlled by K.

Table 4:

Linear Burst Address

FIRST ADDRESS
(EXTERNAL)

SECOND ADDRESS
(INTERNAL)

THIRD ADDRESS
(INTERNAL)

FOURTH ADDRESS
(INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

LOAD NEW ADDRESS

Count=0

READ DOUBLE

Count=Count+2

ADVANCE ADDRESS

BY TWO1

WRITE DOUBLE

Count=Count+2

ADVANCE ADDRESS

BY TWO1

POWER-UP

Supply

voltage

provided

NOP

L, Count=4

Count=2

always

Count=2

always

L#, Count=4

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

NOTE:

1. X means "Don't Care." H means logic HIGH. L means logic LOW.

means rising edge; ¯ means falling edge.

2. Data inputs are registered at K and K# rising edges. Data outputs are delivered at C and C# rising edges, except if C

and C# are HIGH, then data outputs are delivered at K and K# rising edges.

3. All control inputs in the truth table must meet setup and hold times around the rising edge (LOW to HIGH) of K. All

control inputs are registered during the rising edge of K.

4. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
5. Refer to state diagram and timing diagrams for clarification.
6. A1 refers to the address input during a WRITE or READ cycle. A2, A3, and A4 refer to the next internal burst address

in accordance with the burst sequence.

7. It is recommended that K = /K# = C =/ C# when clock is stopped. This is not essential, but permits most rapid restart

by overcoming transmission line charging symmetrically.

Table 5:

Truth Table

Notes 1-7

OPERATION

LD#

R/W#

WRITE Cycle:
Load address, input write data on two
consecutive K and K# rising edges

®H

(A1)

K(t + 1 )

(A2)

K#(t + 1)

(A3)

(t + 2)

(A4)

#(t + 2)

READ Cycle:
Load address, read data on two
consecutive C and C# rising edges

®H

OUT

(A1)

C(t + 1)

OUT

(A2)

C#(t + 1)

OUT

(A3)

C(t + 2)

OUT

(A4)

C#(t + 2)

NOP: No operation

®H

High-Z

STANDBY: Clock stopped

Stopped

State

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Stresses greater than those listed under Absolute

Maximum Ratings may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.

Maximum junction temperature depends upon

package type, cycle time, loading, ambient tempera-
ture, and airflow. See Micron Technical Note TN-05-14
for more information.

ABSOLUTE MAXIMUM RATINGS

Voltage on V

Supply Relative to V

.....-0.5V to +3.6V

Voltage on V

Q Supply

Relative to V

........................................ -0.5V to +V

..................................................... -0.5V to V

+ 0.5V

Storage Temperature ............................. -55ºC to +125ºC
Junction Temperature .......................................... +125ºC
Short Circuit Output Current .............................. ±70mA

Table 6:

DC Electrical Characteristics And Operating Conditions

Notes appear following parameter tables; 0ºC

£ T

£ +70ºC; +2.4V £ V

£ +2.6V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.1

Q + 0.3

3, 4

Input Low (Logic 0) Voltage

(

DC)

-0.3

REF

- 0.1

3, 4

Clock Input Signal Voltage

-0.3

Q + 0.3

3, 4

Input Leakage Current

£ V

-5

µA

Output Leakage Current

Output(s) disabled,

£ V

Q (Q)

-5

µA

Output High Voltage

£ 0.1mA

(

LOW

)

Q - 0.2

3, 5, 7

Note 1

Q/2 - 0.08

Q/2 + 0.08

3, 5, 7

Output Low Voltage

£ 0.1mA

(

LOW

)

0.2

3, 5, 7

Note 2

Q/2 - 0.08

Q/2 + 0.08

3, 5, 7

Supply Voltage

2.4

2.6

Isolated Output Buffer Supply

1.4

1.6

3, 6

Reference Voltage

REF

0.68

0.9

Table 7:

AC Electrical Characteristics And Operating Conditions

Notes appear following parameter tables; 0ºC

£ T

£ +70ºC; +2.4V £ V

£ +2.6V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

(

)

REF

+ 0.2

3, 4, 8

Input Low (Logic 0) Voltage

(

)

REF

- 0.2

3, 4, 8

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Table 8:

Operating Conditions And Maximum Limits

Notes appear following parameter tables

; 0ºC

£ T

£ +70ºC; V

= MAX unless otherwise noted

MAX

DESCRIPTION

CONDITIONS

SYMBOL

TYP

-5

-6

UNITS

NOTES

Operating Supply
Current: DDR

All inputs

£ VIL or

VIH;

Cycle time

KHKH (MIN

);

Outputs open

550

650

550

9, 10, 11

Standby Supply Current:
NOP

KHKH =

KHKH (MIN);

Device in NOP state; All

addresses/data static

SB1

150

225

175

10, 12

Output Supply Current:
DDR (Information only)

= 15pF

TBD

Table 9:

Capacitance

Note 14; notes appear following parameter tables

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

Address/Control Input Capacitance

= 25°C; f = 1 MHz

4.5

5.5

Input, Output Capacitance (DQ)

Clock Capacitance

5.5

6.5

Table 10: Thermal Resistance

Note 14; notes appear following parameter tables

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

NOTES

Junction to Ambient (Airflow of 1m/s)

Soldered on a 4.25 x 1.125 inch,

4-layer printed circuit board

30.9

°C/W

Junction to Case (Top)

1.0

°C/W

Junction to Balls (Bottom)

9.6

°C/W

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Table 11: AC Electrical Characteristics And Recommended Operating

Conditions

Notes 14, 17-19; notes appear following parameter tables; 0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V

DESCRIPTION

SYMBOL

-5

-6

UNITS NOTES

MIN

MAX

MIN

MAX

Clock

Clock cycle time (K, K#, C, C#)

KHKH

5.0

6.0

Clock HIGH time (K, K#, C, C#)

KHKL

2.0

2.4

Clock LOW time (K, K#, C, C#)

KLKH

2.0

2.4

Clock to clock# (K

®K#, C®C#) at

KHKH minimum

KHK#H

2.4

2.8

Clock# to clock (K#

®K, C#®C)at

KHKH minimum

K#HKH

2.4

2.8

Clock to data clock (K

®C, K#®C#)

KHCH

0.0

1.5

0.0

2.0

Output Times

C, C# HIGH to output valid

CHQV

2.4

3.0

C, C# HIGH to output hold

CHQX

0.8

C HIGH to output HIGH-Z

CHQZ

2.4

3.0

20, 21

C HIGH to output LOW-Z

CHQX1

0.8

20, 21

C, C# HIGH to CQ, CQ# HIGH

CHCQH

0.8

2.6

0.8

3.2

CQ, CQ# HIGH to output valid

CHCQV

0.35

0.40

CQ, CQ# HIGH to output hold

CQHQX

-0.35

-0.40

CQ HIGH to output HIGH-Z

CHQQZ

0.35

0.40

20, 21

CQ HIGH to output LOW-Z

CQHQX1

-0.35

-0.40

20, 21

Setup Times

Address valid to K rising edge

AVKH

0.6

0.7

Control inputs valid to K rising edge

IVKH

0.6

0.7

Data-in valid to K, K# rising edge

DVKH

0.6

0.7

Hold Times

K rising edge to address hold

KHAX

0.6

0.7

K rising edge to control inputs hold

KHIX

0.6

0.7

K, K# rising edge to data-in hold

KHDX

0.6

0.7

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Notes

1. Outputs are impedance-controlled. |I

| =

Q/2)/(RQ/5) for values of 175

W £ RQ £ 350W.

2. Outputs are impedance-controlled. I

= (V

2)/(RQ/5) for values of 175

W £ RQ £ 350W.

3. All voltages referenced to V

(GND).

4. Overshoot: V

(

)

£ V

+ 0.7V for t

KHKH/2

Undershoot: V

(

)

³ -0.5V for t £

KHKH/2

Power-up: V

£ V

Q + 0.3V and V

£ 2.4V

and V

£ 1.4V for t £ 200ms

During normal operation, V

Q must not exceed

. Control input signals may not have pulse

widths less than

KHKL (MIN) or operate at cycle

rates less than

KHKH (MIN).

5. AC load current is higher than the shown DC val-

ues. AC I/O curves are available upon request.

6. For higher V

Q voltages, contact factory for

product information.

7. HSTL outputs meet JEDEC HSTL Class I and Class

II standards.

8. To maintain a valid level, the transitioning edge of

the input must:
a. Sustain a constant slew rate from the current AC

level through the target AC level, V

(

) or

(

)

b. Reach at least the target AC level
c. After the AC target level is reached, continue to

maintain at least the target DC level, V

(

) or

(

)

9. I

is specified with no output current and

increases with faster cycle times. I

Q increases

with faster cycle times and greater output loading.
Typical value is measured at 6ns cycle time.

10. Typical values are measured at V

=2.5V, V

Q =

1.5V, and temperature = 25°C.

11. Operating supply currents and burst mode cur-

rents are calculated with 50 percent READ cycles
and 50 percent WRITE cycles.

12. NOP currents are valid when entering NOP after

all pending READ and WRITE cycles are com-
pleted.

13. Average I/O current and power is provided for

informational purposes only and is not tested.
Calculation assumes that all outputs are loaded
with C

(in farads), f = input clock frequency, half

of outputs toggle at each transition (for example,
n = 18 for x36), C

= 6pF, V

Q = 1.5V and uses the

equations: Average I/O Power as dissipated by the
SRAM is:
P = 0.5 × n x f x V

x (C

+ 2C

). Average I

Q =

n x f x V

Q x (C

+ C

14. This parameter is sampled.
15. Average thermal resistance between the die and

the case top surface per MIL SPEC 883 Method
1012.1.

16. Junction temperature is a function of total device

power dissipation and device mounting environ-
ment. Measured per SEMI G38-87.

17. Control input signals may not be operated with

pulse widths less than

KHKL (MIN).

18. Test conditions as specified with the output load-

ing as shown in Figure 5, unless otherwise noted.

19. If C, C# are tied HIGH, then K, K# become the ref-

erences for C, C# timing parameters.

20. Transition is measured ±100mV from steady state

voltage.

21.

CHQXI is greater than

CHQZ at any given voltage

and temperature.

22. This is a synchronous device. All addresses, data,

and control lines must meet the specified setup
and hold times for all latching clock edges.

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

AC Test Conditions

Input pulse levels . . . . . . . . . . . . . . . . . . 0.25V to 1.25V
Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns
Input timing reference levels . . . . . . . . . . . . . . . . 0.75V
Output reference levels

. . . . . . . . . . . . . . . . . . . . . V

Q/2

ZQ for 50

W impedance . . . . . . . . . . . . . . . . . . . . . . . 250W

Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5

Figure 5:

Output Load Equivalent

Figure 6:

READ/WRITE Timing

NOTE:

1. Q01 refers to output from address A0 + 0. Q02 refers to output from the next internal burst address following A0,

etc.

2. Outputs are disabled (High-Z) one clock cycle after a NOP.
3. The second NOP cycle is not necessary for correct device operation; however, at high-clock frequencies it may be

required to prevent bus contention.

Q/2

250

Z = 50

SRAM

0.75V

REF

LD#

R/W#

READ
(burst of 4)

NOP

NOP
(Note 3)

WRITE
(burst of 4)

Q01

Q04

Q41

D21

D22

D23

D24

D31

D32

D33

D34

tKHKL

tKHK#H

tKHCH tCHQV

tCHQX

tKLKH

tKHKH

KHIX

tAVKH tKHAX

tDVKH

tKHDX

tKHCH

Q02

Q03

Q14

Q13

Q11

Q12

NOP

tDVKH

tKHDX

DON'T CARE

UNDEFINED

tCHQX1

tCHQV

tCHQX

tCQHQV

tCHQZ

tCQHQX

IVKH

CQ#

tKHKL

tKHK#H

tKLKH

tKHKH

tCHCQH

tCQHQX1

tCQHQZ

(Note 1)

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

IEEE 1149.1 Serial Boundary Scan (JTAG)

The DDR SRAM incorporates a serial boundary scan

test access port (TAP). This port operates in accor-
dance with IEEE Standard 1149.1-2001 but does not
have the set of functions required for full 1149.1 com-
pliance. These functions from the IEEE specification
are excluded because their inclusion places an added
delay in the critical speed path of the SRAM. Note that
the TAP controller functions in a manner that does not
conflict with the operation of other devices using
1149.1 fully compliant TAPs. The TAP operates using
JEDEC-standard 1.8V I/O logic levels.

The SRAM contains a TAP controller, instruction

Disabling The JTAG Feature

It is possible to operate the SRAM without using the

JTAG feature. To disable the TAP controller, TCK must
be tied LOW (V

) to prevent clocking of the device.

TDI and TMS are internally pulled up and may be
unconnected. Alternately, they may be connected to
V

through a pull-up resistor. TDO should be left

unconnected. Upon power-up, the device will come up
in a reset state which will not interfere with the opera-
tion of the device.

Test Access Port (TAP)
Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.

Test Mode Select (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It
is allowable to leave this ball unconnected if the TAP is
not used. The ball is pulled up internally, resulting in a
logic HIGH level.

Figure 7:

TAP Controller State Diagram

NOTE:

The 0/1 next to each state represents the value
of TMS at the rising edge of TCK.

Test Data-in (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of
any of the registers. The register between TDI and TDO
is chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 7. TDI is internally
pulled up and can be unconnected if the TAP is unused
in an application. TDI is connected to the most signifi-
cant bit (MSB) of any register, as illustrated in Figure 8.

Test Data-out (TDO)

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending
upon the current state of the TAP state machine illus-
trated in Figure 7. The output changes on the falling
edge of TCK. TDO is connected to the least significant
bit (LSB) of any register, as depicted in Figure 8.

TEST-LOGIC

RESET

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

CAPTURE-DR

SHIFT-DR

CAPTURE-IR

SHIFT-IR

EXIT1-DR

PAUSE-DR

EXIT1-IR

PAUSE-IR

EXIT2-DR

UPDATE-DR

EXIT2-IR

UPDATE-IR

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Figure 8:

TAP Controller Block Diagram

NOTE:

X = 68 for the x36 configuration.

Performing A TAP Reset

A RESET is performed by forcing TMS HIGH (V

)

for five rising edges of TCK. This RESET does not affect
the operation of the SRAM and may be performed
while the SRAM is operating.

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

TAP Registers

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the
SRAM test circuitry. Only one register at a time can be
selected through the instruction register. Data is seri-
ally loaded into the TDI ball on the rising edge of TCK.
Data is output on the TDO ball on the falling edge of
TCK.

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it
is placed between the TDI and TDO balls, as shown in
Figure 8. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state, as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two LSBs are loaded with a binary "01" pattern to
allow for fault isolation of the board-level serial test
data path.

Bypass Register

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that
can be placed between the TDI and TDO balls. This
allows data to be shifted through the SRAM with mini-
mal delay. The bypass register is set LOW (V

) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. Several no
connect (NC) balls are also included in the scan regis-
ter to reserve balls. The SRAM has a 69-bit-long regis-
ter.

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the
Shift- DR state. The EXTEST, SAMPLE/PRELOAD, and
SAMPLE Z instructions can be used to capture the
contents of the I/O ring.

The Boundary Scan Order table shows the order in

which the bits are connected. Each bit corresponds to
one of the balls on the SRAM package. The MSB of the
register is connected to TDI, and the LSB is connected
to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the
IDCODE command is loaded in the instruction regis-
ter. The IDCODE is hardwired into the SRAM and can
be shifted out when the TAP controller is in the Shift-
DR state. The ID register has a vendor code and other
information described in the Identification Register
Definitions table.

Tap Instruction Set
Overview

Eight different instructions are possible with the

three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not

Bypass Register

Instruction Register

Identification Register

Boundary Scan Register

Selection

Circuitry

Selection

Circuitry

TCK

TMS

TAP CONTROLLER

TDI

TDO

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.

Instructions are loaded into the TAP controller dur-

ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state,
instructions are shifted through the instruction regis-
ter and through the TDI and TDO balls. To execute the
instruction once it is shifted in, the TAP controller
needs to be moved into the Update-IR state.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in the
TAP controller, hence this device is not IEEE 1149.1
compliant.

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the

instruction register, the SRAM responds as if a SAM-

PLE/ PRELOAD instruction has been loaded. EXTEST
does not place the SRAM outputs in a High-Z state,
including CQ and CQ#.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state.

The IDCODE instruction is loaded into the instruc-

tion register upon power-up or whenever the TAP con-
troller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state, including CQ and CQ#.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bi-directional balls is captured in the boundary
scan register.

The user must be aware that the TAP controller

clock can only operate at a frequency up to 10 MHz,
while the SRAM clock operates more than an order of
magnitude faster. Because there is a large difference in
the clock frequencies, it is possible that during the
Capture-DR state, an input or output will undergo a
transition. The TAP may then try to capture a signal
while in transition (metastable state). This will not
harm the device, but there is no guarantee as to the
value that will be captured. Repeatable results may not
be possible.

To guarantee that the boundary scan register will

capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP con-
troller's capture setup plus hold time (

CS plus

CH).

The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the C and C# and K and K#
captured in the boundary scan register.

Once the data is captured, it is possible to shift out

the data by putting the TAP into the Shift-DR state.
This places the boundary scan register between the
TDI and TDO balls.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruc-
tion will have the same effect as the Pause-DR com-
mand.

BYPASS

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and
TDO. The advantage of the BYPASS instruction is that
it shortens the boundary scan path when multiple
devices are connected together on a board.

RESERVED

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Figure 9:

TAP Timing

NOTE:

CS and

CH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the load in Figure 10.

TLTH

Test Clock

(TCK)

Test Mode Select

(TMS)

tTHTL

Test Data-Out

(TDO)

tTHTH

Test Data-In

(TDI)

tTHMX

tMVTH

tTHDX

tDVTH

tTLOX

tTLOV

DON'T CARE

UNDEFINED

Table 12: TAP AC Characteristics

Notes 1, 2; 0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

Clock cycle time

THTH

100

Clock frequency

MHz

Clock HIGH time

THTL

Clock LOW time

TLTH

Output Times

TCK LOW to TDO unknown

TLOX

TCK LOW to TDO valid

TLOV

TDI valid to TCK HIGH

DVTH

TCK HIGH to TDI invalid

THDX

Setup Times

TMS setup

MVTH

Capture setup

Hold Times

TMS hold

THMX

Capture hold

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

TAP AC Test Conditions

Input pulse levels . . . . . . . . . . . . . . . . . . . . . . . . . .V

to 2.5V

Input rise and fall times . . . . . . . . . . . . . . . . . . . . . . 1ns
Input timing reference levels . . . . . . . . . . . . . . 1.25V
Output reference levels . . . . . . . . . . . . . . . . . . . . 1.25V
Test load termination supply voltage . . . . . . . . 1.25V

Figure 10:

TAP AC Output Load Equivalent

NOTE:

1. All voltages referenced to V

(GND)

2. Overshoot: V

(

)

£ V

+ 0.7V for t

KHKH/2

Undershoot: V

(

)

³ -0.5V for t £

KHKH/2

Power-up: V

£ +2.6 and V

£ +2.4V and V

£ 1.4V for t £ 200ms

During normal operation, V

Q must not exceed V

. Control input signals (LD#, R/W#, etc.) may not have pulse

widths less than

KHKL (MIN) or operate at frequencies exceeding

KF (MAX).

TDO

1.25V

20pF

Z = 50

Table 13: TAP DC Electrical Characteristics And Operation Conditions

0°C

£ T

£ +70°C; +2.4V £ V

£ +2.6V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

1.7

+ 0.3

1, 2

Input Low (Logic 0) Voltage

-0.3

0.7

1, 2

Input Leakage Current

£ V

-5.0

5.0

µA

Output Leakage Current

Output(s) disabled,

-5.0

5.0

µA

£ V

Output Low Voltage

OLC

= 100µA

OL1

0.2

Output Low Voltage

OLT

= 2mA

OL2

0.7

Output High Voltage

OHC

| = 100µA

OH1

2.1

Output High Voltage

OHT

| = 2mA

OH2

1.7

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Table 14: Identification Register Definitions

INSTRUCTION FIELD

256K x 36

DESCRIPTION

REVISION NUMBER
(31:29)

000

Reserved for version number.

DEVICE ID
(28:12)

00010100011000000

Defines 256K x 36 DDR 4-word burst.

DEVICE WIDTH
(22.18)

00100

Defines width of x36 bits.

MICRON JEDEC ID
(17.12)

xxxxxx

Reserved for future use.

MICRON JEDEC ID
CODE (11:1)

00000101100

Allows unique identification of SRAM vendor.

ID Register Presence
Indicator 0)

Indicates the presence of an ID register.

Table 15: Scan Register Size

BIT SIZE (x18)

Instruction

Bypass

Boundary Scan

Table 16: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

EXTEST

000

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction is not 1149.1-compliant. This operation does not affect SRAM operations.

IDCODE

001

Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operations.

SAMPLE Z

010

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all
SRAM output drivers to a High-Z state.

RESERVED

011

Do Not Use: This instruction is reserved for future use.

SAMPLE/
PRELOAD

100

Captures I/O ring contents. Places the boundary scan register between TDI and TDO. This
instruction does not implement 1149.1 preload function and is therefore not 1149.1-
compliant.

RESERVED

101

Do Not Use: This instruction is reserved for future use.

RESERVED

110

Do Not Use: This instruction is reserved for future use.

BYPASS

111

Places the bypass register between TDI and TDO. This operation does not affect SRAM
operations.

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Table 17: Boundary Scan (Exit) Order

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

7B; reads as X

5A; reads as X

R/W#

NC/

A19

3A; reads as 1

GND/

A21

2A; reads as 0

DQ0

10P

CQ#

DQ1

11P

DQ18

DQ2

11N

DQ19

DQ3

10M

DQ20

DQ4

11M

DQ21

DQ5

11L

DQ22

DQ6

10K

DQ23

DQ7

11K

DQ24

DQ8

11J

DQ25

11H

DQ26

DQ9

10J

DQ27

DQ10

11G

DQ28

DQ11

11F

DQ29

DQ12

10E

DQ30

DQ13

11E

DQ31

DQ14

11D

DQ32

DQ15

10C

DQ33

DQ16

11C

DQ34

DQ17

11B

DQ35

11A

GND/

SA20

10A; reads as 0

NC/

SA18

9A; reads as 1

SA1

SA0

LD#

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc.

256K x 36

2.5V V

, HSTL, PIPELINED DDR SRAM

0.16µm Process

ADVANCE

256K x 36 2.5V V

, HSTL, Pipelined DDR SRAM

MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03

Figure 11:

165-Ball FBGA

NOTE:

All dimensions are in millimeters.

DATA SHEET DESIGNATION

Advance: This data sheet contains initial descriptions of products still under development.

10.00

14.00

15.00 ±0.10

1.00

TYP

1.00

TYP

5.00 ±0.05

13.00 ±0.10

PIN A1 ID

BALL A1

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 ±0.05

7.00 ±0.05

7.50 ±0.05

1.20 MAX

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: Ø .33mm

SOLDER BALL DIAMETER REFERS
TO POST REFLOW CONDITION. THE
PRE-REFLOW DIAMETER IS Ø 0.40

SEATING PLANE

0.85 ±0.075

0.12 C

165X Ø 0.45

BALL A11

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT57V256H36EF-xx

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT57V256H36EF-xx