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Электронный компонент: MT58L512Y32D

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1
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
16Mb SYNCBURST
TM
SRAM
FEATURES
Fast clock and OE# access times
Single +3.3V 0.165Vor 2.5V 0.125V power supply
(V
DD
)
Separate +3.3V or 2.5V isolated output buffer
supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
WRITE
Three chip enables for simple depth expansion and
address pipelining
Clock-controlled and registered addresses, data I/Os
and control signals
Internally self-timed WRITE cycle
Burst control (interleaved or linear burst)
Automatic power-down
100-pin TQFP package
165-pin FBGA package
Low capacitive bus loading
x18, x32, and x36 versions available
OPTIONS
TQFP MARKING*
Timing (Access/Cycle/MHz)
3.5ns/6ns/166 MHz
-6
4.0ns/7.5ns/133 MHz
-7.5
5ns/10ns/100 MHz
-10
Configurations
3.3V V
DD
, 3.3V or 2.5V I/O
1 Meg x 18
MT58L1MY18D
512K x 32
MT58L512Y32D
512K x 36
MT58L512Y36D
2.5V V
DD
, 2.5V I/O
1 Meg x 18
MT58V1MV18D
512K x 32
MT58V512V32D
512K x 36
MT58V512V36D
Packages
100-pin TQFP (3-chip enable)
T
165-pin FBGA
F
Operating Temperature Range
Commercial (0C to +70C)
None
*See page 34 for FBGA package marking guide.
Part Number Example:
MT58L1MY18DT-7.5
MT58L1MY18D, MT58V1MV18D,
MT58L512Y32D, MT58V512V32D,
MT58L512Y36D, MT58V512V36D
3.3V V
DD
, 3.3V or 2.5V I/O; 2.5V V
DD
, 2.5V
I/O, Pipelined, Double-Cycle Deselect
GENERAL DESCRIPTION
The Micron
SyncBurst
TM
SRAM family employs high-
speed, low-power CMOS designs that are fabricated
using an advanced CMOS process.
Micron's 16Mb SyncBurst SRAMs integrate a 1 Meg x
18, 512K x 32, or 512K x 36 SRAM core with advanced
synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers
controlled by a positive-edge-triggered single-clock in-
put (CLK). The synchronous inputs include all addresses,
all data inputs, active LOW chip enable (CE#), two
additional chip enables for easy depth expansion (CE2,
CE2#), burst control inputs (ADSC#, ADSP#, ADV#),
byte write enables (BWx#) and global write (GW#). Note
that CE2# is not available on the T Version.
Asynchronous inputs include the output enable
(OE#), clock (CLK) and snooze enable (ZZ). There is also
100-Pin TQFP
1
NOTE: 1. JEDEC-standard MS-026 BHA (LQFP).
165-Pin FBGA
(Preliminary Package Data)
2
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FUNCTIONAL BLOCK DIAGRAM
1 MEG x 18
SA0, SA1, SAs
ADDRESS
REGISTER
ADV#
CLK
BINARY
COUNTER AND
LOGIC
CLR
Q1
Q0
ADSC#
20
20
18
20
BWb#
BWa#
CE#
BYTE "b"
WRITE REGISTER
BYTE "a"
WRITE REGISTER
ENABLE
REGISTER
SA0'
SA1'
OE#
SENSE
AMPS
1 Meg x 9 x 2
MEMORY
ARRAY
ADSP#
2
SA0-SA1
MODE
CE2
CE2#
GW#
BWE#
PIPELINED
ENABLE
DQs
DQPa
DQPb
2
OUTPUT
REGISTERS
INPUT
REGISTERS
E
BYTE "b"
WRITE DRIVER
BYTE "a"
WRITE DRIVER
OUTPUT
BUFFERS
9
9
9
9
18
18
18
18
18
NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for
detailed information.
FUNCTIONAL BLOCK DIAGRAM
512K x 32/36
ADDRESS
REGISTER
ADV#
CLK
BINARY
COUNTER
CLR
Q1
Q0
ADSP#
ADSC#
MODE
19
19
17
19
BWd#
BWc#
BWb#
BWa#
BWE#
GW#
CE#
CE2
CE2#
OE#
BYTE "d"
WRITE REGISTER
BYTE "c"
WRITE REGISTER
BYTE "b"
WRITE REGISTER
BYTE "a"
WRITE REGISTER
ENABLE
REGISTER
PIPELINED
ENABLE
DQs
DQPa
DQPb
DQPc
DQPd
4
OUTPUT
REGISTERS
SENSE
AMPS
512K x 8 x 4
(x32)
512K x 9 x 4
(x36)
MEMORY
ARRAY
OUTPUT
BUFFERS
E
BYTE "a"
WRITE DRIVER
BYTE "b"
WRITE DRIVER
BYTE "c"
WRITE DRIVER
BYTE "d"
WRITE DRIVER
INPUT
REGISTERS
SA0, SA1, SAs
SA0'
9
9
9
9
9
9
36
36
36
36
36
9
9
SA1'
SA0-SA1
3
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
GENERAL DESCRIPTION (continued)
NOTE: 1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
TQFP PIN ASSIGNMENT TABLE
PIN #
x18
x32/x36
1
NC
NC/
DQPc
1
2
NC
DQc
3
NC
DQc
4
V
DD
Q
5
V
SS
6
NC
DQc
7
NC
DQc
8
DQb
DQc
9
DQb
DQc
10
V
SS
11
V
DD
Q
12
DQb
DQc
13
DQb
DQc
14
NC
15
V
DD
16
NC
17
V
SS
18
DQb
DQd
19
DQb
DQd
20
V
DD
Q
21
V
SS
22
DQb
DQd
23
DQb
DQd
24
DQPb
DQd
25
NC
DQd
PIN #
x18
x32/x36
PIN #
x18
x32/x36
PIN #
x18
x32/x36
51
NC
NC/
DQPa
1
52
NC
DQa
53
NC
DQa
54
V
DD
Q
55
V
SS
56
NC
DQa
57
NC
DQa
58
DQa
59
DQa
60
V
SS
61
V
DD
Q
62
DQa
63
DQa
64
ZZ
65
V
DD
66
NC
67
V
SS
68
DQa
DQb
69
DQa
DQb
70
V
DD
Q
71
V
SS
72
DQa
DQb
73
DQa
DQb
74
DQPa
DQb
75
NC
DQb
26
V
SS
27
V
DD
Q
28
NC
DQd
29
NC
DQd
30
NC
NC/
DQPd
1
31
MODE (LBO#)
32
SA
33
SA
34
SA
35
SA
36
SA1
37
SA0
38
DNU
39
DNU
40
V
SS
41
V
DD
42
SA
43
SA
44
SA
45
SA
46
SA
47
SA
48
SA
49
SA
50
SA
a burst mode input (MODE) that selects between inter-
leaved and linear burst modes. The data-out (Q), en-
abled by OE#, is also asynchronous. WRITE cycles can be
from one to two bytes wide (x18) or from one to four
bytes wide (x32/x36), as controlled by the write control
inputs.
Burst operation can be initiated with either address
status processor (ADSP#) or address status controller
(ADSC#) inputs. Subsequent burst addresses can be in-
ternally generated as controlled by the burst advance
input (ADV#).
Address and write control are registered on-chip to
simplify WRITE cycles. This allows self-timed WRITE
cycles. Individual byte enables allow individual bytes to
be written. During WRITE cycles on the x18 device,
BWa# controls DQas and DQPa; BWb# controls DQbs
and DQPb. During WRITE cycles on the x32 and x36
devices, BWa# controls DQas and DQPa; BWb# controls
DQbs and DQPb; BWc# controls DQcs and DQPc; BWd#
controls DQds and DQPd. GW# LOW causes all bytes to
be written. Parity bits are only available on the x18 and
x36 versions.
This device incorporates an additional pipelined
enable register which delays turning off the output
buffer an additional cycle when a deselect is executed.
This feature allows depth expansion without penalizing
system performance.
Micron's 16Mb SyncBurst SRAMs operate from a
+3.3V or +2.5V power supply, and all inputs and outputs
are TTL-compatible. Users can implement either a 3.3V
or 2.5V I/O for the +3.3V V
DD
or a 2.5V I/O for the +2.5V
V
DD
. The device is ideally suited for Pentium
and
PowerPC pipelined systems and systems that benefit
from a very wide, high-speed data bus. The device is also
ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide
applications.
Please refer to the Micron Web site
(
www.micronsemi.com/en/products/sram/
) for the lat-
est data sheet.
76
V
SS
77
V
DD
Q
78
NC
DQb
79
NC
DQb
80
SA
NC/
DQPb
1
81
SA
82
SA
83
ADV#
84
ADSP#
85
ADSC#
86
OE# (G#)
87
BWE#
88
GW#
89
CLK
90
V
SS
91
V
DD
92
CE2#
93
BWa#
94
BWb#
95
NC
BWc#
96
NC
BWd#
97
CE2
98
CE#
99
SA
100
SA
4
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
PIN ASSIGNMENT (TOP VIEW)
100-PIN TQFP
NOTE: 1. No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
NC
NC
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
SA
NC
NC
V
DD
Q
V
SS
NC
DQPa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
NC
NC
V
SS
V
DD
Q
NC
NC
NC
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE (LBO#)
NC
NC
NC
V
DD
Q
V
SS
NC
NC
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
NC
V
DD
NC
V
SS
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQPb
NC
V
SS
V
DD
Q
NC
NC
NC
x18
SA
SA
ADV#
ADSP#
ADSC#
OE# (G#)
BWE#
GW#
CLK
V
SS
V
DD
CE2#
BWa#
BWb#
BWc#
BWd#
CE2
CE#
SA
SA
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
NC/
DQPb
1
DQb
DQb
V
DD
Q
V
SS
DQb
DQb
DQb
DQb
V
SS
V
DD
Q
DQb
DQb
V
SS
NC
V
DD
ZZ
DQa
DQa
V
DD
Q
V
SS
DQa
DQa
DQa
DQa
V
SS
V
DD
Q
DQa
DQa
NC/
DQPa
1
SA
SA
SA
SA
SA
SA
SA
SA
SA
V
DD
V
SS
DNU
DNU
SA0
SA1
SA
SA
SA
SA
MODE (LBO#)
NC/
DQPc
1
DQc
DQc
V
DD
Q
V
SS
DQc
DQc
DQc
DQc
V
SS
V
DD
Q
DQc
DQc
NC
V
DD
NC
V
SS
DQd
DQd
V
DD
Q
V
SS
DQd
DQd
DQd
DQd
V
SS
V
DD
Q
DQd
DQd
NC/
DQPd
1
x32/x36
5
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TQFP PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
37
37
SA0
Input
Synchronous Address Inputs: These inputs are registered and must
36
36
SA1
meet the setup and hold times around the rising edge of CLK.
32-35, 42-50,
32-35, 42-50,
SA
80-82, 99,
81, 82, 99,
100
100
93
93
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
94
94
BWb#
individual bytes to be written and must meet the setup and hold
95
BWc#
times around the rising edge of CLK. A byte write enable is LOW
96
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa pins and DQPa; BWb# controls DQb pins and
DQPb. For the x32 and x36 versions, BWa# controls DQa pins and
DQPa; BWb# controls DQb pins and DQPb; BWc# controls DQc pins
and DQPc; BWd# controls DQd pins and DQPd. Parity is only
available on the x18 and x36 versions.
87
87
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
88
88
GW#
Input
Global Write: This active LOW input allows a full 18-, 32-, or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and
must meet the setup and hold times around the rising edge of
CLK.
89
89
CLK
Input
Clock: This signal registers the address, data, chip enable, byte
write enables and burst control inputs on its rising edge. All
synchronous inputs must meet setup and hold times around the
clock's rising edge.
98
98
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is
sampled only when a new external address is loaded.
92
92
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
64
64
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored. This pin has an internal pull-down and can be floating.
97
97
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
86
86
OE#
Input
Output Enable: This
active LOW, asynchronous input enables the
(G#)
data I/O output drivers. G# is the JEDEC-standard term for OE#.
83
83
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after
the external address is loaded. A HIGH on this pin effectively
causes wait states to be generated (no address advance). To ensure
use of correct address during a WRITE cycle, ADV# must be HIGH at
the rising edge of the first clock after an ADSP# cycle is initiated.
(continued on next page)
6
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TQFP PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
84
84
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
85
85
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
31
31
MODE
Input
Mode: This input selects the burst sequence. A LOW on this pin
(LBO#)
selects "linear burst." NC or HIGH on this pin selects "interleaved
burst." Do not alter input state while device is operating. LBO# is
the JEDEC-standard term for MODE.
(a)
58, 59,
(a)
52, 53,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated with
62, 63, 68, 69, 56-59, 62, 63
Output DQa pins; Byte "b" is associated with DQb pins. For the x32 and
72, 73
x36 versions, Byte "a" is associated with DQa pins; Byte "b" is
(b)
8, 9, 12,
(b)
68, 69
DQb
associated with DQb pins; Byte "c" is associated with DQc pins;
13, 18, 19, 22, 72-75, 78, 79
Byte "d" is associated with DQd pins. Input data must meet setup
23
and hold times around the rising edge of CLK.
(c)
2, 3, 6-9,
DQc
12, 13
(d)
18, 19,
DQd
22-25, 28, 29
74
51
NC/
DQPa
NC/
No Connect/Parity Data I/Os: On the x32 version, these pins are No
24
80
NC/
DQPb
I/O
Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte
1
NC/
DQPc
"b" parity is DQPb. On the x36 version, Byte "a" parity is DQPa;
30
NC/
DQPd
Byte "b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is
DQPd.
15, 41, 65,
15, 41, 65,
V
DD
Supply Power Supply:
See DC Electrical Characteristics and Operating
91
91
Conditions for range.
4, 11, 20, 27,
4, 11, 20, 27,
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
54, 61, 70, 77 54, 61, 70, 77
Operating Conditions for range.
5, 10, 17, 21,
5, 10, 17, 21,
V
SS
Supply Ground:
GND.
26, 40, 55, 60, 26, 40, 55, 60,
67, 71, 76, 90 67, 71, 76, 90
38, 39
38, 39
DNU
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1-3, 6, 7, 14
14, 16, 66
NC
No Connect: These signals are not internally connected and may be
16, 25, 28-30,
connected to ground to improve package heat dissipation.
51-53, 56, 57,
66, 75, 78, 79,
95, 96
NA
NA
NF
No Function: These pins are internally connected to the die and
have the capacitance of an input pin. It is allowable to leave these
pins unconnected or driven by signals.
7
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
PIN LAYOUT (TOP VIEW)
165-PIN FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
V
SS
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
V
DD
DQb
DQb
DQb
DQb
DQPb
NC
MODE
(LBO#)
BWb#
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
NC
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
SA1
SA0
BWE#
GW#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
DNU
DNU
ADSC#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
ADV#
ADSP#
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
SA
SA
SA
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
SA
SA
TOP VIEW
3
4
5
6
7
8
9
10
11
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
CE#
CE2
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQc
DQc
DQc
DQc
V
SS
DQd
DQd
DQd
DQd
NC
NC
NC
NC
NC
NC/
DQPc
DQc
DQc
DQc
DQc
V
DD
DQd
DQd
DQd
DQd
NC/
DQPd
NC
MODE
(LBO#)
BWc#
BWd#
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
BWb#
BWa#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
DNU
DNU
CE2#
CLK
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
SA1
SA0
BWE#
GW#
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
DNU
DNU
ADSC#
OE# (G#)
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
SA
SA
ADV#
ADSP#
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
NC
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
V
DD
Q
SA
SA
SA
SA
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
SA
SA
NC
NC
NC/
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC/
DQPa
SA
SA
TOP VIEW
3
4
5
6
7
8
9
10
11
1
x18
x32/x36
*No Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version.
8
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA PIN DESCRIPTIONS
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
6R
6R
SA0
Input
Synchronous Address Inputs: These inputs are registered and must
6P
6P
SA1
meet the setup and hold times around the rising edge of CLK.
2A, 2B, 3P,
2A, 2B, 3P,
SA
3R, 4P, 4R, 6N, 3R, 4P, 4R, 6N,
8P, 8R, 9P, 9R,
8P, 8R, 9P,
10A, 10B, 10P, 9R, 10A, 10B,
10R, 11A, 11P, 10P, 10R, 11P,
11R
11R
5B
5B
BWa#
Input
Synchronous Byte Write Enables: These active LOW inputs allow
4A
5A
BWb#
individual bytes to be written and must meet the setup and hold
4A
BWc#
times around the rising edge of CLK. A byte write enable is LOW
4B
BWd#
for a WRITE cycle and HIGH for a READ cycle. For the x18 version,
BWa# controls DQa's and DQPa; BWb# controls DQb's and DQPb.
For the x32 and x36 versions, BWa# controls DQa's and DQPa; BWb#
controls DQb's and DQPb; BWc# controls DQc's and DQPc; BWd#
controls DQd's and DQPd. Parity is only available on the x18 and
x36 versions.
7A
7A
BWE#
Input
Byte Write Enable: This active LOW input permits BYTE WRITE
operations and must meet the setup and hold times around the
rising edge of CLK.
7B
7B
GW#
Input
Global Write: This active LOW input allows a full 18-, 32- or 36-bit
WRITE to occur independent of the BWE# and BWx# lines and must
meet the setup and hold times around the rising edge of CLK.
6B
6B
CLK
Input
Clock: This signal registers the address, data, chip enable, byte write
enables, and burst control inputs on its rising edge. All synchronous
inputs must meet setup and hold times around the clock's rising
edge.
3A
3A
CE#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and conditions the internal use of ADSP#. CE# is sampled
only when a new external address is loaded.
6A
6A
CE2#
Input
Synchronous Chip Enable: This active LOW input is used to enable
the device and is sampled only when a new external address is
loaded.
11H
11H
ZZ
Input
Snooze Enable: This active HIGH, asynchronous input causes the
device to enter a low-power standby mode in which all data in the
memory array is retained. When ZZ is active, all other inputs are
ignored.
3B
3B
CE2
Input
Synchronous Chip Enable: This active HIGH input is used to enable
the device and is sampled only when a new external address is
loaded.
8B
8B
OE#(G#)
Input
Output Enable: This
active LOW, asynchronous input enables the
data I/O output drivers.
(continued on next page)
9
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
9A
9A
ADV#
Input
Synchronous Address Advance: This active LOW input is used to
advance the internal burst counter, controlling burst access after the
external address is loaded. A HIGH on ADV# effectively causes wait
states to be generated (no address advance). To ensure use of
correct address during a WRITE cycle, ADV# must be HIGH at the
rising edge of the first clock after an ADSP# cycle is initiated.
9B
9B
ADSP#
Input
Synchronous Address Status Processor: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ is performed using the new address,
independent of the byte write enables and ADSC#, but dependent
upon CE#, CE2, and CE2#. ADSP# is ignored if CE# is HIGH. Power-
down state is entered if CE2 is LOW or CE2# is HIGH.
8A
8A
ADSC#
Input
Synchronous Address Status Controller: This active LOW input
interrupts any ongoing burst, causing a new external address to be
registered. A READ or WRITE is performed using the new address if
CE# is LOW. ADSC# is also used to place the chip into power-down
state when CE# is HIGH.
1R
1R
MODE
Input
Mode: This input selects the burst sequence. A LOW on this
(LB0#)
input selects "linear burst." NC or HIGH on this input selects
"interleaved burst." Do not alter input state while device is
operating.
(a)
10J, 10K,
(a)
10J, 10K,
DQa
Input/ SRAM Data I/Os: For the x18 version, Byte "a" is associated DQas;
10L, 10M, 11D, 10L, 10M, 11J,
Output Byte "b" is associated with DQbs. For the x32 and x36 versions,
11E, 11F, 11G 11K, 11L, 11M
Byte "a" is associated with DQas; Byte "b" is associated with DQbs;
(b)
1J, 1K,
(b)
10D, 10E,
DQb
Byte "c" is associated with DQcs; Byte "d" is associated with DQds.
1L, 1M, 2D,
10F, 10G, 11D,
Input data must meet setup and hold times around the rising edge
2E, 2F, 2G
11E, 11F, 11G
of CLK.
(c)
1D, 1E,
DQc
1F, 1G, 2D,
2E, 2F, 2G
(d)
1J, 1K, 1L,
DQd
1M, 2J, 2K,
2L, 2M
11C
11N
NC/
DQPa
NC/
No Connect/Parity Data I/Os: On the x32 version, these are No
1N
11C
NC/
DQPb
I/O
Connect (NC). On the x18 version, Byte "a" parity is DQPa; Byte "b"
1C
NC/
DQPc
parity is DQPb. On the x36 version, Byte "a" parity is DQPa; Byte
1N
NC/
DQPd
"b" parity is DQPb; Byte "c" parity is DQPc; Byte "d" parity is DQPd.
1H, 4D, 4E, 4F, 1H, 4D, 4E, 4F,
V
DD
Supply Power Supply:
See DC Electrical Characteristics and Operating
4G, 4H, 4J,
4G, 4H, 4J,
Conditions for range.
4K, 4L, 4M,
4K, 4L, 4M,
8D, 8E, 8F,
8D, 8E, 8F,
8G, 8H, 8J,
8G, 8H, 8J,
8K, 8L, 8M
8K, 8L, 8M
(continued on next page)
10
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA PIN DESCRIPTIONS (continued)
x18
x32/x36
SYMBOL
TYPE
DESCRIPTION
3C, 3D, 3E,
3C, 3D, 3E,
V
DD
Q
Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and
3F, 3G, 3J,
3F, 3G, 3J,
Operating Conditions for range.
3K, 3L, 3M,
3K, 3L, 3M,
3N, 9C, 9D,
3N, 9C, 9D,
9E, 9F, 9G,
9E, 9F, 9G,
9J, 9K, 9L,
9J, 9K, 9L,
9M, 9N
9M, 9N
2H, 4C, 4N, 5C, 2H, 4C, 4N, 5C,
V
SS
Supply Ground:
GND.
5D, 5E 5F,
5D, 5E 5F,
5G, 5H, 5J,
5G, 5H, 5J,
5K, 5L, 5M,
5K, 5L, 5M,
6C, 6D, 6E, 6F, 6C, 6D, 6E, 6F,
6G, 6H, 6J,
6G, 6H, 6J,
6K, 6L, 6M,
6K, 6L, 6M,
7C, 7D, 7E,
7C, 7D, 7E,
7F, 7G, 7H,
7F, 7G, 7H,
7J, 7K, 7L,
7J, 7K, 7L,
7M, 7N, 8C, 8N 7M, 7N, 8C, 8N
5P, 5R, 7P, 7R 5P, 5R, 7P, 7R
DNU
Do Not Use: These signals may either be unconnected or wired to
GND to improve package heat dissipation.
1A, 1B, 1C,
1A, 1B, 1P,
NC
No Connect: These signals are not internally connected and
1D, 1E, 1F,
2C, 2N, 2P,
may be connected to ground to improve package heat
1G, 1P, 2C,
2R, 3H, 5N,
dissipation.
2J, 2K, 2L,
9H, 10C, 10H,
2M, 2N, 2P,
10N, 11A, 11B
2R, 3H, 4B,
5A, 5N, 9H,
10C, 10D, 10E,
10F, 10G, 10H,
10N, 11B, 11J,
11K, 11L,
11M, 11N
11
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)
FIRST ADDRESS (EXTERNAL)
SECOND ADDRESS (INTERNAL)
THIRD ADDRESS (INTERNAL)
FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X00
X...X11
X...X10
X...X10
X...X11
X...X00
X...X01
X...X11
X...X10
X...X01
X...X00
LINEAR BURST ADDRESS TABLE (MODE = LOW)
FIRST ADDRESS (EXTERNAL)
SECOND ADDRESS (INTERNAL)
THIRD ADDRESS (INTERNAL)
FOURTH ADDRESS (INTERNAL)
X...X00
X...X01
X...X10
X...X11
X...X01
X...X10
X...X11
X...X00
X...X10
X...X11
X...X00
X...X01
X...X11
X...X00
X...X01
X...X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x18)
FUNCTION
GW#
BWE#
BWa#
BWb#
READ
H
H
X
X
READ
H
L
H
H
WRITE Byte "a"
H
L
L
H
WRITE Byte "b"
H
L
H
L
WRITE All Bytes
H
L
L
L
WRITE All Bytes
L
X
X
X
PARTIAL TRUTH TABLE FOR WRITE COMMANDS (x32/x36)
FUNCTION
GW#
BWE#
BWa#
BWb#
BWc#
BWd#
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE Byte "a"
H
L
L
H
H
H
WRITE All Bytes
H
L
L
L
L
L
WRITE All Bytes
L
X
X
X
X
X
NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written.
12
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TRUTH TABLE
(Notes 1-8)
ADDRESS
OPERATION
USED
CE# CE2# CE2
ZZ
ADSP# ADSC# ADV# WRITE# OE#
CLK
DQ
DESELECT Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
DESELECT Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
SNOOZE MODE, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE: 1. X means "Don't Care." # means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE#, L means any one or more byte write enable signals (BWa#, BWb#, BWc# or BWd#) and BWE# are LOW or
GW# is LOW. WRITE# = H for all BWx#, BWE#, GW# HIGH.
3. BWa# enables WRITEs to DQa's and DQPa. BWb# enables WRITEs to DQb's and DQPb. BWc# enables WRITEs to DQc's
and DQPc. BWd# enables WRITEs to DQd's and DQPd. DQPa and DQPb are only available on the x18 and x36 versions.
DQPc and DQPd are only available on the x36 version.
4. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE# must be HIGH before the input data setup time and held
HIGH throughout the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP# LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more
byte write enable signals and BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing
diagram for clarification.
13
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
3.3V V
DD
, ABSOLUTE MAXIMUM
RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
................................ -0.5V to +4.6V
Voltage on V
DD
Q Supply
Relative to V
SS
................................ -0.5V to +4.6V
V
IN
(DQx) .................................... -0.5V to V
DD
Q + 0.5V
V
IN
(inputs) ................................... -0.5V to V
DD
+ 0.5V
Storage Temperature (TQFP) .............. -55C to +150C
Storage Temperature (FBGA) .............. -55C to +125C
Junction Temperature** ................................... +150C
Short Circuit Output Current ............................ 100mA
2.5V V
DD
, ABSOLUTE MAXIMUM
RATINGS*
Voltage on V
DD
Supply
Relative to V
SS
................................ -0.3V to +3.6V
Voltage on V
DD
Q Supply
Relative to V
SS
................................ -0.3V to +3.6V
V
IN
(DQx) .................................... -0.3V to V
DD
Q + 0.3V
V
IN
(inputs) ................................... -0.3V to V
DD
+ 0.3V
Storage Temperature (TQFP) .............. -55C to +150C
Storage Temperature (FBGA) .............. -55C to +125C
Junction Temperature** ................................... +150C
Short Circuit Output Current ............................ 100mA
*Stresses greater than those listed under "Absolute Maxi-
mum Ratings" may cause permanent damage to the
device. This is a stress rating only, and functional opera-
tion of the device at these or any other conditions above
those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reli-
ability.
**Maximum junction temperature depends upon pack-
age type, cycle time, loading, ambient temperature and
airflow. See Micron Technical Note TN-05-14 for more
information.
3.3V V
DD
, 3.3V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +3.3V 0.165V; V
DD
Q = +3.3V 0.165V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
2.0
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.8
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Output High Voltage
I
OH
= -4.0mA
V
OH
2.4
V
1, 4
Output Low Voltage
I
OL
= 8.0mA
V
OL
0.4
V
1, 4
Supply Voltage
V
DD
3.135
3.465
V
1
Isolated Output Buffer Supply
V
DD
Q
3.135
3.465
V
1, 5
NOTE: 1. All voltages referenced to V
SS
(GND).
2. For 3.3V V
DD
:
Overshoot:
V
IH
+4.6V for t
t
KC/2 for I
20mA
Undershoot:
V
IL
-0.7V for t
t
KC/2 for I
20mA
Power-up:
V
IH
+3.6V and V
DD
3.135V for t 200ms
For 2.5V V
DD
:
Overshoot:
V
IH
+3.6V for t
t
KC/2 for I
20mA
Undershoot:
V
IL
-0.5V for t
t
KC/2 for I
20mA
Power-up:
V
IH
+2.65V and V
DD
2.375V for t 200ms
3. MODE has an internal pull-up, and input leakage = 10A.
4. The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the stated DC values. AC I/O
curves are available upon request.
5. V
DD
Q should never exceed V
DD
. V
DD
and V
DD
Q can be connected together.
14
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
3.3V V
DD
, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +3.3V 0.165V; V
DD
Q = +2.5V 0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
V
IH
Q
1.7
V
DD
Q + 0.3
V
1, 2
Inputs
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Q (DQx)
Output High Voltage
I
OH
= -2.0mA
V
OH
1.7
V
1, 4
I
OH
= -1.0mA
V
OH
2.0
V
1, 4
Output Low Voltage
I
OL
= 2.0mA
V
OL
0.7
V
1, 4
I
OL
= 1.0mA
V
OL
0.4
V
1, 4
Supply Voltage
V
DD
3.135
3.6
V
1
Isolated Output Buffer Supply
V
DD
Q
2.375
2.625
V
1
2.5V V
DD
, 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(0C
T
A
+70C; V
DD
= +2.5V 0.125V; V
DD
Q = +2.5V 0.125V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
Data bus (DQx)
V
IH
Q
1.7
V
DD
Q + 0.3
V
1, 2
Inputs
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-1.0
1.0
A
3
Output Leakage Current
Output(s) disabled,
IL
O
-1.0
1.0
A
0V
V
IN
V
DD
Q (DQx)
Output High Voltage
I
OH
= -2.0mA
V
OH
1.7
V
1, 4
I
OH
= -1.0mA
V
OH
2.0
V
1, 4
Output Low Voltage
I
OL
= 2.0mA
V
OL
0.7
V
1, 4
I
OL
= 1.0mA
V
OL
0.4
V
1, 4
Supply Voltage
V
DD
2.375
2.625
V
1
Isolated Output Buffer Supply
V
DD
Q
2.375
2.625
V
1
NOTE: 1. All voltages referenced to V
SS
(GND).
2. For 3.3V V
DD
:
Overshoot:
V
IH
+4.6V for t
t
KC/2 for I
20mA
Undershoot:
V
IL
-0.7V for t
t
KC/2 for I
20mA
Power-up:
V
IH
+3.6V and V
DD
3.135V for t 200ms
For 2.5V V
DD
:
Overshoot:
V
IH
+3.6V for t
t
KC/2 for I
20mA
Undershoot:
V
IL
-0.5V for t
t
KC/2 for I
20mA
Power-up:
V
IH
+2.65V and V
DD
2.375V for t 200ms
3. MODE has an internal pull-up, and input leakage = 10A.
4. The load used for V
OH
, V
OL
testing is shown in Figure 4 for 2.5V I/O. AC load current is higher than the shown DC
values. AC I/O curves are available upon request.
5. This parameter is sampled.
15
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TQFP THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Thermal Resistance
Test conditions follow standard test methods
JA
46
C/W
1
(Junction to Ambient)
and procedures for measuring thermal
Thermal Resistance
impedance, per EIA/JESD51.
JC
2.8
C/W
1
(Junction to Top of Case)
NOTE: 1. This parameter is sampled.
TQFP CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Control Input Capacitance
T
A
= 25C; f = 1 MHz;
C
I
3
4
pF
1
Input/Output Capacitance (DQ)
V
DD
= 3.3V
C
O
4
5
pF
1
Address Capacitance
C
A
3
3.5
pF
1
Clock Capacitance
C
CK
3
3.5
pF
1
FBGA THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
UNITS NOTES
Junction to Ambient
Test conditions follow standard test methods
q
JA
40
C/W
1
(Airflow of 1m/s)
and procedures for measuring thermal
Junction to Case (Top)
impedance, per EIA/JESD51.
q
JC
9
C/W
1
Junction to Pins
q
JB
17
C/W
1
(Bottom)
FBGA CAPACITANCE
DESCRIPTION
CONDITIONS
SYMBOL
TYP
MAX
UNITS
NOTES
Address/Control Input Capacitance
C
I
2.5
3.5
pF
1
Output Capacitance (Q)
T
A
= 25C; f = 1 MHz
C
O
4
5
pF
1
Clock Capacitance
C
CK
2.5
3.5
pF
1
16
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
NOTE: 1. If V
DD
= +3.3V, then V
DD
Q = +3.3V or +2.5V. If V
DD
= +2.5V, then V
DD
Q = +2.5V.
Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
2. I
DD
is specified with no output current and increases with faster cycle times. I
DD
Q increases with faster cycle times and
greater output loading.
3. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means
device is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25C, and 10ns cycle time.
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Note 1, unless otherwise noted)(0C
T
A
+70C)
DESCRIPTION
CONDITIONS
SYMBOL
TYP
-6
-7.5
-10
UNITS NOTES
Power Supply
Device selected; All inputs
V
IL
Current:
or
V
IH
; Cycle time
t
KC (MIN);
I
DD
225
475
425
325
mA
2, 3, 4
Operating
V
DD
= MAX; Outputs open
Power Supply
Device selected; V
DD
= MAX;
Current: Idle
ADSC#, ADSP#, GW#, BWx#, ADV#
I
DD
1
55
110
100
85
mA
2, 3, 4
V
IH
; All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
CMOS Standby
Device deselected; V
DD
= MAX;
All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
I
SB
2
0.4
10
10
10
mA
3, 4
All inputs static; CLK frequency = 0
TTL Standby
Device deselected; V
DD
= MAX;
All inputs
V
IL
or
V
IH
;
I
SB
3
8
25
25
25
mA
3, 4
All inputs static; CLK frequency = 0
Clock Running
Device deselected; V
DD
= MAX;
ADSC#, ADSP#, GW#, BWx#, ADV#
I
SB
4
55
110
90
85
mA
3, 4
V
IH
; All inputs
V
SS
+ 0.2 or
V
DD
- 0.2;
Cycle time
t
KC (MIN)
MAX
17
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
NOTE: 1. Test conditions as specified with the output loading shown in Figure 1 for +3.3V I/O (V
DD
Q = +3.3V 0.165V) and Figure
3 for 2.5V I/O (V
DD
Q = +2.5V 0.125V) unless otherwise noted.
2. Measured as HIGH above V
IH
and LOW below V
IL
.
3. This parameter is measured with the output loading shown in Figure 2.
4. This parameter is sampled.
5. Transition is measured 500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, "Synchronous SRAM Bus Contention Design Considerations," for a more thorough
discussion on these parameters.
7. OE# is a "Don't Care" when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the
required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
10. If V
DD
= +3.3V, then V
DD
Q = +3.3V or +2.5V. If V
DD
= +2.5V, then V
DD
Q = +2.5V.
Voltage tolerances: +3.3V 0.165 or +2.5V 0.125V for all values of V
DD
and V
DD
Q.
AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Notes 1, 10 unless otherwise noted) (0C
T
A
+70C)
-6
-7.5
-10
DESCRIPTION
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Clock
Clock cycle time
t
KC
6.0
7.5
10
ns
Clock frequency
f
KF
166
133
100
MHz
Clock HIGH time
t
KH
2.3
2.5
3.0
ns
2
Clock LOW time
t
KL
2.3
2.5
3.0
ns
2
Output Times
Clock to output valid
t
KQ
3.5
4.0
5.0
ns
Clock to output invalid
t
KQX
1.5
1.5
1.5
ns
3
Clock to output in Low-Z
t
KQLZ
0
0
0
ns
3, 4, 5, 6
Clock to output in High-Z
t
KQHZ
3.5
4.2
5.0
ns
3, 4, 5, 6
OE# to output valid
t
OEQ
3.5
4.2
5.0
ns
7
OE# to output in Low-Z
t
OELZ
0
0
0
ns
3, 4, 5, 6
OE# to output in High-Z
t
OEHZ
3.5
4.2
4.5
ns
3, 4, 5, 6
Setup Times
Address
t
AS
1.5
1.5
2.0
ns
8, 9
Address status (ADSC#, ADSP#)
t
ADSS
1.5
1.5
2.0
ns
8, 9
Address advance (ADV#)
t
AAS
1.5
1.5
2.0
ns
8, 9
Write signals
t
WS
1.5
1.5
2.0
ns
8, 9
(BWa#-BWd#, BWE#, GW#)
Data-in
t
DS
1.5
1.5
2.0
ns
8, 9
Chip enables (CE#, CE2#, CE2)
t
CES
1.5
1.5
2.0
ns
8, 9
Hold Times
Address
t
AH
0.5
0.5
0.5
ns
8, 9
Address status (ADSC#, ADSP#)
t
ADSH
0.5
0.5
0.5
ns
8, 9
Address advance (ADV#)
t
AAH
0.5
0.5
0.5
ns
8, 9
Write signals
t
WH
0.5
0.5
0.5
ns
8, 9
(BWa#-BWd#, BWE#, GW#)
Data-in
t
DH
0.5
0.5
0.5
ns
8, 9
Chip enables (CE#, CE2#, CE2)
t
CEH
0.5
0.5
0.5
ns
8, 9
18
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
Q
50
V = 1.5V
Z = 50
O
T
Figure 1
Q
351
317
5pF
+3.3V
Figure 2
3.3V V
DD
, 3.3V I/O AC TEST CONDITIONS
Input pulse levels ................... V
IH
= (V
DD
/2.2) + 1.5V
.................... V
IL
= (V
DD
/2.2) - 1.5V
Input rise and fall times ...................................... 1ns
Input timing reference levels ....................... V
DD
/2.2
Output reference levels ............................. V
DD
Q/2.2
Output load .............................. See Figures 1 and 2
LOAD DERATING CURVES
Micron 1 Meg x 18, 512K x 32 and 512K x 36
SyncBurst SRAM timing is dependent upon the capaci-
tive loading on the outputs.
Consult the factory for copies of I/O current versus
voltage curves.
3.3V I/O Output Load Equivalents
3.3V V
DD
, 2.5V I/O AC TEST CONDITIONS
Input pulse levels ............... V
IH
= (V
DD
/2.64) + 1.25V
................ V
IL
= (V
DD
/2.64) - 1.25V
Input rise and fall times ...................................... 1ns
Input timing reference levels ..................... V
DD
/2.64
Output reference levels ................................ V
DD
Q/2
Output load .............................. See Figures 3 and 4
2.5V V
DD
, 2.5V I/O AC TEST CONDITIONS
Input pulse levels .................... V
IH
= (V
DD
/2) + 1.25V
..................... V
IL
= (V
DD
/2) - 1.25V
Input rise and fall times ...................................... 1ns
Input timing reference levels .......................... V
DD
/2
Output reference levels ................................ V
DD
Q/2
Output load .............................. See Figures 3 and 4
Q
50
V = 1.25V
Z = 50
O
T
Figure 3
Q
351
317
5pF
+3.3V
Figure 4
2.5V I/O Output Load Equivalents
19
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
SNOOZE MODE
SNOOZE MODE is a low-current, "power-down"
mode in which the device is deselected and current is
reduced to I
SB
2Z
. The duration of SNOOZE MODE is
dictated by the length of time ZZ is in a HIGH state. After
the device enters SNOOZE MODE, all inputs except ZZ
become gated inputs and are ignored.
ZZ is an asynchronous, active HIGH input that causes
the device to enter SNOOZE MODE. When ZZ becomes
a logic HIGH, I
SB
2Z
is guaranteed after the setup time
t
ZZ
is met. Any READ or WRITE operation pending when
the device enters SNOOZE MODE is not guaranteed to
complete successfully. Therefore, SNOOZE MODE must
not be initiated until valid pending operations are
completed.
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Current during SNOOZE MODE
ZZ
V
IH
I
SB
2Z
10
mA
ZZ active to input ignored
t
ZZ
2(
t
KC)
ns
1
ZZ inactive to input sampled
t
RZZ
2(
t
KC)
ns
1
ZZ active to snooze current
t
ZZI
2(
t
KC)
ns
1
ZZ inactive to exit snooze current
t
RZZI
0
ns
1
NOTE: 1. This parameter is sampled.
SNOOZE MODE WAVEFORM
t
ZZ
I
SUPPLY
CLK
ZZ
t
RZZ
ALL INPUTS
(except ZZ)
DON'T CARE
I
ISB2Z
t
ZZI
t
RZZI
Outputs (Q)
High-Z
DESELECT or READ Only
20
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
READ TIMING
3
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
GW#, BWE#,
BWa#-BWd#
Q
High-Z
tKQLZ
tKQX
tKQ
ADV#
tOEHZ
tKQ
Single READ
BURST READ
tOEQ
tOELZ
tKQHZ
Burst wraps around
to its initial state.
tAAH
tAAS
tWH
tWS
tADSH
tADSS
Q(A2)
Q(A2 + 1)
Q(A2 + 2)
Q(A1)
Q(A2)
Q(A2 + 1)
Q(A3)
Q(A2 + 3)
A2
A3
(NOTE 1)
Deselect
cycle.
(NOTE 3)
Burst continued with
new base address.
(NOTE 4)
ADV# suspends burst.
DON'T CARE
UNDEFINED
NOTE: 1. Q(A2) refers to output from address A2. Q(A2 + 1) refers to output from the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause Q
to be driven until after the following clock rising edge.
4. Outputs are disabled within two clock cycles after deselect.
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
AS
1.5
1.5
2.0
ns
t
ADSS
1.5
1.5
2.0
ns
t
AAS
1.5
1.5
2.0
ns
t
WS
1.5
1.5
2.0
ns
t
CES
1.5
1.5
2.0
ns
t
AH
0.5
0.5
0.5
ns
t
ADSH
0.5
0.5
0.5
ns
t
AAH
0.5
0.5
0.5
ns
t
WH
0.5
0.5
0.5
ns
t
CEH
0.5
0.5
0.5
ns
READ TIMING PARAMETERS
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
KC
6.0
7.5
10
ns
f
KF
166
133
100
MHz
t
KH
2.3
2.5
3.0
ns
t
KL
2.3
2.5
3.0
ns
t
KQ
3.5
4.0
5.0
ns
t
KQX
1.5
1.5
1.5
ns
t
KQLZ
0
0
1.0
ns
t
KQHZ
3.5
4.2
5.0
ns
t
OEQ
3.5
4.2
5.0
ns
t
OELZ
0
0
0
ns
t
OEHZ
3.5
4.2
4.5
ns
21
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
WRITE TIMING
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A1
tCEH
tCES
BWE#,
BWa#-BWd#
Q
High-Z
ADV#
BURST READ
BURST WRITE
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A3)
D(A3 + 1)
D(A3 + 2)
D(A2 + 3)
A2
A3
D
Extended BURST WRITE
D(A2 + 2)
Single WRITE
tADSH
tADSS
tADSH
tADSS
tOEHZ
tAAH
tAAS
tWH
tWS
tDH
tDS
(NOTE 3)
(NOTE 1)
(NOTE 4)
GW#
tWH
tWS
(NOTE 5)
Byte write signals are ignored for first cycle when
ADSP# initiates burst.
ADSC# extends burst.
ADV# suspends burst.
DON'T CARE
UNDEFINED
D(A1)
NOTE: 1. D(A2) refers to input for address A2. D(A2 + 1) refers to input for the next internal burst address following A2.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. OE# must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/
output data contention for the time period prior to the byte write enable inputs being sampled.
4. ADV# must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW# LOW; or by GW# HIGH, BWE# LOW and BWa#-BWb# LOW for x18 device; or
GW# HIGH, BWE# LOW and BWa#-BWd# LOW for x32 and x36 devices.
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
DS
1.5
1.5
2.0
ns
t
CES
1.5
1.5
2.0
ns
t
AH
0.5
0.5
0.5
ns
t
ADSH
0.5
0.5
0.5
ns
t
AAH
0.5
0.5
0.5
ns
t
WH
0.5
0.5
0.5
ns
t
DH
0.5
0.5
0.5
ns
t
CEH
0.5
0.5
0.5
ns
WRITE TIMING PARAMETERS
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
KC
6.0
7.5
10
ns
f
KF
166
133
100
MHz
t
KH
2.3
2.5
3.0
ns
t
KL
2.3
2.5
3.0
ns
t
OEHZ
3.5
4.2
4.5
ns
t
AS
1.5
1.5
2.0
ns
t
ADSS
1.5
1.5
2.0
ns
t
AAS
1.5
1.5
2.0
ns
t
WS
1.5
1.5
2.0
ns
22
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
READ/WRITE TIMING
3
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 5)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
BWE#,
BWa#-BWd#
(NOTE 4)
A3
DON'T CARE
UNDEFINED
NOTE: 1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
ADSS
1.5
1.5
2.0
ns
t
WS
1.5
1.5
2.0
ns
t
DS
1.5
1.5
2.0
ns
t
CES
1.5
1.5
2.0
ns
t
AH
0.5
0.5
0.5
ns
t
ADSH
0.5
0.5
0.5
ns
t
WH
0.5
0.5
0.5
ns
t
DH
0.5
0.5
0.5
ns
t
CEH
0.5
0.5
0.5
ns
READ/WRITE TIMING PARAMETERS
-6
-7.5
-10
SYM
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
t
KC
6.0
7.5
10
ns
f
KF
166
133
100
MHz
t
KH
2.3
2.5
3.0
ns
t
KL
2.3
2.5
3.0
ns
t
KQ
3.5
4.0
5.0
ns
t
KQLZ
0
0
1.0
ns
t
OELZ
0
0
0
ns
t
OEHZ
3.5
4.2
4.5
ns
t
AS
1.5
1.5
2.0
ns
23
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
IEEE 1149.1 SERIAL BOUNDARY SCAN
(JTAG)
The SRAM incorporates a serial boundary scan test
access port (TAP). This port operates in accordance with
IEEE Standard 1149.1-1990 but does not have the set of
functions required for full 1149.1 compliance. These
functions from the IEEE specification are excluded be-
cause their inclusion places an added delay in the critical
speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the
operation of other devices using 1149.1 fully compliant
TAPs. The TAP operates using JEDEC-standard 2.5V I/O
logic levels.
The SRAM contains a TAP controller, instruction
register, boundary scan register, bypass register and ID
register.
DISABLING THE JTAG FEATURE
These pins can be left floating (unconnected), if the
JTAG function is not to be implemented. Upon power-
up, the device will come up in a reset state which will not
interfere with the operation of the device.
TEST ACCESS PORT (TAP)
TEST CLOCK (TCK)
The test clock is used only with the TAP controller.
All inputs are captured on the rising edge of TCK. All
outputs are driven from the falling edge of TCK.
TEST MODE SELECT (TMS)
The TMS input is used to give commands to the TAP
controller and is sampled on the rising edge of TCK. It is
allowable to leave this pin unconnected if the TAP is not
used. The pin is pulled up internally, resulting in a logic
HIGH level.
TEST DATA-IN (TDI)
The TDI pin is used to serially input information into
the registers and can be connected to the input of any of
the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP
instruction register. For information on loading the
instruction register, see Figure 5. TDI is internally pulled
up and can be unconnected if the TAP is unused in an
application. TDI is connected to the most significant bit
(MSB) of any register. (See Figure 6.)
Figure 5
TAP Controller State Diagram
NOTE: The 0/1 next to each state represents the value of TMS at the rising edge of TCK.
TEST-LOGIC
RESET
RUN-TEST/
IDLE
SELECT
DR-SCAN
SELECT
IR-SCAN
CAPTURE-DR
SHIFT-DR
CAPTURE-IR
SHIFT-IR
EXIT1-DR
PAUSE-DR
EXIT1-IR
PAUSE-IR
EXIT2-DR
UPDATE-DR
EXIT2-IR
UPDATE-IR
1
1
1
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
24
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TEST DATA-OUT (TDO)
The TDO output pin is used to serially clock data-out
from the registers. The output is active depending upon
the current state of the TAP state machine. (See Figure 5.)
The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any regis-
ter. (See Figure 6.)
PERFORMING A TAP RESET
A RESET is performed by forcing TMS HIGH (V
DD
) for
five rising edges of TCK. This RESET does not affect the
operation of the SRAM and may be performed while the
SRAM is operating.
At power-up, the TAP is reset internally to ensure that
TDO comes up in a High-Z state.
TAP REGISTERS
Registers are connected between the TDI and TDO
pins and allow data to be scanned into and out of the
SRAM test circuitry. Only one register can be selected at
a time through the instruction register. Data is serially
loaded into the TDI pin on the rising edge of TCK. Data
is output on the TDO pin on the falling edge of TCK.
INSTRUCTION REGISTER
Three-bit instructions can be serially loaded into the
instruction register. This register is loaded when it is
placed between the TDI and TDO pins as shown in
Figure 5. Upon power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded
with the IDCODE instruction if the controller is placed
in a reset state as described in the previous section.
When the TAP controller is in the Capture-IR state,
the two least significant bits are loaded with a binary
"01" pattern to allow for fault isolation of the board-
level serial test data path.
BYPASS REGISTER
To save time when serially shifting data through
registers, it is sometimes advantageous to skip certain
chips. The bypass register is a single-bit register that can
be placed between the TDI and TDO pins. This allows
data to be shifted through the SRAM with minimal
delay. The bypass register is set LOW (V
SS
) when the
BYPASS instruction is executed.
BOUNDARY SCAN REGISTER
The boundary scan register is connected to all the
input and bidirectional pins on the SRAM. Several no
connect (NC) pins are also included in the scan register
to reserve pins for 9Mb and 18Mb Claymore SRAMs. The
x36 configuration has a 68-bit-long register, and the x18
configuration has a 49-bit-long register.
The boundary scan register is loaded with the con-
tents of the RAM I/O ring when the TAP controller is in
the Capture-DR state and is then placed between the TDI
and TDO pins when the controller is moved to the Shift-
DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE
Z instructions can be used to capture the contents of the
I/O ring.
The Boundary Scan Order tables show the order in
which the bits are connected. Each bit corresponds to
one of the bumps on the SRAM package. The MSB of the
Bypass Register
0
Instruction Register
0
1
2
Identification Register
0
1
2
29
30
31
.
.
.
Boundary Scan Register*
0
1
2
.
.
x
.
.
.
Selection
Circuitry
Selection
Circuitry
TCK
TMS
TAP CONTROLLER
TDI
TDO
*x = 49 for the x18 configuration, x = 68 for the x36 configuration.
Figure 6
TAP Controller Block Diagram
25
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
register is connected to TDI, and the LSB is connected to
TDO.
IDENTIFICATION (ID) REGISTER
The ID register is loaded with a vendor-specific, 32-
bit code during the Capture-DR state when the IDCODE
command is loaded in the instruction register. The
IDCODE is hardwired into the SRAM and can be shifted
out when the TAP controller is in the Shift-DR state. The
ID register has a vendor code and other information
described in the Identification Register Definitions table.
TAP INSTRUCTION SET
OVERVIEW
Eight different instructions are possible with the
three-bit instruction register. All combinations are listed
in the Instruction Codes table. Three of these instruc-
tions are listed as RESERVED and should not be used.
The other five instructions are described in detail below.
The TAP controller used in this SRAM is not fully
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST or
the PRELOAD portion of SAMPLE/PRELOAD; rather it
performs a capture of the I/O ring when these instruc-
tions are executed.
Instructions are loaded into the TAP controller dur-
ing the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instruc-
tions are shifted through the instruction register through
the TDI and TDO pins. To execute the instruction once
it is shifted in, the TAP controller needs to be moved into
the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction which is
to be executed whenever the instruction register is loaded
with all 0s. EXTEST is not implemented in this SRAM
TAP controller, and therefore this device is not compli-
ant to 1149.1.
The TAP controller does recognize an all-0 instruc-
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a SAMPLE/
PRELOAD instruction has been loaded. There is one
difference between the two instructions. Unlike the
SAMPLE/PRELOAD instruction, EXTEST places the SRAM
outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific,
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI and
TDO pins and allows the IDCODE to be shifted out of the
device when the TAP controller enters the Shift-DR
state. The IDCODE instruction is loaded into the in-
struction register upon power-up or whenever the TAP
controller is given a test logic reset state.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan
register to be connected between the TDI and TDO pins
when the TAP controller is in a Shift-DR state. It also
places all SRAM outputs into a High-Z state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
When the SAMPLE/PRELOAD instruction is loaded
into the instruction register and the TAP controller is in
the Capture-DR state, a snapshot of data on the inputs
and bi-directional pins is captured in the boundary scan
register.
The user must be aware that the TAP controller clock
can only operate at a frequency up to 10 MHz, while the
SRAM clock operates more than an order of magnitude
faster. Because there is a large difference in the clock
frequencies, it is possible that during the Capture-DR
state, an input or output will undergo a transition. The
TAP may then try to capture a signal while in transition
(metastable state). This will not harm the device, but
there is no guarantee as to the value that will be cap-
tured. Repeatable results may not be possible.
To guarantee that the boundary scan register will
capture the correct value of a signal, the SRAM signal
must be stabilized long enough to meet the TAP
controller's capture setup plus hold time (
t
CS plus
t
CH).
The SRAM clock input might not be captured correctly
if there is no way in a design to stop (or slow) the clock
during a SAMPLE/PRELOAD instruction. If this is an
issue, it is still possible to capture all other signals and
simply ignore the value of the CK and CK# captured in
the boundary scan register.
Once the data is captured, it is possible to shift out the
data by putting the TAP into the Shift-DR state. This
places the boundary scan register between the TDI and
TDO pins.
Note that since the PRELOAD part of the command
is not implemented, putting the TAP to the Update-DR
state while performing a SAMPLE/PRELOAD instruction
will have the same effect as the Pause-DR command.
26
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
BYPASS
When the BYPASS instruction is loaded in the in-
struction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between TDI and TDO.
The advantage of the BYPASS instruction is that it
shortens the boundary scan path when multiple devices
are connected together on a board.
RESERVED
These instruction are not implemented but are re-
served for future use. Do not use these instructions.
t
TLTH
Test Clock
(TCK)
1
2
3
4
5
6
Test Mode Select
(TMS)
tTHTL
Test Data-Out
(TDO)
tTHTH
Test Data-In
(TDI)
tTHMX
tMVTH
tTHDX
tDVTH
tTLOX
tTLOV
DON'T CARE
UNDEFINED
TAP TIMING
TAP AC ELECTRICAL CHARACTERISTICS
(Notes 1, 2) (+20C
T
J
+100C; +2.4V V
DD
+2.6V)
DESCRIPTION
SYMBOL
MIN
MAX
UNITS
Clock
Clock cycle time
t
THTH
100
ns
Clock frequency
f
TF
10
MHz
Clock HIGH time
t
THTL
40
ns
Clock LOW time
t
TLTH
40
ns
Output Times
TCK LOW to TDO unknown
t
TLOX
0
ns
TCK LOW to TDO valid
t
TLOV
20
ns
TDI valid to TCK HIGH
t
DVTH
10
ns
TCK HIGH to TDI invalid
t
THDX
10
ns
Setup Times
TMS setup
t
MVTH
10
ns
Capture setup
t
CS
10
ns
Hold Times
TMS hold
t
THMX
10
ns
Capture hold
t
CH
10
ns
NOTE: 1.
t
CS and
t
CH refer to the setup and hold time requirements of latching data from the boundary scan register.
2. Test conditions are specified using the load in Figure 7.
27
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
TAP AC TEST CONDITIONS
Input pulse levels ....................................... V
SS
to 2.5V
Input rise and fall times ......................................... 1ns
Input timing reference levels ............................. 1.25V
Output reference levels ..................................... 1.25V
Test load termination supply voltage ............... 1.25V
TDO
1.25V
20pF
Z = 50
O
50
Figure 7
TAP AC Output Load Equivalent
TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(+20C
T
J
+110C; +2.4V V
DD
+2.6V unless otherwise noted)
DESCRIPTION
CONDITIONS
SYMBOL
MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
V
IH
1.7
V
DD
+ 0.3
V
1, 2
Input Low (Logic 0) Voltage
V
IL
-0.3
0.7
V
1, 2
Input Leakage Current
0V
V
IN
V
DD
IL
I
-5.0
5.0
A
Output Leakage Current
Output(s) disabled,
IL
O
-5.0
5.0
A
0V
V
IN
V
DD
Q (DQx)
Output Low Voltage
I
OLC
= 100A
V
OL
1
0.2
V
1
Output Low Voltage
I
OLT
= 2mA
V
OL
2
0.7
V
1
Output High Voltage
I
OHC
= -100A
V
OH
1
2.1
V
1
Output High Voltage
I
OHT
= -2mA
V
OH
2
1.7
V
1
NOTE: 1. All voltages referenced to V
SS
(GND).
2. Overshoot:
V
IH
(AC)
V
DD
+ 1.5V for t
t
KHKH/2
Undershoot:
V
IL
(AC)
-0.5V for t
t
KHKH/2
Power-up:
V
IH
+2.6V and V
DD
2.4V and V
DD
Q
1.4V for t 200ms
During normal operation, V
DD
Q must not exceed V
DD
. Control input signals (such as LD#, R/W#, etc.) may not have
pulse widths less than
t
KHKL (MIN) or operate at frequencies exceeding
f
KF (MAX).
28
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
IDENTIFICATION REGISTER DEFINITIONS
INSTRUCTION FIELD
512K x 18
DESCRIPTION
REVISION NUMBER
xxxx
Reserved for version number.
(31:28)
DEVICE DEPTH
00111
Defines depth of 256K or 512K words.
(27:23)
DEVICE WIDTH
00011
Defines width of x18 or x36 bits.
(22:18)
MICRON DEVICE ID
xxxxxx
Reserved for future use.
(17:12)
MICRON JEDEC ID
00000101100
Allows unique identification of SRAM vendor.
CODE (11:1)
ID Register Presence
1
Indicates the presence of an ID register.
Indicator (0)
SCAN REGISTER SIZES
REGISTER NAME
BIT SIZE
Instruction
3
Bypass
1
ID
32
Boundary Scan
68
INSTRUCTION CODES
INSTRUCTION
CODE
DESCRIPTION
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between TDI
and TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Forces all SRAM output drivers to a High-Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO.
Does not affect SRAM operation. This instruction does not implement 1149.1 preload
function and is therefore not 1149.1-compliant.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not affect
SRAM operations.
29
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA BOUNDARY SCAN ORDER (x18)
FBGA BIT#
SIGNAL NAME
PIN ID
FBGA BIT#
SIGNAL NAME
PIN ID
1
SA
TBD
2
SA
TBD
3
SA
TBD
4
SA
TBD
5
SA
TBD
6
SA
TBD
7
SA
TBD
8
DQa
TBD
9
DQa
TBD
10
DQa
TBD
11
DQa
TBD
12
ZZ
TBD
13
DQa
TBD
14
DQa
TBD
15
DQa
TBD
16
DQa
TBD
17
DQPa
TBD
18
SA
TBD
19
SA
TBD
20
SA
TBD
21
ADV#
TBD
22
ADSP
TBD
23
ADSC#
TBD
24
OE# (G#)
TBD
25
BWE#
TBD
26
GW#
TBD
27
CLK
TBD
28
SA
TBD
29
BWa#
TBD
30
BWb#
TBD
31
SA
TBD
32
CE#
TBD
33
SA
TBD
34
SA
TBD
35
DQb
TBD
36
DQb
TBD
37
DQb
TBD
38
DQb
TBD
39
V
DD
TBD
40
DQb
TBD
41
DQb
TBD
42
DQb
TBD
43
DQb
TBD
44
DQPb
TBD
45
MODE (LBO#)
TBD
46
SA
TBD
47
SA
TBD
48
SA
TBD
49
SA
TBD
50
SA1
TBD
51
SA0
TBD
30
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA BOUNDARY SCAN ORDER (x32/36)
36
SA
TBD
37
BWa#
TBD
38
BWb#
TBD
39
BWc#
TBD
40
BWd#
TBD
41
SA
TBD
42
CE#
TBD
43
SA
TBD
44
SA
TBD
45
NC/
DQPc
TBD
46
DQc
TBD
47
DQc
TBD
48
DQc
TBD
49
DQc
TBD
50
DQc
TBD
51
DQc
TBD
52
DQc
TBD
53
DQc
TBD
54
V
DD
TBD
55
DQd
TBD
56
DQd
TBD
57
DQd
TBD
58
DQd
TBD
59
DQd
TBD
60
DQd
TBD
61
DQd
TBD
62
DQd
TBD
63
NC/
DQPd
TBD
64
MODE (LBO#)
TBD
65
SA
TBD
66
SA
TBD
67
SA
TBD
68
SA
TBD
69
SA1
TBD
70
SA0
TBD
FBGA BIT#
SIGNAL NAME
PIN ID
FBGA BIT#
SIGNAL NAME
PIN ID
1
SA
TBD
2
SA
TBD
3
SA
TBD
4
SA
TBD
5
SA
TBD
6
SA
TBD
7
SA
TBD
8
NC/
DQPa
TBD
9
DQa
TBD
10
DQa
TBD
11
DQa
TBD
12
DQa
TBD
13
DQa
TBD
14
DQa
TBD
15
DQa
TBD
16
DQa
TBD
17
ZZ
TBD
18
DQb
TBD
19
DQb
TBD
20
DQb
TBD
21
DQb
TBD
22
DQb
TBD
23
DQb
TBD
24
DQb
TBD
25
DQb
TBD
26
NC/
DQPb
TBD
27
SA
TBD
28
SA
TBD
29
ADV#
TBD
30
ADSP#
TBD
31
ADSC#
TBD
32
OE# (G#)
TBD
33
BWE#
TBD
34
GW#
TBD
35
CLK
TBD
31
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
FBGA PART MARKING GUIDE
S D K P C
Product Family
S = SRAM

M = SRAM Mechanical sample
X = SRAM Engineering sample
Product Type
B = QDR
TM
burst of 2
C = QDR
burst of 4
D = DDR
F = SyncBurst
TM
, Pipelined, Single-Cycle Deslect
G = SyncBurst, Pipelined, Double-Cycle Deslect
H = SyncBurst, Flow-Through
J = ZBT
, Pipelined
K = ZBT, Flow-Through
Density
B = 2Mb, 3.3V V
DD
C = 2Mb, 2.5V V
DD
D = 2Mb, 1.8V V
DD
F = 4Mb, 3.3V V
DD
G = 4Mb, 2.5V V
DD
H = 4Mb, 1.8V V
DD
J = 8Mb, 3.3V V
DD
K = 8Mb, 2.5V V
DD
L = 8Mb, 1.8V V
DD
M = 16Mb, 3.3V V
DD
N = 16Mb, 2.5V V
DD
P = 16Mb, 1.8V V
DD
Width
B = x18, 3.3V V
DD
Q
C = x18, 2.5V V
DD
Q
D = x18, 3.3V & 2.5V V
DD
Q
F = x18, HSTL V
DD
Q
G = x32, 3.3V V
DD
Q
H = x32, 2.5V V
DD
Q
J = x32, 3.3V & 2.5V V
DD
Q
K = x32, HSTL V
DD
Q
L = x36, 3.3V V
DD
Q
M = x36, 2.5V V
DD
Q
N = x36, 3.3V & 2.5V V
DD
Q
P = x36, HSTL V
DD
Q
Q = x72, 3.3V V
DD
Q
R = x72, 2.5V V
DD
Q
S = x72, 3.3V & 2.5V V
DD
Q
T = x72, HSTL V
DD
Q
Speed Grade
B = -3
C = -3.3
D = -4
F = -4.4
G = -5
H = -6
J = -7
K = -7.5
Q = 32Mb, 3.3V V
DD
R = 32Mb, 2.5V V
DD
S = 32Mb, 1.8V V
DD
T = 64Mb, 3.3V V
DD
V = 64Mb, 2.5V V
DD
W = 64Mb, 1.8V V
DD
X = 128Mb, 3.3V V
DD
Y = 128Mb, 2.5V V
DD
Z = 128Mb, 1.8V V
DD
L = -8
M = -8.5
N = -9
P = -9.5
Q = -10
R = -10.5
S = -11
T = -12
QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and
Micron Technology, Inc.
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by
Micron Technology, Inc., and Motorola Inc.
32
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
100-PIN PLASTIC TQFP
(JEDEC LQFP)
14.00 0.10
20.10 0.10
0.62
22.10
+0.10
-0.15
16.00
+0.20
-0.05
PIN #1 ID
0.65
1.50 0.10
0.25
0.60 0.15
1.40 0.05
0.32
+0.06
-0.10
0.15
+0.03
-0.02
0.10
+0.10
-0.05
DETAIL A
DETAIL A
1.00 (TYP)
GAGE PLANE
0.10
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
33
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
165-PIN FBGA
NOTE: 1. All dimensions in millimeters MAX or typical where noted.
MIN
2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
10.00
14.00
15.00 0.10
1.00
(TYP)
1.00
(TYP)
5.00 0.05
13.00 0.10
PIN A1 ID
PIN A1 ID
MOLD COMPOUND: EPOXY NOVOLAC
SUBSTRATE: PLASTIC LAMINATE
6.50 0.05
7.00 0.05
7.50 0.05
1.20 MAX
SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb
SOLDER BALL PAD: .33mm
SEATING PLANE
0.85 0.075
0.10 A
A
TYP
.45
+.05
-.10
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
SyncBurst is a trademark and Micron is a registered trademark of Micron Technology, Inc.
Pentium is a registered trademark of Intel Corporation.
34
16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT58L1MY18D_2.p65 Rev 7/00
2000, Micron Technology, Inc.
16Mb: 1 MEG x 18, 512K x 32/36
PIPELINED, DCD SYNCBURST SRAM
ADVANCE
REVISION HISTORY
Changed FBGA capacitance values, Rev. 7/00, ADVANCE ............................................................................... Aug/8/00
C
I
; TYP 2.5 pF from 4 pF; MAX 3.5 pF from 5 pF
C
O
; TYP 4 pF from 6 pF; MAX 5 pF from 7 pF
C
CK
; TYP 2.5 pF from 5 pF; MAX 3.5 pF from 6 pF
Removed Industrial Temperature references, Rev. 7/00, ADVANCE .............................................................. July/24/00
Added 165-pin FBGA package, Rev. 7/00, ADVANCE .................................................................................... Jun/28/00
Added FBGA part marking references
Removed 119-pin PBGA and references
Added Note: "IT available for -8.5 and -10 speed grades"
Change Pin 14 to NC from V
DD
, Rev. 4/00, ADVANCE .................................................................................. Apr/13/00
Added note: ZZ has internal pull-down
Updated Boundary Scan Order, Rev. 3/00, ADVANCE ..................................................................................... Apr/6/00
Added ADVANCE status, Rev. 1/00, ADVANCE .............................................................................................. Jan/18/00
MT58L1MY18D, Rev. 11/99, ADVANCE ........................................................................................................ Nov/11/99
Added BGA JTAG functionality