Document Outline
- Features
- Options
- Key Timing Parameters
- Pin Assignment (Front View) 168-Pin DIMM
- Part Numbers
- General Description
- Refresh
- Serial Presence-Detect Operation
- SPD Clock and Data Conventions
- SPD Start Condition
- SPD Stop Condition
- Functional Block Diagrams
- MT4LDT464A(X) (32MB)
- MT8LDT864A(X) (64MB)
- Pin Descriptions
- Figure 1 Data Validity
- Figure 2 Definition of Start and Stop
- Figure 3 Acknowledge Response from Receiver
- Serial Presence-Detect Matrix
- Absolute Maximum Ratings
- DC Electrical Characteristics and Operating Conditions
- IDD Operating Conditions and Maximum Limits
- Capacitance
- Fast Page Mode AC Electrical Characteristics
- Fast Page Mode AC Electrical Characteristics
- EDO Page Mode AC Electrical Characteristics
- EDO Page Mode AC Electrical Characteristics
- Serial Presence-Detect EEPROM Operating Conditions
- Serial Presence-Detect EEPROM AC Electrical Characteristics
- Notes
- Read Cycle
- Early Write Cycle
- EDO-Page-Mode Read Cycle
- Fast-Page-Mode Read Cycle
- Fast/EDO-Page-Mode Early Write Cycle
- Read-Write Cycle
- Fast/EDO-Page Mode Read-Write Cycle
- Fast-Page-Mode Read Early Write Cycle
- EDO-Page-Mode Read Early Write Cycle
- EDO Read Cycle
- RAS#-Only Refresh Cycle
- Hidden Refresh Cycle
- SPD EEPROM
- 168-Pin DIMMs
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
1
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
DRAM
MODULE
MT4LDT464A (X), MT8LDT864A (X)
For the latest data sheet, please refer to the Micron Web
site:
www.micronsemi.com/datasheets/datasheet.html
PIN ASSIGNMENT (Front View)
FEATURES
JEDEC-standard ECC pinout in a 168-pin, dual in-
line memory module (DIMM)
32MB (4 Meg x 64) and 64MB (8 Meg x 64)
Nonbuffered
High-performance CMOS silicon-gate process
Single +3.3V 0.3V power supply
All inputs, outputs and clocks are LVTTL-
compatible
4,096-cycle CAS#-BEFORE-RAS# (CBR) refresh
distributed across 64ms
FAST-PAGE-MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
Serial presence-detect (SPD)
OPTIONS
MARKING
Package
168-pin DIMM (gold)
G
Timing
50ns access
-5
60ns access
-6
Access Cycle
FAST PAGE MODE
None
EDO PAGE MODE
X
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
PIN
SYMBOL
1
V
SS
43
V
SS
85
V
SS
127
V
SS
2
DQ0
44
OE2#
86
DQ32
128
RFU
3
DQ1
45
RAS2#
87
DQ33
129
RAS3#
4
DQ2
46
CAS2#
88
DQ34
130
CAS6#
5
DQ3
47
CAS3#
89
DQ35
131
CAS7#
6
V
DD
48
WE2#
90
V
DD
132
RFU
7
DQ4
49
V
DD
91
DQ36
133
V
DD
8
DQ5
50
NC
92
DQ37
134
NC
9
DQ6
51
NC
93
DQ38
135
NC
10
DQ7
52
NC
94
DQ39
136
NC
11
DQ8
53
NC
95
DQ40
137
NC
12
V
SS
54
V
SS
96
V
SS
138
V
SS
13
DQ9
55
DQ16
97
DQ41
139
DQ48
14
DQ10
56
DQ17
98
DQ42
140
DQ49
15
DQ11
57
DQ18
99
DQ43
141
DQ50
16
DQ12
58
DQ19
100
DQ44
142
DQ51
17
DQ13
59
V
DD
101
DQ45
143
V
DD
18
V
DD
60
DQ20
102
V
DD
144
DQ52
19
DQ14
61
NC
103
DQ46
145
NC
20
DQ15
62
RFU
104
DQ47
146
RFU
21
NC
63
NC
105
NC
147
NC
22
NC
64
V
SS
106
NC
148
V
SS
23
V
SS
65
DQ21
107
V
SS
149
DQ53
24
NC
66
DQ22
108
NC
150
DQ54
25
NC
67
DQ23
109
NC
151
DQ55
26
V
DD
68
V
SS
110
V
DD
152
V
SS
27
WE0#
69
DQ24
111
RFU
153
DQ56
28
CAS0#
70
DQ25
112
CAS4#
154
DQ57
29
CAS1#
71
DQ26
113
CAS5#
155
DQ58
30
RAS0#
72
DQ27
114
RAS1#
156
DQ59
31
OE0#
73
V
DD
115
RFU
157
V
DD
32
V
SS
74
DQ28
116
V
SS
158
DQ60
33
A0
75
DQ29
117
A1
159
DQ61
34
A2
76
DQ30
118
A3
160
DQ62
35
A4
77
DQ31
119
A5
161
DQ63
36
A6
78
V
SS
120
A7
162
V
SS
37
A8
79
NC
121
A9
163
NC
38
A10
80
NC
122
A11
164
NC
39
NC (A12)
81
NC
123
NC (A13)
165
SA0
40
V
DD
82
SDA
124
V
DD
166
SA1
41
V
DD
83
SCL
125
RFU
167
SA2
42
RFU
84
V
DD
126
RFU
168
V
DD
168-Pin DIMM
(H-10; 32MB), (H-11; 64MB)
NOTE:
Pin symbols in parentheses are not used on these modules
but may be used for other modules in this product family.
They are for reference only.
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
-5
84ns
50ns
20ns
25ns
13ns
8ns
-6
104ns
60ns
25ns
30ns
15ns
10ns
FPM Operating Mode
SPEED
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
-5
90ns
50ns
30ns
25ns
13ns
30ns
-6
110ns
60ns
35ns
30ns
15ns
40ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
2
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
GENERAL DESCRIPTION
The MT4LDT464A (X) and MT8LDT864A (X) are
randomly accessed 32MB and 64MB memories orga-
nized in a x64 configuration. They are specially pro-
cessed to operate from 3V to 3.6V for low-voltage
memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 22 address bits, which are en-
tered 12 bits (A0-A11) at RAS# time and 10 bits (A0-A9)
at CAS# time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates read mode, while
a logic LOW on WE# dictates write mode. During a
WRITE cycle, data-in (D) is latched by the falling edge
of WE# or CAS#, whichever occurs last. An EARLY
WRITE occurs when WE# is taken LOW prior to CAS#
falling. A LATE WRITE or READ-MODIFY-WRITE oc-
curs when WE# falls after CAS# is taken LOW. During
EARLY WRITE cycles, the data-outputs (Q) will remain
High-Z regardless of the state of OE#. During LATE
WRITE or READ-MODIFY-WRITE cycles, OE# must be
taken HIGH to disable the data-outputs prior to ap-
plying input data. If a LATE WRITE or READ-MODIFY-
WRITE is attempted while keeping OE# LOW, no
WRITE will occur, and the data-outputs will drive read
data from the accessed location.
EDO PAGE MODE
EDO PAGE MODE is an accelerated FAST-PAGE-
MODE cycle. The primary advantage of EDO is the
availability of data-out even after CAS# goes back
HIGH. EDO provides for CAS# precharge time (
t
CP) to
occur without the output data going invalid.
PART NUMBERS
EDO Operating Mode
PART NUMBER
CONFIGURATION
SPEED
MT4LDT464AG-5 X
4 Meg x 64
50ns
MT4LDT464AG-6 X
4 Meg x 64
60ns
MT8LDT864AG-5 X
8 Meg x 64
50ns
MT8LDT864AG-6 X
8 Meg x 64
60ns
FPM Operating Mode
PART NUMBER
CONFIGURATION
SPEED
MT4LDT464AG-5
4 Meg x 64
50ns
MT4LDT464AG-6
4 Meg x 64
60ns
MT8LDT864AG-5
8 Meg x 64
50ns
MT8LDT864AG-6
8 Meg x 64
60ns
This elimination of CAS# output control provides for
pipelined READs.
FAST-PAGE-MODE modules have traditionally
turned the output buffers off (High-Z) with the rising
edge of CAS#. EDO-PAGE-MODE DRAMs operate like
FAST-PAGE-MODE DRAMs, except data will remain
valid or become valid after CAS# goes HIGH during
READs, provided RAS# and OE# are held LOW. If OE#
is pulsed while RAS# and CAS# are LOW, data will
toggle from valid data to High-Z and back to the same
valid data. If OE# is toggled or pulsed after CAS# goes
HIGH while RAS# remains LOW, data will transition
to and remain High-Z.
During an application, if the DQ outputs are wire
OR'd, OE# must be used to disable idle banks of DRAMs.
Alternatively, pulsing WE# to the idle banks during
CAS# HIGH time will also tristate the outputs. Inde-
pendent of OE# control, the outputs will disable after
t
OFF, which is referenced from the rising edge of RAS#
or CAS#, whichever occurs last. (Refer to the 4 Meg x 16
[MT4LC4M16R6] DRAM data sheet for additional
information on EDO functionality.)
REFRESH
Returning RAS# and CAS# HIGH terminates a
memory cycle and decreases chip current to a reduced
standby level. Also, the chip is preconditioned for the
next cycle during the RAS# HIGH time. Correct memory
cell data is preserved by maintaining power and ex-
ecuting any RAS# cycle (READ, WRITE) or RAS# RE-
FRESH cycle (RAS#-ONLY, CBR or HIDDEN) so that all
combinations of RAS# addresses (A0-A11) are executed
at least every
t
REF, regardless of sequence. The CBR
REFRESH cycle will invoke the internal refresh counter
for automatic RAS# addressing.
SERIAL PRESENCE-DETECT OPERATION
This module family incorporates serial presence-
detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various DRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations be-
tween the master (system logic) and the slave EEPROM
device (DIMM) occur via a standard IIC bus using the
DIMM's SCL (clock) and SDA (data) signals, together
with SA(2:0), which provide eight unique DIMM/
EEPROM addresses.
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
3
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT4LDT464A (X) (32MB)
DQ16-DQ31
16
DQ0-DQ15
DQ32-DQ47
DQ48-DQ63
A0-A11
WE0#
CAS0#
RAS0#
12
12
12
DQ0-DQ15
U1
A0-A11
WE#
OE#
RAS#
UCAS#
LCAS#
16
16
16
OE0#
12
WE#
OE#
RAS#
UCAS#
LCAS#
DQ0-DQ15
U2
A0-A11
11
V
DD
V
SS
U1-U4
U1-U4
12
U1-U4 = MT4LC4M16R6 EDO PAGE MODE
U1-U4 = MT4LC4M16F5 FAST PAGE MODE
SPD
SCL
SDA
SA0
SA1
SA2
A0
A1
A2
CAS1#
CAS2#
CAS3#
WE#
OE#
RAS#
UCAS#
LCAS#
DQ0-DQ15
U4
A0-A11
CAS6#
CAS7#
WE0#
CAS4#
RAS0#
DQ0-DQ15
U3
A0-A11
WE#
OE#
RAS#
UCAS#
LCAS#
OE0#
CAS5#
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
4
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT8LDT864A (X) (64MB)
WE2#
CAS4#
RAS2#
OE2#
DQ16-DQ31
16
DQ0-DQ15
DQ32-DQ47
DQ48-DQ63
A0-A11
WE0#
CAS0#
RAS0#
12
12
12
16
16
16
OE0#
12
11
V
DD
V
SS
U1-U8
U1-U8
12
RAS3#
DQ16-DQ31
16
DQ0-DQ15
DQ32-DQ47
DQ48-DQ63
12
11
12
16
16
16
12
11
12
U1-U8 = MT4LC4M16R6 EDO PAGE MODE
U1-U8 = MT4LC4M16F5 FAST PAGE MODE
SPD
SCL
SDA
SA0
SA1
SA2
A0
A1
A2
DQ0-DQ15
U1
A0-A11
WE#
OE#
RAS#
UCAS#
LCAS#
WE#
OE#
RAS#
UCAS#
LCAS#
DQ0-DQ15
U2
A0-A11
CAS2#
CAS3#
CAS1#
WE#
OE#
RAS#
UCAS#
LCAS#
DQ0-DQ15
U4
A0-A11
DQ0-DQ15
U3
A0-A11
WE#
OE#
RAS#
UCAS#
LCAS#
CAS5#
CAS6#
CAS7#
DQ0-DQ15
U5
A0-A11
WE#
OE#
RAS#
UCAS#
LCAS#
WE#
OE#
RAS#
UCAS#
LCAS#
DQ0-DQ15
U6
A0-A11
RAS1#
WE#
OE#
RAS#
UCAS#
LCAS#
DQ0-DQ15
U8
A0-A11
DQ0-DQ15
U7
A0-A11
WE#
OE#
RAS#
UCAS#
LCAS#
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
5
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
30, 45, 114, 129
RAS0#-RAS3#
Input
Row-Address Strobe: RAS# is used to clock-in the
row-address bits. Two RAS# inputs allow for one x64
bank or two x32 banks.
28, 29, 46, 47, 112, 113,
CAS0#-CAS7#
Input
Column-Address Strobe: CAS# is used to clock-in the
130, 131
column-address bits, enable the DRAM output
buffers and strobe the data inputs on WRITE cycles.
27, 48
WE0#, WE2#
Input
Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW,
the access is an EARLY WRITE cycle. If WE# is HIGH
while CAS# is LOW, the access is a READ cycle,
provided OE# is also LOW. If WE# goes LOW after
CAS# goes LOW, then the cycle is a LATE WRITE cycle.
A LATE WRITE cycle is generally used in conjunction
with a READ cycle to form a READ-MODIFY-WRITE
cycle.
31, 44
OE0#, OE2#
Input
Output Enable: OE# is the input/output control for
the DQ pins. These signals may be driven, allowing
LATE WRITE cycles.
33-38, 117-122
A0-A11
Input
Address Inputs: These inputs are multiplexed and
clocked by RAS# and CAS#.
2-5, 7-11, 13-17, 19, 20,
DQ0-DQ63
Input/
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to
55-58, 60, 65-67, 69-72,
Output
the addressed DRAM location. For READ access cycles,
74-77, 86-89, 91-95,
DQ0-DQ63 act as outputs for the addressed DRAM
97-101, 103, 104,
location.
139-142, 144, 149-151,
153-156, 158-161
42, 62, 111, 115,
RFU
Reserved for Future Use: These pins should be left
125-126, 128, 132, 146
unconnected.
6, 18, 26, 40, 41, 49, 59,
V
DD
Supply
Power Supply: +3.3V 0.3V.
73, 84, 90, 102, 110,
124, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
V
SS
Supply
Ground.
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
82
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out
of the presence-detect portion of the module.
83
SCL
Input
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
165-167
SA0-SA2
Input
Presence-Detect Address Inputs. These pins are used
to configure the presence-detect device.
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
6
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 3
Acknowledge Response From Receiver
Figure 1
Data Validity
Figure 2
Definition of Start and Stop
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
SCL
SDA
START
BIT
STOP
BIT
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions
(Figures 1 and 2).
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has
been met.
SPD STOP CONDITION
All communications are terminated by a stop con-
dition, which is a LOW-to-HIGH transition of SDA
when SCL is HIGH. The stop condition is also used to
place the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to
indicate successful data transfers. The transmitting
device, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 3).
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and
its slave address. If both the device and a WRITE
operation have been selected, the SPD device will re-
spond with an acknowledge after the receipt of each
subsequent eight-bit word. In the read mode the SPD
device will transmit eight bits of data, release the SDA
line and monitor the line for an acknowledge. If an
acknowledge is detected and no stop condition is
generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and
await the stop condition to return to standby power
mode.
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
7
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT MATRIX
BYTE
DESCRIPTION
ENTRY (VERSION)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
HEX
0
NUMBER OF BYTES USED BY MICRON
128
1
0
0
0
0
0
0
0
80
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
0
0
0
0
1
0
0
0
08
2
MEMORY TYPE
FAST PAGE MODE
0
0
0
0
0
0
0
1
01
EDO PAGE MODE
0
0
0
0
0
0
1
0
02
3
NUMBER OF ROW ADDRESSES
12
0
0
0
0
1
1
0
0
0C
4
NUMBER OF COLUMN ADDRESSES
10
0
0
0
0
1
0
1
0
0A
5
NUMBER OF BANKS
1 (32MB)
0
0
0
0
0
0
0
1
01
2 (64MB)
0
0
0
0
0
0
1
0
02
6
DATA WIDTH
x64
0
1
0
0
0
0
0
0
40
7
DATA WIDTH (continued)
NONE
0
0
0
0
0
0
0
0
00
8
VOLTAGE INTERFACE
LVTTL
0
0
0
0
0
0
0
1
01
9
RAS# ACCESS TIME (
t
RAC)
50ns (-5)
0
0
1
1
0
0
1
0
32
60ns (-6)
0
0
1
1
1
1
0
0
3C
10
CAS# ACCESS TIME (
t
CAC)
13ns (-5)
0
0
0
0
1
1
0
1
0D
15ns (-6)
0
0
0
0
1
1
1
1
0F
11
MODULE CONFIGURATION TYPE
NONPARITY
0
0
0
0
0
0
0
0
00
12
REFRESH RATES
15.625s/NORMAL
0
0
0
0
0
0
0
0
00
13
DRAM WIDTH (PRIMARY DRAM)
x16
0
0
0
1
0
0
0
0
10
14
ERROR-CHECKING DRAM DATA WIDTH
NONE
0
0
0
0
0
0
0
0
00
15-61
RESERVED
0
0
0
0
0
0
0
0
00
62
SPD REVISION
REV. 0
0
0
0
0
0
0
0
0
00
63
CHECKSUM FOR BYTES 0-62
32MB -5 (EDO)
0
0
1
1
0
0
0
1
31
32MB -6 (EDO)
0
0
1
1
1
1
0
1
3D
32MB -6 (FPM)
0
0
1
1
1
1
0
0
3C
64MB -5 (EDO)
0
0
1
1
0
0
1
0
32
64MB -6 (EDO)
0
0
1
1
1
1
1
0
3E
64MB -6 (FPM)
0
0
1
1
1
1
0
1
3D
64
MANUFACTURER'S JEDEC ID CODE
MICRON
0
0
1
0
1
1
0
0
2C
65-71
MANUFACTURER'S JEDEC CODE (CONT.)
1
1
1
1
1
1
1
1
FF
72
MANUFACTURING LOCATION
0
0
0
0
0
0
0
1
01
0
0
0
0
0
0
1
0
02
0
0
0
0
0
0
1
1
03
0
0
0
0
0
1
0
0
04
73-90
MODULE PART NUMBER (ASCII)
x
x
x
x
x
x
x
x
xx
91
PCB IDENTIFICATION CODE
1
0
0
0
0
0
0
0
1
01
2
0
0
0
0
0
0
1
0
02
3
0
0
0
0
0
0
1
1
03
4
0
0
0
0
0
1
0
0
04
92
IDENTIFICATION CODE (CONT.)
0
0
0
0
0
0
0
0
0
00
93
YEAR OF MANUFACTURE IN BCD
x
x
x
x
x
x
x
x
xx
94
WEEK OF MANUFACTURE IN BCD
x
x
x
x
x
x
x
x
xx
95-98
MODULE SERIAL NUMBER
x
x
x
x
x
x
x
x
xx
99-125 MANUFACTURER-SPECIFIC DATA (RSVD)
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
8
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
Pin Relative to V
SS
........ -1V to +4.6V
Voltage on Inputs or I/O Pins
Relative to V
SS
..................................... -1V to +4.6V
Operating Temperature, T
A
(ambient) .. 0C to +70C
Storage Temperature (plastic) ........... -55C to +125C
Power Dissipation ................................................... 8W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other condi-
tions above those indicated in the operational sections
of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods
may affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2
V
DD
+ 0.3
V
30
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-0.5
0.8
V
30
INPUT LEAKAGE CURRENT:
CAS0#-CAS7#,
I
I
1
-4
4
A
Any input 0V
V
IN
V
DD
+ 0.3V
RAS0#-RAS3#
(All other pins not under test = 0V)
OE0#, OE2#, WE0#, WE2#
I
I
2
-8
8
A
31
A0-A11
I
I
3
-16
16
A
31
OUTPUT LEAKAGE CURRENT:
DQ0-DQ63
I
OZ
-10
10
A
31
DQ is disabled; 0V
V
OUT
V
DD
+ 0.3V
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -2mA)
Output Low Voltage (I
OUT
= 2mA)
V
OL
0.4
V
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
9
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
I
DD
OPERATING CONDITIONS AND MAXIMUM LIMITS
(Notes: 1, 5, 6) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL SIZE
-5
-6
UNITS NOTES
STANDBY CURRENT: TTL
I
DD
1
32MB
4
4
mA
(RAS# = CAS# = V
IH
)
64MB
8
8
mA
STANDBY CURRENT: CMOS
I
DD
2
32MB
2
2
mA
(RAS# = CAS# V
DD
- 0.2V; DQs may be left open;
64MB
4
4
mA
Other inputs: V
IN
V
DD
- 0.2V or V
IN
- 0.2V)
OPERATING CURRENT: Random READ/WRITE
32MB
700
660
mA
Average power supply current
I
DD
3
3, 24
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
64MB
704
664
mA
OPERATING CURRENT: FAST PAGE MODE
32MB
420
380
mA
Average power supply current
I
DD
4
3, 24
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
64MB
424
384
mA
OPERATING CURRENT: EDO PAGE MODE ("X" version only)
32MB
620
500
mA
Average power supply current
I
DD
5
3, 24
(RAS# = V
IL
, CAS#, address cycling:
t
PC =
t
PC [MIN])
64MB
624
504
mA
REFRESH CURRENT: RAS#-ONLY
32MB
700
660
mA
Average power supply current
I
DD
6
3, 24
(RAS# cycling, CAS# = V
IH
:
t
RC =
t
RC [MIN])
64MB
704
664
mA
REFRESH CURRENT: CBR
32MB
700
660
mA
Average power supply current
I
DD
7
3, 4
(RAS#, CAS#, address cycling:
t
RC =
t
RC [MIN])
64MB
704
664
mA
MAX
CAPACITANCE
PARAMETER
SYMBOL 32MB 64MB UNITS NOTES
Input Capacitance: A0-A11
C
I
1
22
42
p F
2
Input Capacitance: CAS0#-CAS7#, RAS0#-RAS3#
C
I
2
10
17
p F
2
Input Capacitance: OE0#, OE2#, WE0#, WE2#
C
I
3
17
32
p F
2
Input/Output Capacitance: DQ0-DQ63
C
I
O
10
17
p F
2
MAX
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
10
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 29) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
-5
-6
PARAMETER
SYMBOL
MIIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
t
AA
25
30
ns
Column-address hold time (referenced to RAS#)
t
AR
40
45
ns
Column-address setup time
t
ASC
0
0
ns
Row-address setup time
t
ASR
0
0
ns
Column address to WE# delay time
t
AWD
48
55
ns
23
Access time from CAS#
t
CAC
13
15
ns
14
Column-address hold time
t
CAH
8
10
ns
CAS# pulse width
t
CAS
13
10,000
15
10,000
ns
CAS# hold time (CBR Refresh)
t
CHR
15
15
ns
4
CAS# to output in Low-Z
t
CLZ
3
3
ns
25
CAS# precharge time
t
CP
8
10
ns
15
Access time from CAS# precharge
t
CPA
30
35
ns
CAS# to RAS# precharge time
t
CRP
5
5
ns
CAS# hold time
t
CSH
50
60
ns
CAS# setup time (CBR Refresh)
t
CSR
5
5
ns
4
CAS# to WE# delay time
t
CWD
36
40
ns
23
WRITE command to CAS# lead time
t
CWL
13
15
ns
Data-in hold time
t
DH
8
10
ns
22
Data-in setup time
t
DS
0
0
ns
22
Output disable
t
OD
3
13
3
15
ns
Output enable
t
OE
13
15
ns
OE# hold time from WE# during
t
OEH
13
15
ns
21
READ-MODIFY-WRITE cycle
Output buffer turn-off delay
t
OFF
3
13
3
15
ns
19, 25, 26
OE# setup prior to RAS# during
t
ORD
0
0
ns
HIDDEN REFRESH cycle
FAST-PAGE-MODE READ or WRITE cycle time
t
PC
30
35
ns
FAST-PAGE-MODE READ-WRITE cycle time
t
PRWC
76
85
ns
Access time from RAS#
t
RAC
50
60
ns
13
RAS# to column-address delay time
t
RAD
13
15
ns
17
Row-address hold time
t
RAH
8
10
ns
RAS# pulse width
t
RAS
50
10,000
60
10,000
ns
RAS# pulse width (FAST PAGE MODE)
t
RASP
50
125,000
60
125,000
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
11
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FAST PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 29) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS - FAST PAGE MODE OPTION
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Random READ or WRITE cycle time
t
RC
90
110
ns
RAS# to CAS# delay time
t
RCD
18
20
ns
16
READ command hold time (referenced to CAS#)
t
RCH
0
0
ns
18
READ command setup time
t
RCS
0
0
ns
Refresh period (4,096 cycles)
t
REF
64
64
ms
RAS# precharge time
t
RP
30
40
ns
RAS# to CAS# precharge time
t
RPC
0
0
ns
READ command hold time (referenced to RAS#)
t
RRH
0
0
ns
18
RAS# hold time
t
RSH
13
15
ns
READ-WRITE cycle time
t
RWC
131
155
ns
RAS# to WE# delay time
t
RWD
73
85
ns
23
WRITE command to RAS# lead time
t
RWL
13
15
ns
Transition time (rise or fall)
t
T
2
50
2
50
ns
WRITE command hold time
t
WCH
8
10
ns
WRITE command hold time (referenced to RAS#)
t
WCR
40
45
ns
WE# command setup time
t
WCS
0
0
ns
23
WRITE command pulse width
t
WP
8
10
ns
WE# hold time (CBR Refresh)
t
WRH
10
10
ns
WE# setup time (CBR Refresh)
t
WRP
10
10
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
12
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 29) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from column address
t
AA
25
30
ns
Column-address setup to CAS#
t
ACH
12
15
ns
precharge during WRITEs
Column-address hold time (referenced to RAS#)
t
AR
38
45
ns
Column-address setup time
t
ASC
0
0
ns
Row-address setup time
t
ASR
0
0
ns
Column address to WE# delay time
t
AWD
42
49
ns
23
Access time from CAS#
t
CAC
13
15
ns
14
Column-address hold time
t
CAH
8
10
ns
CAS# pulse width
t
CAS
8
10,000
10
10,000
ns
CAS# hold time (CBR Refresh)
t
CHR
8
10
ns
4
CAS# to output in Low-Z
t
CLZ
0
0
ns
Data output hold after CAS# LOW
t
COH
3
3
ns
CAS# precharge time
t
CP
8
10
ns
15
Access time from CAS# precharge
t
CPA
28
35
ns
CAS# to RAS# precharge time
t
CRP
5
5
ns
CAS# hold time
t
CSH
38
45
ns
CAS# setup time (CBR Refresh)
t
CSR
5
5
ns
4
CAS# to WE# delay time
t
CWD
28
35
ns
23
WRITE command to CAS# lead time
t
CWL
8
10
ns
Data-in hold time
t
DH
8
10
ns
22
Data-in setup time
t
DS
0
0
ns
22
Output disable
t
OD
0
12
0
15
ns
Output enable
t
OE
12
15
ns
OE# hold time from WE# during
t
OEH
8
10
ns
READ-MODIFY-WRITE cycle
OE# HIGH hold time from CAS# HIGH
t
OEHC
5
10
ns
OE# HIGH pulse width
t
OEP
5
5
ns
OE# LOW to CAS# HIGH setup time
t
OES
4
5
ns
Output buffer turn-off delay
t
OFF
0
12
0
15
ns
19, 27
OE# setup prior to RAS#
t
ORD
0
0
ns
19
during HIDDEN REFRESH cycle
EDO-PAGE-MODE READ or WRITE cycle time
t
PC
20
25
ns
EDO-PAGE-MODE READ-WRITE cycle time
t
PRWC
47
56
ns
Access time from RAS#
t
RAC
50
60
ns
13
RAS# to column-address delay time
t
RAD
9
12
ns
17
Row-address hold time
t
RAH
9
10
ns
RAS# pulse width
t
RAS
50
10,000
60
10,000
ns
RAS# pulse width (EDO PAGE MODE)
t
RASP
50
125,000
60
125,000
ns
Random READ or WRITE cycle time
t
RC
84
104
ns
RAS# to CAS# delay time
t
RCD
11
14
ns
16
READ command hold time (referenced to CAS#)
t
RCH
0
0
ns
18
READ command setup time
t
RCS
0
0
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
13
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
EDO PAGE MODE
AC ELECTRICAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 10, 11, 12, 29) (V
DD
= +3.3V 0.3V)
AC CHARACTERISTICS
-5
-6
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
UNITS
NOTES
Refresh period (4,096 cycles)
t
REF
64
64
ms
RAS# precharge time
t
RP
30
40
ns
RAS# to CAS# precharge time
t
RPC
5
5
ns
READ command hold time (referenced to RAS#)
t
RRH
0
0
ns
18
RAS# hold time
t
RSH
13
15
ns
READ-WRITE cycle time
t
RWC
116
140
ns
RAS# to WE# delay time
t
RWD
67
79
ns
23
WRITE command to RAS# lead time
t
RWL
13
15
ns
Transition time (rise or fall)
t
T
2
50
2
50
ns
WRITE command hold time
t
WCH
8
10
ns
WRITE command hold time (referenced to RAS#)
t
WCR
38
45
ns
WE# command setup time
t
WCS
0
0
ns
Output disable delay from WE# (CAS# HIGH)
t
WHZ
12
15
ns
WRITE command pulse width
t
WP
5
5
ns
WE# pulse width for output disable when CAS# HIGH
t
WPZ
10
10
ns
WE# hold time (CBR Refresh)
t
WRH
8
10
ns
WE# setup time (CBR Refresh)
t
WRP
8
10
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
14
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
SERIAL PRESENCE-DETECT EEPROM OPERATING CONDITIONS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7 V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT:
I
SB
30
A
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
I
DD
2
mA
SCL clock frequency = 100 KHz
SERIAL PRESENCE-DETECT EEPROM AC ELECTRICAL CHARACTERISTICS
(Notes: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.3
3.5
s
Time the bus must be free before a new transition can start
t
BUF
4.7
s
Data-out hold time
t
DH
300
ns
SDA and SCL fall time
t
F
300
ns
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
4
s
Clock HIGH period
t
HIGH
4
s
Noise suppression time constant at SCL, SDA inputs
t
I
100
ns
Clock LOW period
t
LOW
4.7
s
SDA and SCL rise time
t
R
1
s
SCL clock frequency
t
SCL
100
KHz
Data-in setup time
t
SU:DAT
250
ns
Start condition setup time
t
SU:STA
4.7
s
Stop condition setup time
t
SU:STO
4.7
s
WRITE cycle time
t
WR
10
ms
28
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
15
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
NOTES
1. All voltages referenced to V
SS
.
2. This parameter is sampled. V
DD
= +3.3V; f = 1 MHz.
3. I
DD
is dependent on output loading and cycle
rates. Specified values are obtained with minimum
cycle time and the outputs open.
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured.
6. An initial pause of 100s is required after power-
up, followed by eight RAS# REFRESH cycles
(RAS#-ONLY or CBR with WE# HIGH), before
proper device operation is ensured. The eight RAS#
cycle wake-ups should be repeated any time the
t
REF refresh requirement is exceeded.
7. AC characteristics assume
t
T = 2ns.
8. V
IH
(MIN) and V
IL
(MAX) are reference levels for
measuring timing of input signals. Transition times
are measured between V
IH
and V
IL
(or between V
IL
and V
IH
).
9. In addition to meeting the transition rate
specification, all input signals must transit between
V
IH
and V
IL
(or between V
IL
and V
IH
) in a mono-
tonic manner.
10.For EDO Page Mode, if CAS# and RAS# = V
IH
,
data output is High-Z. For Fast Page Mode, if
CAS# = V
IN
, data output is High-Z.
11.If CAS# = V
IL
, data output may contain data from
the last valid READ cycle.
12.Measured with a load equivalent to two TTL gates
and 100pF and V
OL
= 0.8V and V
OH
= 2V.
13.Requires that
t
AA and
t
CAC are not violated.
14.Requires that
t
AA and
t
RAC are not violated.
15.If CAS# is LOW at the falling edge of RAS#, Q will
be maintained from the previous cycle. To initiate
a new cycle and clear the data-out buffer, CAS#
must be pulsed HIGH for
t
CP.
16.The
t
RCD (MAX) limit is no longer specified.
t
RCD
(MAX) was specified as a reference point only. If
t
RCD was greater than the specified
t
RCD (MAX)
limit, then access time was controlled exclusively
by
t
CAC (
t
RAC [MIN] no longer applied). With or
without the
t
RCD (MAX) limit,
t
AA and
t
CAC
must always be met.
17.The
t
RAD (MAX) limit is no longer specified.
t
RAD
(MAX) was specified as a reference point only. If
t
RAD was greater than the specified
t
RAD (MAX)
limit, then access time was controlled exclusively
by
t
AA (
t
RAC and
t
CAC no longer applied). With
or without the
t
RAD (MAX) limit,
t
AA,
t
RAC and
t
CAC must always be met.
18.Either
t
RCH or
t
RRH must be satisfied for a READ
cycle.
19.
t
OFF (MAX) defines the time at which the output
achieves the open circuit condition and is not
referenced to V
OH
or V
OL
.
20.A HIDDEN REFRESH may also be performed after
a WRITE cycle. In this case, WE# = LOW and
OE# = HIGH.
21.The maximum current ratings are based with the
memory operating or being refreshed in the x64
mode. The stated maximums may be reduced by
approximately one-half when used in the x32
mode.
22.These parameters are referenced to CAS# leading
edge in EARLY WRITE cycles and WE# leading
edge in LATE WRITE or READ-MODIFY-WRITE
cycles.
23.
t
WCS,
t
RWD,
t
AWD
and
t
CWD
are
not
restrictive
operating
parameters.
t
WCS
applies
to
EARLY
WRITE
cycles.
If
t
WCS
>
t
WCS
(MIN),
the
cycle
is
an
EARLY
WRITE
cycle
and
the
data
output
will
remain
an
open
circuit
throughout
the
entire
cycle.
t
RWD,
t
AWD
and
t
CWD
define
READ-
MODIFY-WRITE
cycles.
Meeting
these
limits
allows
for
reading
and
disabling
output
data
and
then
applying
input
data.
OE#
held
HIGH
and
WE#
taken
LOW
after
CAS#
goes
LOW
result
in
a
LATE
WRITE
(OE#-controlled)
cycle.
t
WCS,
t
RWD,
t
CWD
and
t
AWD
are
not
applicable
in
a
LATE
WRITE
cycle.
24.Column address changed once each cycle.
25.The 3ns minimum parameter guaranteed by
design.
26.Measured with the specified current load and
100pF.
27.
t
OFF on an EDO module is determined by the
latter of the RAS# and CAS# signals to transition
HIGH.
28.The SPD EEPROM WRITE cycle time (
t
WR) is the
time from a valid stop condition of a write
sequence to the end of the EEPROM internal erase/
program cycle. During the WRITE cycle, the
EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the
EEPROM does not respond to its slave address.
29.If OE# is tied permanently LOW, LATE WRITE or
READ-MODIFY-WRITE operations are not
possible.
30.V
IH
overshoot: V
IH
(MAX) = V
DD
+ 2V for a pulse
width
10ns, and the pulse width cannot be
greater than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
10ns, and the pulse width cannot be greater than
one third of the cycle rate.
31. 32MB module values will be half of those shown.
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
16
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
t
OE (EDO)
12
15
ns
t
OFF (FPM)
3
13
3
15
ns
t
OFF (EDO)
0
12
0
15
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
OD (FPM)
3
13
3
15
ns
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
READ CYCLE
tRRH
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tOFF
tRCH
ROW
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tRSH
tCSH
tRP
tRC
tRAS
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
tOD
tOE
OE#
V
V
IH
IL
COLUMN
CAS#
WE#
NOTE 1
tACH
DON'T CARE
UNDEFINED
NOTE: 1.
t
OFF is referenced from rising edge of RAS# or CAS#, whichever occurs last.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
17
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
EARLY WRITE CYCLE
DON'T CARE
UNDEFINED
V
V
IH
IL
VALID DATA
ROW
COLUMN
ROW
tDS
tWP
tWCH
tWCS
tWCR
tRWL
tCWL
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCAS
tRSH
tCSH
tRCD
tCRP
tRAS
tRC
tRP
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
tDH
WE#
CAS#
tACH
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR (FPM)
40
45
ns
t
WCR (EDO)
38
45
ns
t
WCS
0
0
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
18
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ CYCLE
VALID
DATA
VALID
DATA
VALID
DATA
COLUMN
COLUMN
COLUMN
ROW
ROW
DON'T CARE
UNDEFINED
tOD
tCAH
tASC
tCP
tRSH
tCP
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tCAC
tCPA
tAA
tCAC
tRAC
tAA
tCLZ
tOE
tOD
tOE
tOD
OPEN
OPEN
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
RAS#
OE#
tCAS
tCAS
CAS#
WE#
tCOH
tOEP
tOEHC
tOES
tOES
tACH
tACH
tACH
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OEHC
5
10
ns
t
OEP
5
5
ns
t
OES
4
5
ns
t
OFF
0
12
0
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
COH
3
3
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
OD
0
12
0
15
ns
t
OE
12
15
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
19
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FAST PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
40
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
13
10,000
15
10,000
ns
t
CLZ
3
3
ns
t
CP
8
10
ns
t
CPA
30
35
ns
t
CRP
5
5
ns
t
CSH
50
60
ns
t
OD
3
13
3
15
ns
VALID
DATA
VALID
DATA
VALID
DATA
COLUMN
COLUMN
COLUMN
ROW
ROW
tRCS
tCAH
tASC
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
tRP
tCAH
tASC
tCAH
tASC
tAR
tRAH
tRAD
tASR
tRCS
tRCH
tRCH
tRCS
tRRH
tRCH
tOFF
tCAC
tCPA
tAA
tCLZ
tOFF
tCAC
tCPA
tAA
tCLZ
tOFF
tCAC
tRAC
tAA
tCLZ
OPEN
OPEN
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
RAS#
DON'T CARE
UNDEFINED
FAST-PAGE-MODE READ CYCLE
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
13
15
ns
t
OFF
3
13
3
15
ns
t
PC
30
35
ns
t
RAC
50
60
ns
t
RAD
13
15
ns
t
RAH
8
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
18
20
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RRH
0
0
ns
t
RSH
13
15
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
20
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
tDS
tDH
tDS
tDH
tDS
tDH
tWCR
VALID DATA
VALID DATA
VALID DATA
tRWL
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tWP
tCWL
tWCH
tWCS
tCAH
tASC
tCAH
tASC
tCAH
tASC
tRAH
tASR
tRAD
tACH
tACH
tACH
tAR
COLUMN
COLUMN
COLUMN
ROW
ROW
tCP
tCAS
tRSH
tCP
tCAS
tCP
tCAS
tRCD
tCRP
tPC
tCSH
tRASP
t RP
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
V
V
IH
IL
DQ
V
V
IOH
IOL
RAS#
DON'T CARE
UNDEFINED
t
PC (EDO)
20
25
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCR (FPM)
40
45
ns
t
WCR (EDO)
38
45
ns
t
WCS
0
0
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
PC (FPM)
30
35
ns
FAST/EDO-PAGE-MODE EARLY WRITE CYCLE
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
21
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
t
OE (EDO)
12
15
ns
t
OEH (FPM)
13
15
ns
t
OEH (EDO)
8
10
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWC (FPM)
131
155
ns
t
RWC (EDO)
116
140
ns
t
RWD (FPM)
73
85
ns
t
RWD (EDO)
67
79
ns
t
RWL
13
15
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH (EDO)
12
15
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD (FPM)
48
55
ns
t
AWD (EDO)
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWD (FPM)
36
40
ns
t
CWD (EDO)
28
35
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
OD (FPM)
3
13
3
15
ns
READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
VALID D
OUT
VALID D
IN
ROW
COLUMN
ROW
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OPEN
OPEN
tOE
tOD
tCAC
tRAC
tAA
t CLZ
tDS
tDH
tAWD
tWP
tRWL
tCWL
tCWD
tRWD
tRCS
tASC
tCAH
tAR
tASR
tRAD
tCRP
tRCD
tCAS
tRSH
tCSH
tRAS
tRWC
tRP
tRAH
OE#
tOEH
WE#
tACH
CAS#
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
22
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
t
OE (EDO)
12
15
ns
t
OEH (FPM)
13
15
ns
t
OEH (EDO)
8
10
ns
t
PC (FPM)
30
35
ns
t
PC (EDO)
20
25
ns
t
PRWC (FPM)
76
85
ns
t
PRWC (EDO)
47
56
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWD (FPM)
73
85
ns
t
RWD (EDO)
67
79
ns
t
RWL
13
15
ns
t
WP (FPM)
8
10
ns
t
WP (EDO)
5
5
ns
FAST/EDO-PAGE-MODE READ-WRITE CYCLE
(LATE WRITE and READ-MODIFY-WRITE cycles)
DON'T CARE
UNDEFINED
tOE
tOE
tOE
OPEN
D OUT
VALID
DIN
VALID
D OUT
VALID
D IN
VALID
D OUT
VALID
D IN
VALID
OPEN
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCPA
tCLZ
tCAC
tDH
tDS
tAA
tCLZ
tCAC
tRAC
tWP
tCWL
tRWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tWP
tCWL
tCWD
tAWD
tRCS
tRWD
tASR
tRAH
tASC
tRAD
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tCAS
tRSH
tCP
tRP
tRASP
tCAS
tCP
tCAS
tRCD
tCSH
t PC
tCRP
ROW
COLUMN
COLUMN
COLUMN
ROW
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
V
V
IH
IL
DQ
V
V
IOH
IOL
V
V
IH
IL
RAS#
OE#
WE#
tPRWC
tOEH
tOD
tOD
tOD
NOTE 1
NOTE: 1.
t
PC is for LATE WRITE cycles only.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
AWD (FPM)
48
55
ns
t
AWD (EDO)
42
49
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS (FPM)
13
10,000
15
10,000
ns
t
CAS (EDO)
8
10,000
10
10,000
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CP
8
10
ns
t
CPA (FPM)
30
35
ns
t
CPA (EDO)
28
35
ns
t
CRP
5
5
ns
t
CSH (FPM)
50
60
ns
t
CSH (EDO)
38
45
ns
t
CWD (FPM)
36
40
ns
t
CWD (EDO)
28
35
ns
t
CWL (FPM)
13
15
ns
t
CWL (EDO)
8
10
ns
t
DH
8
10
ns
t
DS
0
0
ns
t
OD (FPM)
3
13
3
15
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
23
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FAST PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
40
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
13
10,000
15
10,000
ns
t
CLZ
3
3
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
50
60
ns
t
CWL
13
15
ns
t
DH
8
10
ns
t
DS
0
0
ns
NOTE: 1. Do not drive data prior to tristate.
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OFF
3
13
3
15
ns
t
PC
30
35
ns
t
RAC
50
60
ns
t
RAD
13
15
ns
t
RAH
8
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
18
20
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
RWL
13
15
ns
t
WCH
8
10
ns
t
WCS
0
0
ns
t
WP
8
10
ns
ROW
VALID
DATA
VALID DATA
OPEN
tCRP
tRCD
tCAS
tRSH
tRASP
tRP
tPC
tASC
tCAH
tAR
tASR
tRAD
tRAH
tWCS
tWP
tRWL
tRCS
tDH
tDS
tCAC
tOFF
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
DQ
V
V
OH
OL
WE#
V
V
IH
IL
tCSH
COLUMN
tCP
tCP
tASC
tCAH
tCWL
tWCH
tCLZ
tAA
RAC
DON'T CARE
UNDEFINED
t
NOTE 1
ROW
COLUMN
tCAS
FAST-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
24
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
EDO-PAGE-MODE READ EARLY WRITE CYCLE
(Pseudo READ-MODIFY-WRITE)
V
V
IH
IL
V
V
IH
IL
RAS#
V
V
IH
IL
ADDR
V
V
IH
IL
WE#
tRASP
tRP
ROW
COLUMN (A)
COLUMN (N)
ROW
V
V
IH
IL
OE#
V
V
IOH
IOL
tCRP
tCSH
tCAS
tRCD
tASR
tRAH
tRAD
tASC
tAR
tCAH
tASC
tCAH
tASC
tCAH
tCP
tRSH
VALID DATA
IN
tRCS
tRCH
tWCS
tOE
VALID
DATA (B)
VALID DATA (A)
tWHZ
tCAC
tCPA
tAA
tCAC
tAA
OPEN
DQ
tPC
RAC
t
tCOH
tWCH
tDS
tDH
tPC
COLUMN (B)
tACH
CAS#
tCAS
tCAS
tCP
tCP
DON'T CARE
UNDEFINED
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OE
12
15
ns
t
PC
20
25
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RASP
50
125,000
60
125,000
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
RP
30
40
ns
t
RSH
13
15
ns
t
WCH
8
10
ns
t
WCS
0
0
ns
t
WHZ
12
15
ns
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
ACH
12
15
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
COH
3
3
ns
t
CP
8
10
ns
t
CPA
28
35
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
t
DH
8
10
ns
t
DS
0
0
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
25
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
EDO READ CYCLE
(with WE#-controlled disable)
tCLZ
tCAC
tRAC
tAA
VALID DATA
OPEN
tRCH
tRCS
tASC
tRAH
tRAD
tAR
tCAH
tRCD
tCAS
tCSH
tCRP
tASR
ROW
OPEN
RAS#
V
V
IH
IL
V
V
IH
IL
ADDR
V
V
IH
IL
DQ
V
V
OH
OL
V
V
IH
IL
tOD
tOE
OE#
V
V
IH
IL
COLUMN
WE#
tWHZ
tWPZ
tCP
tASC
tRCS
COLUMN
tCLZ
DON'T CARE
UNDEFINED
CAS#
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
OD
0
12
0
15
ns
t
OE
12
15
ns
t
RAC
50
60
ns
t
RAD
9
12
ns
t
RAH
9
10
ns
t
RCD
11
14
ns
t
RCH
0
0
ns
t
RCS
0
0
ns
t
WHZ
12
15
ns
t
WPZ
10
10
ns
EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CAS
8
10,000
10
10,000
ns
t
CLZ
0
0
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSH
38
45
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
26
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
ASR
0
0
ns
t
CHR (FPM)
15
15
ns
t
CHR (EDO)
8
10
ns
t
CP
8
10
ns
t
CRP
5
5
ns
t
CSR
5
5
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
RAS#-ONLY REFRESH CYCLE
ROW
V
V
IH
IL
CAS#
V
V
IH
IL
ADDR
V
V
IH
IL
RAS#
tRC
tRAS
tRP
tCRP
tASR
tRAH
ROW
OPEN
DQ
V
V
OH
OL
tRPC
WE#
V
V
IH
IL
CBR REFRESH CYCLE
(Addresses, OE# = DON'T CARE)
tRP
V
V
IH
IL
RAS#
tRAS
OPEN
tCHR
tCSR
V
V
IH
IL
V
V
OH
OL
CAS#
DQ
tRP
tRAS
tRPC
tCSR
tRPC
tCHR
tCP
V
V
IH
IL
tWRP
tWRH
tWRP
tWRH
WE#
DON'T CARE
UNDEFINED
NOTE 1
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RP
30
40
ns
t
RPC (FPM)
0
0
ns
t
RPC (EDO)
5
5
ns
t
WRH (FPM)
10
10
ns
t
WRH (EDO)
8
10
ns
t
WRP (FPM)
10
10
ns
t
WRP (EDO)
8
10
ns
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
27
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
t
OFF (FPM)
3
13
3
15
ns
t
OFF (EDO)
0
12
0
15
ns
t
ORD
0
0
ns
t
RAC
50
60
ns
t
RAD (FPM)
13
15
ns
t
RAD (EDO)
9
12
ns
t
RAH (FPM)
8
10
ns
t
RAH (EDO)
9
10
ns
t
RAS
50
10,000
60
10,000
ns
t
RC (FPM)
90
110
ns
t
RC (EDO)
84
104
ns
t
RCD (FPM)
18
20
ns
t
RCD (EDO)
11
14
ns
t
RP
30
40
ns
t
RSH
13
15
ns
FAST PAGE MODE AND EDO PAGE MODE
TIMING PARAMETERS
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
t
AA
25
30
ns
t
AR (FPM)
40
45
ns
t
AR (EDO)
38
45
ns
t
ASC
0
0
ns
t
ASR
0
0
ns
t
CAC
13
15
ns
t
CAH
8
10
ns
t
CHR (FPM)
15
15
ns
t
CHR (EDO)
8
10
ns
t
CLZ (FPM)
3
3
ns
t
CLZ (EDO)
0
0
ns
t
CRP
5
5
ns
t
OD (FPM)
3
13
3
15
ns
t
OD (EDO)
0
12
0
15
ns
t
OE (FPM)
13
15
ns
t
OE (EDO)
12
15
ns
HIDDEN REFRESH CYCLE
20
(WE# = HIGH; OE# = LOW)
DON'T CARE
UNDEFINED
tCLZ
tOFF
OPEN
VALID DATA
OPEN
COLUMN
ROW
tCAC
tRAC
tAA
tCAH
tASC
tRAH
tASR
tRAD
tAR
tCRP
tRCD
tRSH
tRAS
tRC
tRP
tCHR
tRAS
DQ
V
V
IOH
IOL
V
V
IH
IL
ADDR
V
V
IH
IL
CAS#
V
V
IH
IL
RAS#
-5
-6
SYMBOL
MIN
MAX
MIN
MAX
UNITS
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
28
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
SPD EEPROM
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
SERIAL PRESENCE-DETECT EEPROM
TIMING PARAMETERS
SYMBOL
MIN
MAX
UNITS
t
AA
0.3
3.5
s
t
BUF
4.7
s
t
DH
300
ns
t
F
300
ns
t
HD:DAT
0
s
t
HD:STA
4
s
t
HIGH
4
s
t
LOW
4.7
s
t
R
1
s
t
SU:DAT
250
ns
t
SU:STA
4.7
s
t
SU:STO
4.7
s
SYMBOL
MIN
MAX
UNITS
4, 8 Meg x 64 Nonbuffered DRAM DIMMs
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DM88.p65 Rev. 2/99
1999, Micron Technology, Inc.
29
4, 8 MEG x 64
NONBUFFERED DRAM DIMMs
168-PIN DIMM
(64MB)
168-PIN DIMM
(32MB)
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP
.039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.661 (42.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
1.060 (26.92)
1.040 (26.42)
.054 (1.37)
.046 (1.17)
.125 (3.18)
MAX
PIN 1 (PIN 85 ON BACKSIDE)
.700 (17.78)
TYP
.118 (3.00)
(2X)
.118 (3.00) TYP
4.550 (115.57)
.050 (1.27)
TYP
.118 (3.00)
TYP
.039 (1.00)
TYP
.079 (2.00) R
(2X)
.039 (1.00)R (2X)
FRONT VIEW
.128 (3.25)
.118 (3.00)
PIN 84 (PIN 168 ON BACKSIDE)
(2X)
.250 (6.35) TYP
1.661 (42.18)
2.625 (66.68)
5.256 (133.50)
5.244 (133.20)
1.060 (26.92)
1.040 (26.42)
.054 (1.37)
.046 (1.17)
.157 (4.00)
MAX
NOTE: All dimensions in inches (millimeters) MAX or typical where noted.
MIN
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micronsemi.com, Internet: http://www.micronsemi.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark of Micron Technology, Inc.
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