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Электронный компонент: MT8LSDF3264LWG-13E__

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1
32 Meg x 64 SDRAM MICRODIMM
2001, Micron Technology, Inc.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON'S PRODUCTION DATA SHEET SPECIFICATIONS.
TIMING PARAMETERS
PC100
PC133
Module Markings
CL -
t
RCD -
t
RP
CL -
t
RCD -
t
RP
-13E
2 - 2 - 2
2 - 2 - 2
-133
2 - 2 - 2
3 - 3 - 3
-10E
2 - 2 - 2
N/A
NOTE: CL = CAS (READ) Latency
MICRODIMM
SDRAM MODULE
MT8LSDF3264(L)W
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/datasheets
PIN ASSIGNMENT
144-Pin MicroDIMM
(MO-214)
FEATURES
JEDEC-standard, PC100, PC133, 144-pin
MicroDIMM
Utilizes 100 MHz and 133 MHz SDRAM components
256MB (32 Meg x 64)
Single +3.3V 0.3V power supply
Fully synchronous; all signals registered on
positive edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge and Auto Refresh Modes
Self Refresh Mode: Standard and Low Power
64ms, 8,192-cycle refresh.
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD)
OPTIONS
MARKING
Package
144-pin MicroDIMM (gold)
G
Frequency/CAS Latency
133 MHz/CL = 2
-13E
133 MHz/CL = 3
-133
100 MHz/CL = 2
-10E
Self Refresh Current
Standard
None
Low power
L*
PIN
FRONT
PIN
BACK
PIN
FRONT
PIN
BACK
1
V
SS
2
V
SS
73
NC
74
CK1
3
DQ0
4
DQ32
75
V
SS
76
V
SS
5
DQ1
6
DQ33
77
NC
78
NC
7
DQ2
8
DQ34
79
NC
80
NC
9
DQ3
10
DQ35
81
V
DD
82
V
DD
11
V
DD
12
V
DD
83
DQ16
84
DQ48
13
DQ4
14
DQ36
85
DQ17
86
DQ49
15
DQ5
16
DQ37
87
DQ18
88
DQ50
17
DQ6
18
DQ38
89
DQ19
90
DQ51
19
DQ7
20
DQ39
91
V
SS
92
V
SS
21
V
SS
22
V
SS
93
DQ20
94
DQ52
23
DQMB0
24
DQMB4
95
DQ21
96
DQ53
25
DQMB1
26
DQMB5
97
DQ22
98
DQ54
27
V
DD
28
V
DD
99
DQ23
100
DQ55
29
A0
30
A3
101
V
DD
102
V
DD
31
A1
32
A4
103
A6
104
A7
33
A2
34
A5
105
A8
106
BA0
35
V
SS
36
V
SS
107
V
SS
108
V
SS
37
DQ8
38
DQ40
109
A9
110
BA1
39
DQ9
40
DQ41
111
A10
112
A11
41
DQ10
42
DQ42
113
V
DD
114
V
DD
43
DQ11
44
DQ43
115
DQMB2
116
DQMB6
45
V
DD
46
V
DD
117
DQMB3
118
DQMB7
47
DQ12
48
DQ44
119
V
SS
120
V
SS
49
DQ13
50
DQ45
121
DQ24
122
DQ56
51
DQ14
52
DQ46
123
DQ25
124
DQ57
53
DQ15
54
DQ47
125
DQ26
126
DQ58
55
V
SS
56
V
SS
127
DQ27
128
DQ59
57
NC
58
NC
129
V
DD
130
V
DD
59
NC
60
NC
131
DQ28
132
DQ60
61
CK0
62
CKE0
133
DQ29
134
DQ61
63
V
DD
64
V
DD
135
DQ30
136
DQ62
65
RAS#
66
CAS#
137
DQ31
138
DQ63
67
WE#
68
NC
139
V
SS
140
V
SS
69
S0#
70
A12
141
SDA
142
SCL
71
NC
72
NC
143
V
DD
144
V
DD
*Consult Micron for availability
2
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
ADDRESS TABLE
256MB Module
Refresh Count
8K
Device Banks
4 (BA0, BA1)
Base Device Configuration
32 Meg x 8
Row Addressing
8K (A0A12)
Column Addressing
1K (A0A9)
Module Banks
1 (S0#)
PART NUMBERS
PART NUMBER
CONFIGURATION
VERSION
MT8LSDF3264(L)WG-13E__
32 Meg x 64
133 MHz, CL = 2
MT8LSDF3264(L)WG-133__
32 Meg x 64
133 MHz, CL = 3
MT8LSDF3264(L)WG-10E__
32 Meg x 64
100 MHz, CL = 2
NOTE: All part numbers end with a five-place code, of which
last two are not shown designating component and
PCB revisions. Consult factory for current revision
codes. Example: MT8LSDF3264(L)WG-133B1.
GENERAL DESCRIPTION
The Micron
MT8LSDF3264(L)W is a high-speed
CMOS, dynamic random-access, 256MB memory mod-
ule, organized in a x64 configuration. This module uses
SDRAMs that are internally configured as quad-bank
DRAMs with a synchronous interface (all signals are
registered on the positive edge of the clock signal CK0).
Read and write accesses to the SDRAM module are
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then followed
by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used
to select the device bank and row to be accessed (BA0,
BA1 select the device bank, A0-A12 select the device
row). The address bits registered coincident with the
READ or WRITE command are used to select the start-
ing column location for the burst access.
This module provides for programmable READ or
WRITE burst lengths of 1, 2, 4, or 8 locations, or the full
page, with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed de-
vice row precharge that is initiated at the end of the
burst sequence. This module uses an internal pipelined
architecture to achieve high-speed operation. This
architecture is compatible with the 2n rule of prefetch
architectures, but it also allows the device column ad-
dress to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one de-
vice bank while accessing the alternate device bank
will hide the PRECHARGE cycles and provide seam-
less, high-speed, random-access operation.
This module is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs, outputs, and clocks are LVTTL-compatible.
SDRAM modules offer substantial advances in
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic column-address generation, the ability to inter-
leave between device banks in order to hide precharge
time, and the capability to randomly change device
column addresses on each clock cycle during a burst
access. For more information regarding SDRAM opera-
tion, refer to the 256Mb data sheet.
SERIAL PRESENCE-DETECT OPERATION
This module incorporates serial presence-detect
(SPD). The SPD function is implemented using a 2,048-
bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes can be programmed by
Micron to identify the module type and various SDRAM
organizations and timing parameters. The remaining
128 bytes of storage are available for use by the cus-
tomer. System READ/WRITE operations between the
master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM's
SCL (clock) and SDA (data) signals.
3
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
DQM CS#
U5
NOTE:
All resistor values are 10 ohms.
U1-U8 = MT48LC32M8A2FB SDRAMs
A0
SPD
U9
SCL
SDA
A1
A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DQMB7
DQM CS#
U6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQMB6
DQM CS#
U7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQMB5
DQM CS#
U8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB4
DQM CS#
U4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMB3
DQM CS#
U3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
DQM CS#
U2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB1
DQM CS#
U1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S0#
RAS#
CAS#
CKE0
WE#
RAS#: SDRAMs U1-U8
CAS#: SDRAMs U1-U8
CKE: SDRAMs U1-U8
WE#: SDRAMs U1-U8
A0-A12: SDRAMs U1-U8
BA0-1: SDRAMs U1-U8
A0-A12
BA0-1
V
DD
V
SS
SDRAMs U1-U8
SDRAMs U1-U8
CK0
U1, U7
U2, U8
CK1
U3, U5
U4, U6
WP
4
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
PIN DESCRIPTIONS
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
65, 66, 67
RAS#, CAS#, Input
Command Inputs RAS#, CAS#, and WE# (along with S0#)
WE#
define the command being entered.
61, 74
CK0, CK1
Input
Clock: CK0 and CK1 are driven by the system clock. All SDRAM
input signals are sampled on the positive edge of CK. CK also
increments the internal burst counter and controls the output
registers.
62
CKE0
Input
Clock Enable: CKE0 activates (HIGH) and deactivates (LOW) the
CK0-CK1 signals. Deactivating the clock provides POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND operation (burst access in progress). CKE0 is synchronous
except after the device enters power-down and self refresh modes,
where CKE0 becomes asynchronous until after exiting the same
mode. The input buffers, including CK0-CK1, are disabled during
power-down and self refresh modes, providing low standby power.
69
S0#
Input
Chip Select: S0# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S0#
is registered HIGH. S0# is considered part of the command code.
23, 24, 25, 26, 115,
DQMB0
Input
Input Mask: DQMB is an input mask signal for write accesses. Input
116, 117, 118
DQMB7
data is masked when DQMB is sampled HIGH during a WRITE cycle.
The output buffers are placed in a High-Z state (after a two-clock
latency) when DQMB is sampled HIGH during a READ cycle.
106,110
BA0, BA1
Input
Bank Address: BA0 and BA1 define to which device device bank
the ACTIVE, READ, WRITE, or PRECHARGE command is being
applied. BA0 is also used to program the twelfth bit of the Mode
Register.
29, 30, 31, 32, 33, 34,
A0-A12
Input
Address Inputs: A0-A12 are sampled during the ACTIVE
70, 103, 104, 105,
command (row-address A0-A12) and READ/WRITE command
109, 111, 112
(column-address A0-A9, with A10 defining auto precharge) to
select one location out of the memory array in the respective
device bank. A10 is sampled during a PRECHARGE command to
determine if all device banks are to be precharged (A10 HIGH). The
address inputs also provide the op-code during a LOAD MODE
REGISTER command.
142
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
141
SDA
Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to
Output transfer addresses and data into and data out of the presence-
detect portion of the module.
NOTE: Pin numbers may not correlate with symbols. Refer to pin assigment tables for pin number and symbol information.
5
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
PIN DESCRIPTIONS (continued)
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
3, 4, 5, 6, 7, 8, 9, 10,
DQ0DQ63
Input/ Data I/Os: Data bus.
13, 14, 15, 16, 17, 18,
Output
19, 20, 37, 38, 39, 40
41, 42, 43, 44, 47, 48,
49,
50, 51, 52, 53, 54,
83, 84, 85, 86, 87, 88,
89, 90, 93, 94, 95, 96,
97, 98, 99, 100, 121,
122, 123, 124, 125, 126,
127, 128, 131, 132, 133,
134, 135, 136, 137, 138
11, 12, 27, 28, 45, 46,
V
DD
Supply Power Supply: +3.3V 0.3V.
63, 64, 81, 82, 101, 102,
113, 114, 129, 143, 130,
144
1, 2, 21, 22, 35, 36, 55,
V
SS
Supply Ground.
56, 75, 76, 91, 92, 107,
108, 119, 120, 139,
140
57, 58, 59, 60, 68, 71,
NC
_
No Connect: These pins are not connected for this module.
72, 73, 77, 78, 79, 80
NOTE: Pin numbers may not correlate with symbols. Refer to pin assigment tables for pin number and symbol information.
6
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
SDRAM COMPONENT DESCRIPTION
In general, the 256Mb SDRAM memory device used
for this module is a quad-bank DRAM that operates at
3.3V and includes a synchronous interface (all signals
are registered on the positive edge of the clock signal,
CLK). The four banks of a x8, 256Mb device are each
configured as 8,192 bit-rows by 1,024 bit columns, by 8
input/output bits.
MODULE FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst
oriented; accesses start at a selected location and con-
tinue for a programmed number of locations in a pro-
grammed sequence. Accesses begin with the registra-
tion of an ACTIVE command, which is then followed by
a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used to
select the device bank and row to be accessed BA0 and
BA1 select the device bank, A0-A12 select the device
row. The address bits A0-A9, registered coincident with
the READ or WRITE command, are used to select the
starting device column location for the burst access.
Prior to normal operation, the SDRAM must be ini-
tialized. The following sections provide detailed infor-
mation covering device initialization, register defini-
tion, command descriptions and device operation.
Initialization
SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to V
DD
and V
DD
Q (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100s delay
prior to issuing any command other than a COMMAND
INHIBIT or NOP. Starting at some point during this
100s period and continuing at least through the end
of this period, COMMAND INHIBIT or NOP commands
should be applied.
Once the 100s delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied.
All device banks must then be precharged, thereby plac-
ing the device in the all device banks idle state.
Once in the idle state, two AUTO REFRESH cycles
must be performed. After the AUTO REFRESH cycles
are complete, the SDRAM is ready for mode register
programming. Because the mode register will power
up in an unknown state, it should be loaded prior to
applying any operational command.
Mode Register Definition
MODE REGISTER
The mode register is used to define the specific mode
of operation of the SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS
latency, an operating mode and a write burst mode, as
shown in Mode Register Definition Diagram. The mode
register is programmed via the LOAD MODE REGIS-
TER command and will retain the stored information
until it is programmed again or the device loses power.
Mode register bits M0-M2 specify the burst length,
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write burst
mode, and M10 and M11 are reserved for future use.
Address A12 (M12) is undefined but should be driven
LOW during loading of the mode register.
The mode register must be loaded when all device
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
Burst Length
Read and write accesses to the SDRAM are burst
oriented, with the burst length being programmable,
as shown in Mode Register Definition Diagram. The
burst length determines the maximum number of col-
umn locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively se-
lected. All accesses for that burst take place within this
block, meaning that the burst will wrap within the block
if a boundary is reached, as shown in the Burst Defini-
tion Table. The block is uniquely selected by A1-A9
when the burst length is set to two; A2-A9 when the
burst length is set to four; and by A3-A9 when the burst
length is set to eight. The remaining (least significant)
address bit(s) is (are) used to select the starting loca-
tion within the block. Full-page bursts wrap within the
page if the boundary is reached, as shown in the Burst
Definition Table.
7
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
NOTE: 1. For full-page accesses: y = 1,024.
2. For a burst length of two, A1-A9 select the block-
of-two burst; A0 selects the starting column
within the block.
3. For a burst length of four, A2-A9 select the block-
of-four burst; A0-A1 select the starting column
within the block.
4. For a burst length of eight, A3-A9 select the block-
of-eight burst; A0-A2 select the starting column
within the block.
5. For a full-page burst, the full row is selected and
A0-A9 select the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9 select the unique
column to be accessed, and mode register bit M3
is ignored.
Burst Definition
Table
Burst
Starting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential
Type = Interleaved
A0
2
0
0-1
0-1
1
1-0
1-0
A1 A0
0
0
0-1-2-3
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
A2 A1 A0
0
0
0
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7
0
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A9
Cn, Cn + 1, Cn + 2
Page
Cn + 3, Cn + 4...
Not Supported
(y)
(location 0-y)
...Cn - 1,
Cn...
Mode Register Definition
Diagram
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is deter-
mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.
M3 = 0
1
2
4
8
Reserved
Reserved
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
6
5
4
3
8
2
1
0
M1
0
0
1
1
0
0
1
1
M2
0
0
0
0
1
1
1
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
0
1
1
0
0
1
1
M6
0
0
0
0
1
1
1
1
M6-M0
M8
M7
Op Mode
A10
A11
10
11
Reserved*
WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M12, M11, M10 = 0, 0, 0
to ensure compatibility
with future devices.
A12
12
8
32/64 Meg x 64 SDRAM SODIMM
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256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
CAS
SPEED
LATENCY = 2
LATENCY = 3
-13E
133
143
-133
100
133
-10E
100
N/A
Figure 1
CAS Latency
CLK
DQ
T2
T1
T3
T0
CAS Latency = 3
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
T4
NOP
DON'T CARE
UNDEFINED
CLK
DQ
T2
T1
T3
T0
CAS Latency = 2
LZ
D
OUT
tOH
t
COMMAND
NOP
READ
tAC
NOP
Table 1
CAS Latency
CAS Latency
The CAS latency is the delay, in clock cycles, be-
tween the registration of a READ command and the
availability of the first piece of output data. The la-
tency can be set to two or three clocks.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available by
clock edge n + m. The DQs will start driving as a result of
the clock edge one cycle earlier (n + m - 1), and provided
that the relevant access times are met, the data will be
valid by clock edge n + m. For example, assuming that
the clock cycle time is such that all relevant access times
are met, if a READ command is registered at T0 and the
latency is programmed to two clocks, the DQs will start
driving after T1 and the data will be valid by T2, as
shown in Figure 1. Table 1 indicates the operating fre-
quencies at which each CAS latency setting can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions
may result.
Operating Mode
The normal operating mode is selected by setting
M7 and M8 to zero; the other combinations of values for
M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
READ and WRITE bursts.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
When M9 = 0, the burst length programmed via
M0-M2 applies to both READ and WRITE bursts; when
M9 = 1, the programmed burst length applies to
READ bursts, but write accesses are single-location
(nonburst) accesses.
9
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2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
TRUTH TABLE SDRAM COMMANDS AND DQMB OPERATION
(Note: 1)
NAME (FUNCTION)
CS# RAS# CAS# WE# DQMB ADDR
DQs
NOTES
COMMAND INHIBIT (NOP)
H
X
X
X
X
X
X
NO OPERATION (NOP)
L
H
H
H
X
X
X
ACTIVE (Select bank and activate row)
L
L
H
H
X
Bank/Row
X
3
READ (Select bank and column, and start READ burst)
L
H
L
H
L/H
8
Bank/Col
X
4
WRITE (Select bank and column, and start WRITE burst)
L
H
L
L
L/H
8
Bank/Col
Valid
4
BURST TERMINATE
L
H
H
L
X
X
Active
PRECHARGE (Deactivate row in bank or banks)
L
L
H
L
X
Code
X
5
AUTO REFRESH or SELF REFRESH
L
L
L
H
X
X
X
6, 7
(Enter self refresh mode)
LOAD MODE REGISTER
L
L
L
L
X
Op-Code
X
2
Write Enable/Output Enable
L
Active
8
Write Inhibit/Output High-Z
H
High-Z
8
NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-A12 define the op-code written to the Mode Register, and should be driven low.
3. A0-A12 provide device row address. BA0, BA1 determine which device bank is made active.
4. A0-A9 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW
disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to.
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged and
BA0, BA1 are "Don't Care."
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
COMMANDS
The following Truth Table provides a general refer-
ence of available commands. For a more detailed descrip-
tion of commands and operations, refer to the 256Mb
SDRAM component data sheet.
10
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2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS*
Voltage on V
DD
, V
DD
Q Supply
Relative to V
SS
....................................... -1V to +4.6V
Voltage on Inputs, NC or I/O Pins
Relative to V
SS
....................................... -1V to +4.6V
Operating Temperature,
T
A
(commercial) ....................................... 0C to +70C
Storage Temperature (plastic) ............ -55C to +150C
Power Dissipation ........................................................ 8W
*Stresses greater than those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only, and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of
this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect reliability.
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(Notes: 1, 5, 6; notes appear following the parameter tables) (V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS NOTES
SUPPLY VOLTAGE
V
DD
, V
DD
Q
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
2
V
DD
+ 0.3
V
22
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-0.3
0.8
V
22
INPUT LEAKAGE CURRENT:
Any input 0V
V
IN
V
DD
I
I
-40
40
A
32
(All other pins not under test = 0V)
OUTPUT LEAKAGE CURRENT: DQs are disabled;
I
OZ
-40
40
A
32
0V
V
OUT
V
DD
Q
OUTPUT LEVELS:
V
OH
2.4
V
Output High Voltage (I
OUT
= -4mA)
Output Low Voltage (I
OUT
= 4mA)
V
OL
0.4
V
11
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256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
I
DD
SPECIFICATIONS AND CONDITIONS*
(Notes: 1, 5, 6, 11, 13; notes appear following the parameter tables) (V
DD
, V
DD
Q = +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL -13E -133 -10E UNITS NOTES
OPERATING CURRENT: Active Mode;
I
DD
1
1,080 1,000 1,000
mA
3, 18,
Burst = 2; READ or WRITE;
t
RC =
t
RC (MIN)
19, 29
STANDBY CURRENT: Power-Down Mode;
I
DD
2
16
16
16
mA
29
All device banks idle; CKE = LOW
STANDBY CURRENT: Active Mode;
I
DD
3
320
320
320
mA
3, 12,
CKE = HIGH; CS# = HIGH; All device banks active after
t
RCD met;
19, 29
No accesses in progress
OPERATING CURRENT: Burst Mode; Continuous burst;
I
DD
4
1,080 1,080 1,080
mA
3, 18,
READ or WRITE; All device banks active
19, 29
AUTO REFRESH CURRENT
t
RFC =
t
RFC (MIN)
I
DD
5
2,280 2,160 2,160
mA
3, 12,
CS# = HIGH; CKE = HIGH
t
RFC = 7.81 s
I
DD
6
28
28
28
mA
18, 19,
29, 30
SELF REFRESH CURRENT: CKE
0.2V
Standard
I
DD
7
20
20
20
mA
4
Low power (L)
I
DD
7
12
12
12
mA
MAX
*DRAM components only.
12
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256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
ELECTRICAL CHARACTERISTICS AND RECOMMENDEDAC OPERATING CONDITIONS
(Notes: 5, 6, 8, 9, 11, 31; notes appear following the parameter tables) (V
DD
, V
DD
Q = +3.3V 0.3V)
AC CHARACTERISTICS
-13E
-133
-10E
PARAMETER
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
Access time from
CL = 3
t
AC(3)
5.4
5.4
6
ns
27
CLK (pos. edge)
CL = 2
t
AC(2)
5.4
6
6
ns
Address hold time
t
AH
0.8
0.8
1
ns
Address setup time
t
AS
1.5
1.5
2
ns
CLK high-level width
t
CH
2.5
2.5
3
ns
CLK low-level width
t
CL
2.5
2.5
3
ns
Clock cycle time
CL = 3
t
CK(3)
7
7.5
8
ns
23
CL = 2
t
CK(2)
7.5
10
10
ns
23
CKE hold time
t
CKH
0.8
0.8
1
ns
CKE setup time
t
CKS
1.5
1.5
2
ns
CS#, RAS#, CAS#, WE#, DQM hold time
t
CMH
0.8
0.8
1
ns
CS#, RAS#, CAS#, WE#, DQM setup time
t
CMS
1.5
1.5
2
ns
Data-in hold time
t
DH
0.8
0.8
1
ns
Data-in setup time
t
DS
1.5
1.5
2
ns
Data-out high-impedance
CL = 3
t
HZ(3)
5.4
5.4
6
ns
10
time
CL = 2
t
HZ(2)
5.4
6
6
ns
10
Data-out low-impedance time
t
LZ
1
1
1
ns
Data-out hold time (load)
t
OH
3
3
3
ns
Data-out hold time (no load)
t
OH
N
1.8
1.8
1.8
ns
28
ACTIVE to PRECHARGE command
t
RAS
37
120,000
44
120,000
50
120,000
ns
29
ACTIVE to ACTIVE command period
t
RC
60
66
70
ns
ACTIVE to READ or WRITE delay
t
RCD
15
20
20
ns
Refresh period (8,192 rows)
t
REF
64
64
64
ms
AUTO REFRESH period
t
RFC
66
66
70
ns
PRECHARGE command period
t
RP
15
20
20
ns
ACTIVE bank a to ACTIVE bank b command
t
RRD
14
15
20
ns
Transition time
t
T
0.3
1.2
0.3
1.2
0.3
1.2
ns
7
WRITE recovery time
t
WR
1 CLK +
1 CLK +
1 CLK +
ns
24
7ns
7.5ns
7ns
14
15
15
ns
25
Exit SELF REFRESH to ACTIVE command
t
XSR
67
75
80
ns
20
CAPACITANCE
(Note 2; notes appear following parameter tables)
PARAMETER
SYMBOL MIN
MAX UNITS
Input Capacitance: A0-A12, BA0, BA1, RAS#, CAS#, WE#, CKE0, S0#
C
I
1
12
30.4
p F
Input Capacitance: CK0, CK1
C
I
2
6
14
p F
Input Capacitance: DQM0-DQM7
C
I
4
1.5
3.8
p F
Input/Output Capacitance: SCL, SA0-SA2, SDA
C
I
5
10
p F
Input/Output Capacitance: DQ0-DQ63
C
IO
3
6
p F
13
32/64 Meg x 64 SDRAM SODIMM
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2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
AC FUNCTIONAL CHARACTERISTICS
(Notes: 5, 6, 7, 8, 9, 11, 31; notes appear following the parameter tables) (0C
T
A
+70C)
PARAMETER
SYMBOL
-13E
-133
-10E
UNITS NOTES
READ/WRITE command to READ/WRITE command
t
CCD
1
1
1
t
CK
17
CKE to clock disable or power-down entry mode
t
CKED
1
1
1
t
CK
14
CKE to clock enable or power-down exit setup mode
t
PED
1
1
1
t
CK
14
DQM to input data delay
t
DQD
0
0
0
t
CK
17
DQM to data mask during WRITEs
t
DQM
0
0
0
t
CK
17
DQM to data high-impedance during READs
t
DQZ
2
2
2
t
CK
17
WRITE command to input data delay
t
DWD
0
0
0
t
CK
17
Data-in to ACTIVE command
t
DAL
4
5
4
t
CK
15, 21
Data-in to PRECHARGE command
t
DPL
2
2
2
t
CK
16, 21
Last data-in to burst STOP command
t
BDL
1
1
1
t
CK
17
Last data-in to new READ/WRITE command
t
CDL
1
1
1
t
CK
17
Last data-in to PRECHARGE command
t
RDL
2
2
2
t
CK
16, 21
LOAD MODE REGISTER command to ACTIVE or REFRESH command
t
MRD
2
2
2
t
CK
26
Data-out to high-impedance from PRECHARGE command
CL = 3
t
ROH(3)
3
3
3
t
CK
17
CL = 2
t
ROH(2)
2
2
2
t
CK
17
14
32/64 Meg x 64 SDRAM SODIMM
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256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
14. Timing actually specified by
t
CKS; clock(s) speci-
fied as a reference only at minimum cycle rate.
15. Timing actually specified by
t
WR plus
t
RP; clock(s)
specified as a reference only at minimum cycle
rate.
16. Timing actually specified by
t
WR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any timing param-
eter.
18. The I
DD
current will increase or decrease propor-
tionally according to the amount of frequency al-
teration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK must be toggled a minimum of two times dur-
ing this period.
21. Based on
t
CK = 10ns for -10E, and
t
CK = 7.5ns for -
133 and -13E.
22. V
IH
overshoot: V
IH
(MAX) = V
DD
Q + 2V for a pulse
width
3ns, and the pulse width cannot be greater
than one third of the cycle rate. V
IL
undershoot: V
IL
(MIN) = -2V for a pulse width
3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
t
WR, and PRECHARGE commands). CKE may be
used to reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (
t
RP) begins 7ns for -13E; 7.5ns for -133
and 7ns for -10E after the first clock delay, after the
last WRITE is executed. May not exceed limit set
for precharge mode.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
t
AC for -133/-13E at CL = 3 with no load is 4.6ns and
is guaranteed by design.
28. Parameter guaranteed by design.
29. The value of
t
RAS used in -13E speed grade mod-
ule SPDs is calculated from
t
RC -
t
RP.
30. For -10E, CL= 2 and
t
CK = 10ns; for -133, CL = 3 and
t
CK = 7.5ns; for -13E, CL = 2 and
t
CK = 7.5ns.
31. CKE is HIGH during refresh command period
t
RFC (MIN) else CKE is LOW. The I
DD
6 limit is actu-
ally a nominal value and does not result in a fail
value.
32. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
NOTES
1.
All voltages referenced to V
SS
.
2.
This parameter is sampled. V
DD
, V
DD
Q = +3.3V;
f = 1 MHz, T
A
= 25C; pin under test biased at 1.4V.
3.
I
DD
is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range is ensured (0C
T
A
+70C).
6.
An initial pause of 100s is required after power-
up, followed by two AUTO REFRESH commands,
before proper device operation is ensured. (V
DD
and V
DD
Q must be powered up simultaneously. V
SS
and V
SS
Q must be at same potential.) The two
AUTO REFRESH command wake-ups should be
repeated any time the
t
REF refresh requirement is
exceeded.
7.
AC characteristics assume
t
T = 1ns.
8.
In addition to meeting the transition rate specifi-
cation, the clock and CKE must transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
9.
Outputs measured at 1.5V with equivalent load:
Q
50pF
10.
t
HZ defines the time at which the output achieves
the open circuit condition; it is not a reference to
V
OH
or V
OL
. The last valid data element will meet
t
OH before going High-Z.
11. AC timing and I
DD
tests have V
IL
= 0V and V
IH
= 3V,
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V
IL
(MAX) and V
IH
(MIN)
and no longer at the 1.5V crossover point. Refer to
Micron Technical Note, TN-48-09, for additional
information on SDRAM timing.
12. Other input signals are allowed to transition no
more than once every two clocks and are otherwise
at valid V
IH
or V
IL
levels.
13. I
DD
specifications are tested after the device is prop-
erly initialized.
15
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2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
SCL
SDA
DATA STABLE
DATA STABLE
DATA
CHANGE
Figure 3
Data Validity
SCL
SDA
START
BIT
STOP
BIT
Figure 4
Definition of Start and Stop
SCL from Master
Data Output
from Transmitter
Data Output
from Receiver
9
8
Acknowledge
Figure 5
Acknowledge Response From Receiver
SPD CLOCK AND DATA CONVENTIONS
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions as
indicated in Figures 3 and 4.
SPD START CONDITION
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL is
HIGH. The SPD device continuously monitors the SDA
and SCL lines for the start condition and will not re-
spond to any command until this condition has been
met.
SPD STOP CONDITION
All communications are terminated by a stop condi-
tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
SPD ACKNOWLEDGE
Acknowledge is a software convention used to indi-
cate successful data transfers. The transmitting de-
vice, either master or slave, will release the bus after
transmitting eight bits. During the ninth clock cycle,
the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data as indicated in
Figure 5.
The SPD device will always respond with an ac-
knowledge after recognition of a start condition and its
slave address. If both the device and a WRITE opera-
tion have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop con-
dition to return to standby power mode.
16
32/64 Meg x 64 SDRAM SODIMM
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2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
SCL
SDA IN
SDA OUT
tLOW
tSU:STA
tHD:STA
tF
tHIGH
tR
tBUF
tDH
tAA
tSU:STO
tSU:DAT
tHD:DAT
UNDEFINED
SPD EEPROM TIMING DIAGRAM
SERIAL PRESENCE-DETECT EEPROM TIMING
PARAMETERS
SYMBOL
MIN
MAX
UNITS
t
AA
0.3
3.5
s
t
BUF
4.7
s
t
DH
300
ns
t
F
300
ns
t
HD:DAT
0
s
t
HD:STA
4
s
SYMBOL
MIN
MAX
UNITS
t
HIGH
4
s
t
LOW
4.7
s
t
R
1
s
t
SU:DAT
250
ns
t
SU:STA
4.7
s
t
SU:STO
4.7
s
EEPROM DEVICE SELECT CODE
The most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
Memory Area Select Code (two arrays)
1
0
1
0
E2
E1
E0
RW
Protection Register Select Code
0
1
1
0
E2
E1
E0
RW
EEPROM OPERATING MODES
MODE
RW BIT
WC
1
BYTES
INITIAL SEQUENCE
Current Address Read
1
X
1
START, Device Select, RW = `1'
Random Address Read
0
X
1
START, Device Select, RW = `0', Address
1
X
1
reSTART, Device Select, RW = `1'
Sequential Read
1
X


1
Similar to Current or Random Address Read
Byte Write
0
V
IL
1
START, Device Select, RW = `0'
Page Write
0
V
IL
16
START, Device Select, RW = `0'
NOTE: 1. X = V
IH
or V
IL
.
17
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS
(Note: 1) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
SUPPLY VOLTAGE
V
DD
3
3.6
V
INPUT HIGH VOLTAGE: Logic 1; All inputs
V
IH
V
DD
x 0.7
V
DD
+ 0.5
V
INPUT LOW VOLTAGE: Logic 0; All inputs
V
IL
-1
V
DD
x 0.3
V
OUTPUT LOW VOLTAGE: I
OUT
= 3mA
V
OL
0.4
V
INPUT LEAKAGE CURRENT: V
IN
= GND to V
DD
I
LI
10
A
OUTPUT LEAKAGE CURRENT: V
OUT
= GND to V
DD
I
LO
10
A
STANDBY CURRENT:
I
SB
30
A
SCL = SDA = V
DD
- 0.3V; All other inputs = GND or 3.3V +10%
POWER SUPPLY CURRENT:
I
DD
2
mA
SCL clock frequency = 100 KHz
SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS
(Note: 2) (V
DD
= +3.3V 0.3V)
PARAMETER/CONDITION
SYMBOL
MIN
MAX
UNITS
NOTES
SCL LOW to SDA data-out valid
t
AA
0.3
3.5
s
Time the bus must be free before a new transition can start
t
BUF
4.7
s
Data-out hold time
t
DH
300
ns
SDA and SCL fall time
t
F
300
ns
Data-in hold time
t
HD:DAT
0
s
Start condition hold time
t
HD:STA
4
s
Clock HIGH period
t
HIGH
4
s
Noise suppression time constant at SCL, SDA inputs
t
I
100
ns
Clock LOW period
t
LOW
4.7
s
SDA and SCL rise time
t
R
1
s
SCL clock frequency
t
SCL
100
KHz
Data-in setup time
t
SU:DAT
250
ns
Start condition setup time
t
SU:STA
4.7
s
Stop condition setup time
t
SU:STO
4.7
s
WRITE cycle time
t
WRC
10
ms
3
NOTE: 1. All voltages referenced to V
SS
.
2. All voltages referenced to V
SS
.
3. Timing actually specified by
t
WR.
18
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
SERIAL PRESENCE-DETECT MATRIX
(Note: 1)
MT8LSDF3264WG
BYTE
DESCRIPTION
ENTRY (VERSION)
HEX VALUE
0
NUMBER OF BYTES USED BY MICRON
128
80
1
TOTAL NUMBER OF SPD MEMORY BYTES
256
08
2
MEMORY TYPE
SDRAM
04
3
NUMBER OF ROW ADDRESSES
13
0D
4
NUMBER OF COLUMN ADDRESSES
10
0A
5
NUMBER OF BANKS
1
01
6
MODULE DATA WIDTH (bit 0 is LSB)
64
40
7
MODULE DATA WIDTH (bit 7 is MSB)
00
00
8
MODULE VOLTAGE INTERFACE LEVELS
LVTTL
01
9
SDRAM CYCLE TIME,
t
CK
70
70
(CAS LATENCY = 3)
7.5 (-133)
75
8 (-10E)
80
10
SDRAM ACCESS FROM CLOCK,
t
AC
5.4 (-13E/-133)
54
(CAS LATENCY = 3)
6 (-10E)
60
11
MODULE CONFIGURATION TYPE
NON PARITY
00
12
REFRESH RATE/TYPE
7.8/SELF
82
13
SDRAM WIDTH (PRIMARY SDRAM)
8
08
14
ERROR-CHECKING SDRAM DATA WIDTH
NONE
00
15
MIN. CLOCK DELAY FROM BACK-TO-BACK RANDOM COLUMN ADDRESSES,
t
CCD
1
01
16
BURST LENGTHS SUPPORTED
1, 2, 4, 8, FULL-PAGE
8F
17
NUMBER OF BANKS ON SDRAM DEVICE
4
04
18
CAS LATENCIES SUPPORTED
2,3
06
19
CS LATENCY
1
01
20
WE LATENCY
1
01
21
SDRAM MODULE ATTRIBUTES
UNBUFFERED
00
22
SDRAM DEVICE ATTRIBUTES: GENERAL
14
0E
23
SDRAM CYCLE TIME,
t
CK
7.5 (-13E)
75
(CAS LATENCY = 2)
10 (-133/-10E)
A0
24
SDRAM ACCESS FROM CLK,
t
AC
5.4 (-13E)
54
(CAS LATENCY = 2)
6 (-133/-10E)
60
25
SDRAM CYCLE TIME,
t
CK
00
00
(CAS LATENCY = 1)
26
SDRAM ACCESS FROM CLK,
t
AC
00
00
(CAS LATENCY = 1)
27
MINIMUM ROW PRECHARGE TIME,
t
RP
15 (-13E)
0F
20 (-133/-10E)
14
28
MINIMUM ROW ACTIVE TO ROW ACTIVE,
t
RRD
14 (-13E)
0E
15 (-133)
0F
20 (-10E)
14
29
MINIMUM RAS# TO CAS# DELAY,
t
RCD
15 (-13E)
0F
20 (-133/-10E)
14
30
MINIMUM RAS# PULSE WIDTH, (
t
RAS MODULE =
t
RC -
t
RP)
45 (-13E)*
2D
44 (-133)
2C
50 (-10E)
32
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. The value of
t
RAS used for the -13E module is calculated from
t
RC -
t
RP. Actual device spec value is 37ns.
19
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
SERIAL PRESENCE-DETECT MATRIX (continued)
(Note: 1, 2)
MT8LSDF3264WG
BYTE
DESCRIPTION
ENTRY (VERSION)
HEX VALUE
31
MODULE BANK DENSITY
256MB
40
32
COMMAND AND ADDRESS SETUP TIME,
t
AS,
t
CMS
1.5 (-13E/-133)
15
2 (-10E)
20
33
COMMAND AND ADDRESS HOLD TIME,
t
AH,
t
CMH
0.8 (--13E/133)
08
1 (-10E)
10
34
DATA SIGNAL INPUT SETUP TIME,
t
DS
1.5 (-13E/-133)
15
2 (-10E)
20
35
DATA SIGNAL INPUT HOLD TIME,
t
DH
0.8 (-13E/-133)
08
1 (-10E)
10
36-61
RESERVED
00
00
62
SPD REVISION
REV. 1.2B
12
63
CHECKSUM FOR BYTES 0-62
-13E
8B
-133
D1
-10E
19
64
MANUFACTURER'S JEDEC ID CODE
MICRON
2C
65-71
MANUFACTURER'S JEDEC ID CODE (CONT.)
FF
FF
72
MANUFACTURING LOCATION
0111
010B
73-90
MODULE PART NUMBER (ASCII)
xx
91
PCB IDENTIFICATION CODE
1-9
01-09
92
IDENTIFICATION CODE (CONT.)
0
00
93
YEAR OF MANUFACTURE IN BCD
xx
xx
94
WEEK OF MANUFACTURE IN BCD
xx
xx
95-98
MODULE SERIAL NUMBER
xx
xx
99-125
MANUFACTURER-SPECIFIC DATA (RSVD)
126
SYSTEM FREQUENCY
100/133 MHz
64
127
SDRAM COMPONENT AND CLOCK DETAIL
CK0, CK1, A/P
CF
NOTE: 1. "1"/"0": Serial Data, "driven to HIGH"/"driven to LOW."
2. x = Variable Data.
20
32/64 Meg x 64 SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SDF8C32x64WG_A.p65; Rev. A, Pub. 1/02
2001, Micron Technology, Inc.
256MB (x64)
SDRAM MICRODIMM
PRELIMINARY
NOTE: 1. All dimensions in millimeter (inches)
MAX
or typical where noted.
MIN
2. Unless otherwise given, tolerances are 0.05mm (0.002).
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron is a registered trademark and the Micron logo and M logo are trademarks of Micron Technology, Inc.
DATA SHEET DESIGNATION
Preliminary: This data sheet contains initial characterization limits that are subject to change upon full characterization of production
devices.
3.80 (.150)
30 (1.181)
38 (1.496)
9.98 (.393)
5.99 (.236)
0 (0)
2.00 (.079)
7 (.276)
34 (1.339)
0 (0)
1.00 (.044)
2.00 (.080)
R1 (.039)
0.1 (.004)
4 Places
R1 (.039)
0.1 (.004)
MAX
0.876 (.0345)
0.724 (.0285)
U1
U2
U9
U3
U4
SECONDARY SIDE
U5
U6
U7
U8
PIN 144
PIN 2
PRIMARY SIDE
144-PIN MICRODIMM
256MB MODULE