09005aef808016ae
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4_8C16_32_64X32UG_A.fm - Rev. A 2/03 EN
1
2003, Micron Technology Inc.
64MB, 128MB, 256MB (x32)
100-PIN SDRAM DIMM
SYNCHRONOUS
DRAM MODULE
MT4LSDT1632U
-
64MB
;
MT8LSDT1632U
-
64MB
MT8LSDT3232U
-
128MB
;
MT8LSDT6432U
-
256MB
For the latest data sheet, please refer to the Micron
Web site:
www.micron.com/moduleds
Features
JEDEC pinout in a 100-pin, dual in-line memory
module (DIMM)
64MB (16 Meg x 32) , 128MB (32 Meg x 32), and
256MB (64 Meg x 32)
Utilizes 100 MHz and 125 MHz SDRAM
components
Single +3.3V power supply
Fully synchronous; all signals registered on positive
edge of system clock
Internal pipelined operation; column address can
be changed every clock cycle
Internal banks for hiding row access/precharge
Programmable burst lengths: 1, 2, 4, 8, or full page
Auto Precharge and Auto Refresh Modes
64MB and 128 MB modules; 64ms, 4,096-cycle
refresh (15.625s refresh interval); 256MB modules;
64ms, 8,192-cycle refresh (7.81s refresh interval)
LVTTL-compatible inputs and outputs
Serial Presence-Detect (SPD
)
Figure 1: 100-Pin DIMM (MO-161)
Table 1:
Timing Parameters
CL = CAS (READ) latency
MODULE
MARKING
CLOCK
FREQUENCY
ACCESS TIME
SETUP
TIME
HOLD
TIME
CL = 2 CL = 3
-75
133 MHz
5.4ns
1.5ns
0.8ns
-8
125 MHz
6ns
6ns
2ns
1ns
-10
100 MHz
9ns
7.5ns
2ns
1ns
OPTIONS MARKING
Package
100-pin DIMM (Gold)
G
100-pin DIMM (Lead-Free)
Y
Frequency / CAS Latency
133 MHz (7.5ns) / CL = 3
-75
125 MHz (8ns) / CL = 3
-8
100 MHz (10ns) / CL = 2
-10
Table 2:
Address Table
MODULE DENSITY
MT4LSDT1632U
MT8LSDT1632U
MT8LSDT3232U
MT8LSDT6432U
Refresh Count
4K
4K
4K
8K
Device Banks
4 (BA0-BA1)
4 (BA0-BA1)
4 (BA0-BA1)
4 (BA0-BA1)
Device Configuration
16 Meg x 8
8 Meg x 8
16 Meg x 8
32 Meg x 8
Device Row Addressing
4K (A0-A11)
4K (A0-A11)
4K (A0-A11)
8K (A0-A12)
Device Column Addressing
1K (A0-A9)
512 (A0-A8)
1K (A0-A9)
1K (A0-A9)
Module Ranks
1 (S0#, S2#)
2 (S0#, S2#; S1#, S3#) 2 (S0#, S2#; S1#, S3#) 2 (S0#, S2#; S1#, S3#)
64MB, 128MB, 256MB (x32)
100-PIN SDRAM DIMM
09005aef808016ae
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4_8C16_32_64X32UG_A.fm - Rev. A 2/03 EN
2
2003, Micron Technology Inc.
NOTE:
Pin 20 is A12 for 256MB module; for all others NC.
Figure 2: Pin Locations (100-Pin DIMM)
Table 3:
Part Numbers
PART NUMBER
CONFIGURATION
SYSTEM BUS
SPEED
MT4LSDT1632UG-75__
16 Meg x 32
133 MHz
MT4LSDT1632UY-75__
16 Meg x 32
133 MHz
MT4LSDT1632UG-8__
16 Meg x 32
125 MHz
MT4LSDT1632UY-8__
16 Meg x 32
125 MHz
MT4LSDT1632UG-10__
16 Meg x 32
100 MHz
MT4LSDT1632UY-10__
16 Meg x 32
100 MHz
MT8LSDT1632UG-75__
16 Meg x 32
133 MHz
MT8LSDT1632UY-75__
16 Meg x 32
133 MHz
MT8LSDT1632UG-8__
16 Meg x 32
125 MHz
MT8LSDT1632UY-8__
16 Meg x 32
125 MHz
MT8LSDT1632UG-10__
16 Meg x 32
100 MHz
MT8LSDT1632UY-10__
16 Meg x 32
100 MHz
MT8LSDT3232UG-75__
32 Meg x 32
133 MHz
MT8LSDT3232UY-75__
32 Meg x 32
133 MHz
MT8LSDT3232UG-8__
32 Meg x 32
125 MHz
MT8LSDT3232UY-8__
32 Meg x 32
125 MHz
MT8LSDT3232UG-10__
32 Meg x 32
100 MHz
MT8LSDT3232UY-10__
32 Meg x 32
100 MHz
MT8LSDT6432UG-75__
64 Meg x 32
133 MHz
MT8LSDT6432UY-75__
64 Meg x 32
133 MHz
MT8LSDT6432UG-8__
64 Meg x 32
125 MHz
MT8LSDT6432UY-8__
64 Meg x 32
125 MHz
MT8LSDT6432UG-10__
64 Meg x 32
100 MHz
MT8LSDT6432UY-10__
64 Meg x 32
100 MHz
Table 4:
Pin Assignment Front
(100-Pin DIMM)
PIN SYMBOL PIN
SYMBOL
PIN
SYMBOL
PIN SYMBOL
1
Vss
13
A0
26
Vss
38
DQ16
2
DQ0
14
A2
27
CKE0
39
DQ17
3
DQ1
15
A4
28
WE#
40
DQ18
4
DQ2
16
A6
29
S0#
41
DQ19
5
DQ3
17
A8
30
S2#
42
V
DD
6
V
DD
18
A10
31
V
DD
43
DQ20
7
DQ4
19
BA1
32
NC
44
DQ21
8
DQ5
20
A12
/NC
33
NC
45
DQ22
9
DQ6
21
V
DD
34
NC
46
DQ23
10
DQ7
22
NC
35
NC
47
Vss
11
DQMB0
23
RFU
36
Vss
48
SDA
12
Vss
24
RFU
37
DQMB2
49
SCL
25
CK0
50
V
DD
Table 5:
Pin Assignment Back
(100-Pin DIMM)
PIN SYMBOL PIN
SYMBOL
PIN
SYMBOL
PIN SYMBOL
51
Vss
63
A1
76
Vss
88
DQ24
52
DQ8
64
A3
77
CKE1
89
DQ25
53
DQ9
65
A5
78
NC
90
DQ26
54
DQ10
66
A7
79
S1#
91
DQ27
55
DQ11
67
A9
80
S3#
92
V
DD
56
V
DD
68
BA0
81
V
DD
93
DQ28
57
DQ12
69
A11
82
NC
94
DQ29
58
DQ13
70
NC
83
NC
95
DQ30
59
DQ14
71
V
DD
84
NC
96
DQ31
60
DQ15
72
RAS#
85
NC
97
Vss
61
DQMB1
73
CAS#
86
Vss
98
SA0
62
Vss
74
RFU
87
DQMB3
99
SA1
75
CK1
100
SA2
Indicates a V
DD
or V
DD
Q
pin
Indicates a V
SS
pin
PIN 1
PIN 50
U1
U2
U3
U4
U9
Front View
PIN 100
PIN 51
U8
U7
U6
U5
Back View
(Not Populated for MT4LSDT1632U Module)
64MB, 128MB, 256MB (x32)
100-PIN SDRAM DIMM
09005aef808016ae
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4_8C16_32_64X32UG_A.fm - Rev. A 2/03 EN
3
2003, Micron Technology Inc.
Table 6:
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to the Pin Assignment Tables on page 2 for more information
PIN NUMBER
SYMBOL
TYPE
DESCRIPTION
28, 72, 73
WE#, RAS#,
CAS#
Input
Command Inputs: RAS#, CAS# and WE# (along with S#) define the command
being entered.
25, 75
CK0, CK1
Input
Clock: CK is driven by the system clock. All SDRAM input signals are sampled
on the positive edge of CK. CK also increments the internal burst counter
and controls the output registers.
27, 77
CKE0, CKE1
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal.
Deactivating the clock provides POWER-DOWN and SELF REFRESH operation
(all banks idle), or CLOCK SUSPEND operation (burst access in progress). CKE
is synchronous except after the device enters power-down and self refresh
modes, where CKE becomes asynchronous until after exiting the same mode.
The input buffers, including CK, are disabled during power-down and self
refresh modes, providing low standby power.
29, 30, 79, 80
S0#-S3#
Input
Chip Select: S# enables (registered LOW) or disables (registered HIGH) the
the command decoder. All commands are masked when S# is registered
HIGH. S# is considered part of the command code.
11, 37, 61, 87
DQMB0-
DQMB3
Input
Input/Output Mask: DQMB is an input mask signal for write accesses and an
output enable signal for read accesses. Input data is masked when DQMB is
sampled HIGH during a WRITE cycle. The output buffers are placed in a High-
Z state (after a two-clock latency) when DQMB is sampled HIGH during a
READ cycle.
19, 68
BA0, BA1
Input
Device Bank Address: BA0 and BA1 define to which device bank the ACTIVE,
READ, WRITE, or PRECHARGE command is being applied.
13, 14, 15, 16, 17,
18, 20
(256MB)
,
63, 64, 65, 66, 67,
69
A0-A11
(64MB, 128MB)
A0-A12
(256MB)
Input
Address Inputs: Provide the row address for ACTIVE commands, and the
column address and auto precharge bit (A10) for READ/WRITE commands, to
select one location out of the memory array in the respective device bank.
A10 is sampled during a PRECHARGE command to determine whether the
PRECHARGE applies to one device bank (A10 LOW, device bank selected by
BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the
op-code during a LOAD MODE REGISTER command.
49
SCL
Input
Serial Clock for Presence-Detect: SCL is used to synchronize the presence-
detect data transfer to and from the module.
98-100
SA0-SA2
Input
Presence-Detect Address Inputs: These pins are used to configure the
presence-detect device.
2-5, 7-10, 38-41,
43-46, 52-55, 57-
60, 88-91, 93-96
DQ0-DQ31
Input/
Output
Data I/Os: Data bus.
48
SDA
Input/
Output
Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer
addresses and data into and data out of the presence-detect portion of the
module.
6, 21, 31, 42, 50,
56, 71, 81, 92
V
DD
Supply Power Supply: +3.3V 0.3V.
1, 12, 26, 36, 47,
51, 62, 76, 86, 97
V
SS
Supply Ground.
23, 24, 74
RFU
Reserved for Future Use: These pins should be left unconnected.
20
(64MB, 128MB)
,
22, 32-35, 70, 78,
82-85
NC
Not connected.
64MB, 128MB, 256MB (x32)
100-PIN SDRAM DIMM
09005aef808016ae
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4_8C16_32_64X32UG_A.fm - Rev. A 2/03 EN
4
2003, Micron Technology Inc.
Figure 3: Functional Block Diagram (MT4LSDT1632U)
RAS#
CAS#
CKE0
RAS#: SDRAMs
CAS#: SDRAMs
CKE0: SDRAMs
WE#: SDRAMS
A0-A11: SDRAMs
BA: SDRAMs
BA: SDRAMs
WE#
A0-A11
BA0
BA1
V
DD
V
SS
SDRAMs
SDRAMs
U1
U2
U3
U4
CK0
DQM CS#
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMB3
DQM CS#
U3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
DQM CS#
U2
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB1
DQM CS#
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S2#
S0#
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
WP
SCL
U9
NOTE:
1. All resistor values are 10
W unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as referenced
in the Module Part Numbering Guide at
www.micron.com/numberguide
.
SDRAMs MT48LB16M8A2TG for MT4LSDT1632U
64MB, 128MB, 256MB (x32)
100-PIN SDRAM DIMM
09005aef808016ae
Micron Technology, Inc., reserves the right to change products or specifications without notice.
SD4_8C16_32_64X32UG_A.fm - Rev. A 2/03 EN
5
2003, Micron Technology Inc.
Figure 4: Functional Block Diagram
(MT8LSDT1632U, MT8LSDT3232U, and MT8LSDT6432U)
RAS#
CAS#
CKE0
RAS#: SDRAMs
CAS#: SDRAMs
CKE0: SDRAMs U1-U4
CKE1: SDRAMs U5-U8
WE#: SDRAMs
A0-A11: SDRAMs
A0-A12: SDRAMs
BA0: SDRAMs
BA1: SDRAMs
CKE1
WE#
A0-A11 (MT8LSDT1632U,
MT8LSDT3232U)
A0-A12 (MT8LSDT6432U)
BA0
BA1
V
DD
V
SS
SDRAMs U1-U8
SDRAMs U1-U8
U1
U2
U3
U4
CK0
U5
U6
U7
U8
CK1
DQM CS#
U8
DQM CS#
U7
DQM CS#
U6
DQM CS#
U5
DQM CS#
U4
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQMB3
DQM CS#
U3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQMB2
DQM CS#
U2
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQMB1
DQM CS#
U1
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQMB0
S2#
S0#
S3#
S1#
A0
SA0
SERIAL PD
SDA
A1
SA1
A2
SA2
WP
SCL
U9
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
NOTE:
1. All resistor values are
10
W unless otherwise specified.
2. Per industry standard, Micron utilizes various component speed grades as referenced
in the Module Part Numbering Guide at
www.micron.com/numberguide
.
SDRAMs = MT48LC8M8A2TG for MT8LSDT1632U
SDRAMs = MT48LC16M8A2TG for MT8LSDT3232U
SDRAMs = MT48LC32M8A2TG for MT8LSDT6432U
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