PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

09005aef80867a99
DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

DDR SDRAM
DIMM

MT8VDDT1664A 128MB
MT8VDDT3264A 256MB

For the latest data sheet, please refer to the Micron

Web

site:

www.micron.com/moduleds

Features

· 184-pin dual in-line memory module (DIMM)
· Fast data transfer rates: PC3200
· CAS Latency 3
· Utilizes 400 MT/s DDR SDRAM components
· 128MB (16 Meg x 64) and 256MB (32 Meg x 64)
· V

= V

Q= +2.6V

· V

DDSPD

= +2.3V to +3.6V

· 2.6V I/O (SSTL_2 compatible)
· Commands entered on each positive CK edge
· DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

· Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

· Bidirectional data strobe (DQS) transmitted/

received with data--i.e., source-synchronous data
capture

· Differential clock inputs (CK and CK#)
· Four internal device banks for concurrent operation
· Programmable burst lengths: 2, 4, or 8
· Auto precharge option
· Auto Refresh and Self Refresh Modes
· 15.6µs (128MB), 7.8125µs (256MB) maximum

average periodic refresh interval

· Serial Presence Detect (SPD) with EEPROM
· Programmable READ CAS latency
· Gold edge connectors

Figure 1: 184-Pin DIMM (MO-206)

NOTE:

All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT8VDDT3264AG-40BA1

OPTIONS

MARKING

· Package

184-pin DIMM (Standard)

184-pin DIMM (Lead-free)

· Memory Clock/Speed, CAS Latency

5ns (200 MHz), 400 MT/s, CL = 3

-40B

Table 1:

Address Table

128MB

256MB

Refresh Count

Row Addressing

4K (A0A11)

8K (A0A12)

Device Bank Addressing

4 (BA0, BA1)

Device Configuration

16 Meg x 8

32 Meg x 8

Column Addressing

1K (A0A9)

Module Rank Addressing

1 (S0#)

Table 2:

Part Numbers and Timing Parameters

PARTNUMBER

MODULE
DENSITY

CONFIGURATION

MODULE

BANDWITH

MEMORYCLOCK/

DATA RATE

LATENCY

(CL -

RCD -

RP)

MT8VDDT1664AG-40B__

128MB

16 Meg x 64

3.2 GB/s

5ns/400 MT/s

3-3-3

MT8VDDT1664AY-40B__

128MB

16 Meg x 64

3.2 GB/s

5ns/400 MT/s

3-3-3

MT8VDDT3264AG-40B__

256MB

32 Meg x 64

3.2 GB/s

5ns/400 MT/s

3-3-3

MT8VDDT3264AY-40B__

256MB

32 Meg x 64

3.2 GB/s

5ns/400 MT/s

3-3-3

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

NOTE:

Pin 115 is "No Connect" for the 128MB module, or "A12" for the 256MB module.

Figure 2: 184-Pin DIMM Pin Locations

Table 3:

Pin Assignment
(184-Pin DIMM Front)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

REF

DQ17

DNU

DQ0

DQS2

DNU

DQ48

DQ1

DQ49

DQS0

DQ18

DNU

DQ2

BA1

CK2#

DQ32

CK2

DQ3

DQ19

DQ33

DQS6

DQ24

DQS4

DQ50

DQ34

DQ51

DQ8

DQ25

DQ9

DQS3

BA0

DQS1

DQ35

DQ56

DQ40

DQ57

CK1

DQ26

CK1#

DQ27

WE#

DQS7

DQ41

DQ58

DQ10

CAS#

DQ59

DQ11

CKE0

DNU

DQS5

DNU

DQ42

SDA

DQ16

DQ43

SCL

Table 4:

Pin Assignment (184-Pin
DIMM Back)

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

116

139

162

DQ47

DQ4

117

DQ21

140

DNU

163

DQ5

118

A11

141

A10

164

119

DQS11/DM2

142

DNU

165

DQ52

DQS9/DM0

120

143

166

DQ53

DQ6

121

DQ22

144

DNU

167

DQ7

122

145

168

100

123

DQ23

146

DQ36

169

DQS15/DM6

101

124

147

DQ37

170

DQ54

102

125

148

171

DQ55

103

126

DQ28

149

DQS13/DM4

172

104

127

DQ29

150

DQ38

173

105

DQ12

128

151

DQ39

174

DQ60

106

DQ13

129

DQS12/DM3

152

175

DQ61

107

DQS10/DM1

130

153

DQ44

176

108

131

DQ30

154

RAS#

177

DQS16/DM7

109

DQ14

132

155

DQ45

178

DQ62

110

DQ15

133

DQ31

156

179

DQ63

111

DNU

134

DNU

157

S0#

180

112

135

DNU

158

DNU

181

SA0

113

136

159

DQS14/DM5

182

SA1

114

DQ20

137

CK0

160

183

SA2

115

NC/

A12

138

CK0#

161

DQ46

184

DDSPD

PIN 93

PIN 144

PIN 145

PIN 184

PIN 1

PIN 52

PIN 53

PIN 92

Indicates a V

or V

Q pin

Indicates a V

No Components This Side of Module

Back View

Front View

U10

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 2 for more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

REF

Input

SSTL_2 reference voltage.

63, 65, 154

WE#, CAS#,

RAS#

Input

Command Inputs: WE#, RAS#, and CAS# (along with S#) define
the command being entered.

16, 17, 75, 76, 137, 138

CK0, CK0#, CK1,

CK1#, CK2, CK2#

Input

Clocks: CK and CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the positive
edge of CK and negative edge of CK#. Output data (DQs and
DQS) is referenced to the crossings of CK and CK#.

CKE0

Input

Clock Enable: CKE activates (HIGH) and deactivates (LOW)
internal clock signals, device input buffers, and output drivers.
Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all device banks idle), or ACTIVE
POWER-DOWN (row ACTIVE in any device bank). CKE is
synchronous for all functions except for disabling outputs,
which is achieved asynchronously. CKE must be maintained
HIGH throughout read and write accesses. Input buffers
(excluding CK, CK# and CKE) are disabled during
POWERDOWN. Input buffers (excluding CKE) are disabled
during SELF REFRESH. CKE is an SSTL_2 input but will detect an
LVCMOS LOW level after V

is applied and until CKE is first

brought HIGH. After CKE is brought HIGH, it becomes an
SSTL_2 input only.

157

S0#

Input

Chip Select: S# enables (registered LOW) and disable (registered
HIGH) the command decoder. All commands are masked when
S# is registered HIGH. S# is considered part of the command
code.

52, 59

BA0, BA1

Input

Bank Addresses: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.

27, 29, 32, 37, 41, 43,

48, 115

(256MB),

118,

122, 125, 130, 141

A0-A11

128MB

A0-A12

256MB

Input

Address Inputs: Sampled during the ACTIVE command (row-
address) and READ/WRITE command (column-address, with A10
defining auto precharge) to select one location out of the
memory array in the respective device device bank. A10 is
sampled during a PRECHARGE command to determine whether
the PRECHARGE applies to one device bank (A10 LOW) or all
device banks (A10 HIGH). The address inputs also provide the
op-code during a MODE REGISTER SET command.

SDA

Input/

Output

Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.

SCL

Input

Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.

181, 182, 183

SA0-SA2

Input

Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.

5, 14, 25, 36, 56, 67, 78, 86,
97, 107, 119, 129, 149, 159,

169, 177

DQS0DQS7,

DQS9DQS16

Input/

Output

Data I/Os: Check bits. ECC, one-bit error detection and
correction.

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

2, 4, 6, 8, 12, 13, 19, 20, 23,

24, 28, 31, 33, 35, 39, 40,
53, 55, 57, 60, 61, 64, 68,
69, 72, 73, 79, 80, 83, 84,

87, 88, 94, 95, 98, 99, 105,

106, 109, 110, 114, 117,
121, 123, 126, 127, 131,
133, 146, 147, 150, 151,
153, 155, 161, 162, 165,
166, 170, 171, 174, 175,

178, 179

DQ0-DQ63

Input/

Output

Data I/Os: Data bus.

15, 22, 30, 54, 62, 77, 96,

104, 112, 128, 136, 143,

156, 164, 172, 180

Supply

DQ Power Supply: +2.6V ±0.1V.

7, 38, 46, 70, 85, 108, 120,

148, 168

Supply

Power Supply: +2.6V ±0.1V.

3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,

124, 132, 139, 145, 152,

160, 176

Supply

Ground.

184

DDSPD

Supply

Serial EEPROM positive power supply: +2.3V to +3.6V.

9, 10, 71, 82, 90, 101, 102,

103, 113, 115 (128MB),

163, 167, 173

No Connect: These pins should be left unconnected.

44, 45, 47, 49, 51, 111, 134,

135, 140, 142, 144, 158

DNU

Do Not Use: These pins are not connected on this module but
are assigned pins on other modules in this product family.

Table 5:

Pin Descriptions

Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables on page 2 for more information

PIN NUMBERS

SYMBOL

TYPE

DESCRIPTION

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

Figure 3: Functional Block Diagram

SA0

SERIAL PD

U10

SDA

SA1

SA2

BA0, BA1

A0-A11 (128MB)

A0-A12 (256MB)

RAS#

BA0, BA1: DDR SDRAMS

A0-A11: DDR SDRAMS

A0-A12: DDR SDRAMS

RAS#: DDR SDRAMS

CAS#: DDR SDRAMS

WE#: DDR SDRAMS

CKE0: DDR SDRAMS

CAS#

WE#

CKE0

REF

DDR SDRAMS

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DM CS# DQS

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS9/DM0

S0#

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

SCL

DM CS# DQS

DQS0

DQS13/DM4

DQS4

DQS10/DM1

DQS1

DQS14/DM5

DQS5

DQS11/DM2

DQS2

DQS15/DM6

DQS6

DM CS# DQS

DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ

DM CS# DQS

DQS12/DM3

DQS3

DQS16/DM7

DQS7

DDQ

DDR SDRAMS

DDR
SDRAM
X 2

CK0
CK0#

DDSPD

SPD

5.1

120

6pF

DDR
SDRAM
X 3

120

4.5pF

CK1
CK1#

DDR
SDRAM
X 3

120

4.5pF

CK2
CK2#

NOTE:

1. All resistor values are 22

W unless otherwise specified.

2. Per industry standard, Micron utilizes various component speed

grades as referenced in the Module Part Numbering Guide at

www.micron.com/numberguide

MT46V16M8TG = DDR SDRAMs, 128MB Modules
MT46V32M8TG = DDR SDRAMs, 256MB Modules

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

General Description

The MT8VDDT1664A and MT8VDDT3264A are

high-speed CMOS, dynamic random-access, 128MB
and 256MB memory modules organized in a x64 con-
figuration. DDR SDRAM modules use internally con-
figured quad-bank DDR SDRAM devices.

DDR SDRAM modules use a double data rate archi-

tecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architec-
ture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corre-
sponding n-bit wide, one-half-clock-cycle data trans-
fers at the I/O pins.

A bidirectional data strobe (DQS) is transmitted

externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.

DDR SDRAM modules operate from multiple differ-

ential clocks (CK and CK#); the crossing of CK going
HIGH and CK# going LOW will be referred to as the
positive edge of CK. Commands (address and control
signals) are registered at every positive edge of CK.
Input data is registered on both edges of DQS, and out-
put data is referenced to both edges of DQS, as well as
to both edges of CK.

Read and write accesses to DDR SDRAM modules

are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select devices bank; A0A11 select
device row for the 128MB module, A0A12 select
device row for the 256MB module). The address bits
registered coincident with the READ or WRITE com-
mand are used to select the device bank and the start-
ing device column location for the burst access.

DDR SDRAM modules provide for programmable

read or write burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.

The pipelined, multibank architecture of DDR

SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.

An auto refresh mode is provided, along with a

power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All out-
puts are SSTL_2, Class II compatible. For more
information regarding DDR SDRAM operation, refer to
the 128Mb and 256Mb DDR SDRAM data sheets.

Serial Presence-Detect Operation

DDR SDRAM modules incorporate serial presence-

detect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I

C bus

using the DIMM's SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the DDR SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency and an operating mode, as shown in
Figure 4, Mode Register Definition Diagram, on page 7.
The mode register is programmed via the MODE REG-
ISTER SET command (with BA0 = 0 and BA1 = 0) and
will retain the stored information until it is pro-
grammed again or the device loses power (except for
bit A8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory, provided it is performed cor-
rectly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Vio-
lating either of these requirements will result in
unspecified operation.

Mode register bits A0A2 specify the burst length,

A3 specifies the type of burst (sequential or inter-
leaved), A4A6 specify the CAS latency, and A7A11
(for the 128MB module) or A7A12 (for the 256MB
module) specify the operating mode.

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.

The ordering of accesses within a burst is deter-

mined by the burst length, the burst type and the start-
ing column address, as shown in Table 6, Burst
Definition Table, on page 8.

Burst Length

Read and write accesses to the DDR SDRAM are

burst oriented, with the burst length being program-
mable, as shown in Mode Register Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations
are available for both the sequential and the inter-
leaved burst types.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may
result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1A9 when the burst length is set to two,
by A2A9 when the burst length is set to four and by
A3A9 when the burst length is set to eight. The
remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. The
programmed burst length applies to both read and
write bursts.

Read Latency

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 5,
CAS Latency Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table
Table 7:, CAS Latency (CL) Table, indicates the operat-
ing frequencies at which each CAS latency setting can
be used.

Reserved states should not be used as unknown

operation or incompatibility with future versions may
result.

Operating Mode

The normal operating mode is selected by issuing a

MODE REGISTER SET command with bits A7

A11 (for

the 128MB module), or A7

A12 (for the 256MB mod-

ule) each set to zero, and bits A0

A6 set to the desired

values.

Figure 4: Mode Register Definition

Diagram

M3 = 0

Reserved

M3 = 1

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

Valid

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

2.5

Reserved

Burst Length

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

M6-M0

M8 M7

Operating Mode

A10

A12 A11

BA0

BA1

* M14 and M13 (BA0 and BA1)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

M10

M12 M11

Burst Length

CAS Latency BT

A7 A6 A5 A4 A3

A2 A1 A0

Mode Register (Mx)

Address Bus

Operating Mode

A10

A11

BA0

BA1

* M13 and M12 (BA0 and BA1)

must be "0, 0" to select the

base mode register (vs. the

extended mode register).

128MB Module

256MB Module

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

NOTE:

1. For a burst length of two, A1A9 select the two-data-

element block; A0 selects the first access within the
block.

2. For a burst length of four, A2A9 select the four-data-

element block; A0A1 select the first access within the
block.

3. For a burst length of eight, A3A9 select the eight-data-

element block; A0A2 select the first access within the
block.

4. Whenever a boundary of the block is reached within a

given sequence above, the following access wraps
within the block.

Figure 5: CAS Latency Diagram

A DLL reset is initiated by issuing a MODE REGIS-

TER SET command with bits A7 and A9

A11 (for

128MB module), or A7 and A9

A12 (for 256MB mod-

ule) each set to zero, bit A8 set to one, and bits A0

set to the desired values.

Although not required by the Micron device, JEDEC

specifications recommend when a LOAD MODE REG-
ISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER com-
mand to select normal operating mode.

All other combinations of values for A7

A11, or A7

A12, are reserved for future use and/or test modes.
Test modes and reserved states should not be used
because unknown operation or incompatibility with
future versions may result.

Table 6:

Burst Definition Table

BURST

LENGTH

STARTING

COLUMN

ADDRESS

ORDER OF ACCESSES WITHIN

A BURST

TYPE =

SEQUENTIAL

TYPE =

INTERLEAVED

0-1

1-0

A1 A0

0-1-2-3

1-2-3-0

1-0-3-2

2-3-0-1

3-0-1-2

3-2-1-0

A1 A0

0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7

1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6

2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5

3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4

4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3

5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2

6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1

7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0

Table 7:

CAS Latency (CL) Table

ALLOWABLE OPERATING

CLOCK FREQUENCY (MHZ)

SPEED

CL = 2

CL = 2.5

CL = 3

-40B

£ f £ 133

£ f £ 167 125 £ f £ 200

CK#

COMMAND

DQS

CL = 2

READ

NOP

READ

NOP

Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ

CK#

COMMAND

DQS

CL = 2.5

T2n

T3n

T2n

T3n

DON'T CARE

TRANSITIONING DATA

CK#

COMMAND

DQS

CL = 3

READ

NOP

T2n

T3n

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Extended Mode Register

The extended mode register controls functions

beyond those controlled by the mode register; these
additional functions are DLL enable/disable and out-
put drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram. The extended mode register is
programmed via the LOAD MODE REGISTER com-
mand to the mode register (with BA0 = 1 and BA1 = 0)
and will retain the stored information until it is pro-
grammed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode regis-
ter (BA0/BA1 both low) to reset the DLL.

The extended mode register must be loaded when

all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified oper-
ation.

DLL Enable/Disable

The DLL must be enabled for normal operation.

DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evalua-
tion. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is enabled,
200 clock cycles must occur before a READ command
can be issued.

Figure 6: Extended Mode Register

Definition Diagram

NOTE:

1. E13 and E12 (128MB module), or E14 and E13 (256MB

Module) (BA1 and BA0) must be "0, 1" to select the
Extended Mode Register (vs. the base Mode Register).

2. The QFC# option is not supported.

Operating Mode

Reserved

Valid

DLL

Enable

Disable

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Drive Strength

Normal

E1,

Operating Mode

A10

A11

A12

BA1 BA0

E6 E5

E10

E11

E12

DLL

A7 A6 A5 A4 A3

A2 A1 A0

Extended Mode
Register (Ex)

Address Bus

Operating Mode

A10

A11

BA1 BA0

128MB Module

256MB Module

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Commands

The Truth Tables below provide a general reference

of available commands. For a more detailed descrip-

tion of commands and operations, refer to the 128Mb
and 256Mb DDR SDRAM data sheets.

NOTE:

1. DESELECT and NOP are functionally interchangeable.
2. BA0BA1 provide device bank address and A0A11 (128MB) or A0A12 (256MB) provide device row address.
3. BA0BA1 provide device bank address; A0A9 provide device column address; A10 HIGH enables the auto precharge fea-

ture (nonpersistent), and A10 LOW disables the auto precharge feature.

4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read

bursts with auto precharge enabled and for write bursts.

5. A10 LOW: BA0BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0

BA1 are "Don't Care."

6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are "Don't Care" except for CKE.
8. BA0BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0

= 1, BA1 = 0 select extended mode register; other combinations of BA0BA1 are reserved). A0A11 (for 128MB module)
or A0A12 (for 256MB module) provide the op-code to be written to the selected mode register.

Table 8:

Truth Table Commands

CKE is HIGH for all commands shown except SELF REFRESH

NAME (FUNCTION)

CS#

RAS#

CAS#

WE#

ADDR

NOTES

DESELECT (NOP)

NO OPERATION (NOP)

ACTIVE (Select bank and activate row)

Bank/Row

READ (Select bank and column, and start READ burst)

Bank/Col

WRITE (Select bank and column, and start WRITE burst)

Bank/Col

BURST TERMINATE

PRECHARGE (Deactivate row in bank or banks)

Code

AUTO REFRESH or SELF REFRESH (Enter self refresh mode)

6, 7

LOAD MODE REGISTER

Op-Code

Table 9:

Truth Table DM Operation

Used to mask write data; provided coincident with the corresponding data

NAME (FUNCTION)

WRITE Enable

Valid

WRITE Inhibit

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-

tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.

Voltage on V

Supply

Relative to V

-1V to +3.6V

Voltage on V

Q Supply

Relative to V

-1V to +3.6V

Voltage on V

REF

and Inputs

Relative to V

-1V to +3.6V

Voltage on I/O Pins

Relative to V

-0.5V to V

Q +0.5V

Operating Temperature

(ambient)0

°C to +70°C

Storage Temperature (plastic) . . . . . .-55

°C to +150°C

Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 8W
Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA

Table 10: DC Electrical Characteristics and Operating Conditions

Notes: 15, 14; notes appear on pages 1618; 0

£ T

£ +70

C; V

= V

Q = +2.6V ±0.1V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Supply Voltage

2.5

2.7

32, 36, 47

I/O Supply Voltage

2.5

2.7

32, 36, 39,

I/O Reference Voltage

REF

0.49 x V

Q 0.51 x V

6, 39

I/O Termination Voltage (system)

REF

- 0.04

REF

+ 0.04

7, 39

Input High (Logic 1) Voltage

(

)

REF

+ 0.15

+ 0.3

Input Low (Logic 0) Voltage

(

)

-0.3

REF

- 0.15

INPUT LEAKAGE CURRENT
Any Input 0

£ V

, V

REF

Pin 0

£ V

£ 1.35V

(All other pins not under test = 0V)

Command/
Address, S#, CKE

-16

µA

CK1, CK1#, CK2,
CK2#

-6

CK0, CK0#

-4

-2

OUTPUT LEAKAGE CURRENT
(DQs are disabled; 0V

£ V

OUT

£ V

DQ, DQS

-5

µA

OUTPUT LEVELS:
High Current (V

OUT

= V

Q-0.373V, minimum V

REF

, minimum V

)

Low Current (V

OUT

= 0.373V, maximum V

REF

, maximum V

)

-16.8

33, 34

16.8

Table 11: AC Input Operating Conditions

Notes: 15, 14; notes appear on pages 1618; 0

£ T

£ +70

C; V

= V

Q = +2.6V ±0.1V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

)

REF

+ 0.310

12, 25, 35

Input Low (Logic 0) Voltage

(

)

REF

- 0.310

12, 25, 35

I/O Reference Voltage

REF

(

)

0.49 x V

0.51 x V

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Table 12: I

Specifications and Conditions (128MB)

DDR SDRAM components only
Notes: 15, 8, 10, 12; notes appear on pages 1618; 0

£ T

£ +70

C; V

= V

Q = +2.6V ±0.1V

MAX

PARAMETER/CONDITION

SYM

-40B

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;

Address and control inputs changing once every two clock cycles

DD0

920

20, 41

OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address and control inputs

changing once per clock cycle

DD1

1,080

20, 41

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;

Power-down mode;

CK =

CK (MIN); CKE = LOW

DD2P

21, 28, 43

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK (MIN); CKE = HIGH; Address and other control inputs changing

once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

400

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;

Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

200

21, 28, 43

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-

Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle; Address and other control inputs changing
once per clock cycle

DD3N

400

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank
active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); I

OUT

= 0mA

DD4R

1,080

20, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;

CK =

CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

1,240

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

1,920

RC = 15.625µs

DD5A

24, 43

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with

auto precharge,

RC = minimum

RC allowed;

CK =

CK (MIN); Address and

control inputs change only during Active, READ, or WRITE commands

DD7

2,840

20, 42

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Table 13: I

Specifications and Conditions (256MB)

DDR SDRAM components only
Notes: 15, 8, 10, 12; notes appear on pages 1618; 0

£ T

£ +70

C; V

= V

Q = +2.6V ±0.1V

MAX

PARAMETER/CONDITION

SYM

-40B

UNITS

NOTES

OPERATING CURRENT: One device bank; Active-Precharge;

RC =

RC (MIN);

CK =

CK (MIN); DQ, DM, and DQS inputs changing once per clock cycle;

Address and control inputs changing once every two clock cycles

DD0

1,080

20, 41

OPERATING CURRENT: One device bank; Active-Read-Pre-charge; Burst = 4;

RC =

RC (MIN);

CK =

CK (MIN); I

OUT

= 0mA; Address and control inputs

changing once per clock cycle

DD1

1,360

mA 20,

PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;

Power-down mode;

CK =

CK (MIN); CKE = LOW

DD2P

21, 28, 43

IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle;

CK =

CK (MIN); CKE = HIGH; Address and other control inputs changing

once per clock cycle. V

= V

REF

for DQ, DQS, and DM

DD2F

480

ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;

Power-down mode;

CK =

CK (MIN); CKE = LOW

DD3P

320

21, 28, 43

ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-

Precharge;

RC =

RAS (MAX);

CK =

CK (MIN); DQ, DM, and DQS inputs

changing twice per clock cycle; Address and other control inputs changing
once per clock cycle

DD3N

560

OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device bank

active; Address and control inputs changing once per clock cycle;

CK =

(MIN); I

OUT

= 0mA

DD4R

1,600

20, 41

OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device

bank active; Address and control inputs changing once per clock cycle;

CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle

DD4W

1,480

AUTO REFRESH CURRENT

RC =

RFC (MIN)

DD5

2,080

20, 43

RC = 15.625µs

DD5A

24, 43

SELF REFRESH CURRENT: CKE

£ 0.2V

DD6

OPERATING CURRENT: Four device bank interleaving READs (BL= 4) with

auto precharge,

RC = minimum

RC allowed;

CK =

CK (MIN); Address and

control inputs change only during Active, READ, or WRITE commands

DD7

3,760

20, 42

Table 14: Capacitance

Note: 11; notes appear on pages 1618

PARAMETER

SYMBOL

MIN

MAX

UNITS

Input/Output Capacitance: DQ, DQS

4.0

5.0

Input Capacitance: Command and Address, S#

16.0

24.0

Input Capacitance: CK0, CK0#

10.0

12.0

Input Capacitance: CK1, CK1#; CK2, CK2#

10.5

13.5

Input Capacitance: CKE

16.0

24.0

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Table 15: DDR SDRAM Component Electrical Characteristics and

Recommended AC Operating Conditions

Notes: 15, 8, 1215, 29, 31; notes appear on pages 1618; 0°C

£ T

£ +70°C; V

= V

Q = +2.6V ±0.1V

AC CHARACTERISTICS

-40B

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

Access window of DQs from CK/CK#

-0.7

+0.7

CK high-level width

0.45

0.55

CK low-level width

0.45

0.55

Clock cycle time

CL= 3

CK (3)

7.5

41, 46

CL= 2.5

CK (2.5)

41, 46

CL= 2

CK (2)

7.5

41, 46

DQ and DM input hold time relative to DQS

0.4

23, 27

DQ and DM input setup time relative to DQS

0.4

23, 27

DQ and DM input pulse width (for each input)

DIPW

1.75

Access window of DQS from CK/CK#

DQSCK

-0.6

+0.6

DQS input high pulse width

DQSH

0.35

DQS input low pulse width

DQSL

0.35

DQS-DQ skew, DQS to last DQ valid, per group, per access

DQSQ

0.40

22, 23

Write command to first DQS latching transition

DQSS

0.72

1.28

DQS falling edge to CK rising - setup time

DSS

0.2

DQS falling edge from CK rising - hold time

DSH

0.2

Half clock period

CH,

Data-out high-impedance window from CK/CK#

+0.70

16, 38

Data-out low-impedance window from CK/CK#

-0.70

16, 39

Address and control input hold time (1 V/ns)

0.6

Address and control input setup time (1 V/ns)

0.6

Address and control input hold time (0.5 V/ns)

0.6

Address and control input setup time (0.5 V/ns)

0.6

LOAD MODE REGISTER command cycle time

MRD

DQ-DQS hold, DQS to first DQ to go non-valid, per access

HP -

QHS

22, 23

Data hold skew factor

QHS

0.50

ACTIVE to PRECHARGE command

RAS

70,000

ACTIVE to READ with Auto precharge command

RAP

ACTIVE to ACTIVE/AUTO REFRESH command period

AUTO REFRESH command period

RFC

ACTIVE to READ or WRITE delay

RCD

PRECHARGE command period

DQS read preamble

RPRE

0.9

1.1

DQS read postamble

RPST

0.4

0.6

ACTIVE bank a to ACTIVE bank b command

RRD

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DQS write preamble

WPRE

0.25

DQS write preamble setup time

WPRES

18, 19

DQS write postamble

WPST

0.4

0.6

Write recovery time

Internal WRITE to READ command delay

WTR

Data valid output window

QH -

DQSQ

REFRESH to REFRESH command interval

128MB

REFC

140.6

µs

256MB

REFC

70.3

µs

Average periodic refresh interval

128MB

REFI

15.6

µs

256MB

REFI

7.8

µs

Terminating voltage delay to V

VTD

Exit SELF REFRESH to non-READ command

XSNR

Exit SELF REFRESH to READ command

XSRD

200

Table 15: DDR SDRAM Component Electrical Characteristics and

Recommended AC Operating Conditions (Continued)

Notes: 15, 8, 1215, 29, 31; notes appear on pages 1618; 0°C

£ T

£ +70°C; V

= V

Q = +2.6V ±0.1V

AC CHARACTERISTICS

-40B

PARAMETER

SYMBOL

MIN

MAX

UNITS

NOTES

128MB, 256MB (x64), PC3200

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DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

Notes

1. All voltages referenced to V

2. Tests for AC timing, Idd, and electrical AC and DC

characteristics may be conducted at nominal ref-
erence/supply voltage levels, but the related spec-
ifications and device operation are guaranteed for
the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC timing and I

tests may use a V

-to-V

swing of up to 1.5V in the test environment, but
input timing is still referenced to Vref (or to the
crossing point for CK/CK#), and parameter speci-
fications are guaranteed for the specified AC input
levels under normal use conditions. The mini-
mum slew rate for the input signals used to test
the device is 1V/ns in the range between V

(

)

and V

(

5. The AC and DC input level specifications are as

defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).

6. V

REF

is expected to equal VddQ/2 of the transmit-

ting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on

Vref

may not exceed ±2 percent of the

DC value. Thus, from V

Q/2, V

REF

is allowed

±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest V

REF

bypass capacitor.

7. V

is not applied directly to the device. V

is a

system supply for signal termination resistors, is
expected to be set equal to V

REF

and must track

variations in the DC level of V

REF

8. I

is dependent on output loading and cycle

rates. Specified values are obtained with mini-
mum cycle time at CL = 3 for -40B with the out-
puts open.

9. Enables on-chip refresh and address counters.

10. I

specifications are tested after the device is

properly initialized, and is averaged at the defined
cycle rate.

11. This parameter is sampled. V

= +2.6V ±0.1V,

Q = +2.6V ±0.1V, V

REF

= Vss, f = 200 MHz, T

25°C, V

OUT

(

) = V

Q/2, V

OUT

(peak to peak) =

0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.

12. Slew rates less than 0.5V/ ns are not allowed. If the

slew rate exceeds 4.5V/ns, functionality is uncertain.

13. The CK/CK# input reference level (for timing ref-

erenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is V

REF

14. Inputs are not recognized as valid until V

REF

stabi-

lizes. Exception: during the period before Vref sta-
bilizes, CKE

£ 0.3 x V

Q is recognized as LOW.

15. The output timing reference level, as measured at the

timing reference point indicated in Note 3, is V

16.

HZ and

LZ transitions occur in the same access

time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).

17. If DQS transitions to HIGH above V

(DC) MIN,

then it must not transition to LOW below V

(DC)

MIN prior to

DQSH (MIN).

18. This is not a device limit. The device will operate

with a negative value, but system performance
could be degraded due to bus turnaround.

19. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,

depending on

DQSS.

20. MIN (

RC or

RFC) for I

measurements is the

smallest multiple of

CK that meets the minimum

absolute value for the respective parameter.

RAS

(MAX) for I

measurements is the largest multi-

ple of

CK that meets the maximum absolute

value for

RAS.

21. The refresh period 64ms. This equates to an aver-

age refresh rate of 15.625µs (128MB modules), or
7.821µs (256MB modules). However, an AUTO
REFRESH command must be asserted at least
once every 140.6µs (128MB modules) or 70.3µs
(256MB modules); burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.

22. The valid data window is derived by achieving

other specifications:

HP (

CK/2),

DQSQ, and

(

QH =

HP -

QHS). The data valid window derates

in direct proportion to the clock duty cycle and a

Output
(V

OUT

)

Reference

Point

30pF

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

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DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation
of 45/55. Functionality is uncertain when operat-
ing beyond a 45/55 ratio.

23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not

result in a fail value. CKE is HIGH during

REFRESH command period (

RFC [MIN]) else

CKE is LOW (i.e., during standby).

25. To maintain a valid level, the transitioning edge of

the input must:
a) Sustain a constant slew rate from the current

AC level through to the target AC level, V

(

)

or V

(

b) Reach at least the target AC level.
c) After the AC target level is reached, continue

to maintain at least the target DC level, V

(

)

or V

(

26. JEDEC specifies CK and CK# input slew rate must

£ 1V/ns (2V/ns differentially).

27. DQ and DM input slew rates must not deviate

from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate less than 0.5V/ns is not
allowed. If slew rate exceeds 4V/ns, functionality
is uncertain.

28. V

must not vary more than 4 percent if CKE is

not active while any bank is active.

29. The clock is allowed up to ±150ps of jitter. Each

timing parameter is allowed to vary by the same
amount.

30.

HP min is the lesser of

CL minimum and

minimum actually applied to the device CK and
CK/ inputs, collectively during bank active.

31. READs and WRITEs with auto precharge are not

allowed to be issued until

RAS(min) can be satis-

fied prior to the internal precharge command
being issued.

32. Any positive glitch in the nominal voltage must be

less than 1/3 of the clock and not more than
+400mV or 2.9V, whichever is less. Any negative
glitch must be less than 1/3 of the clock cycle and
not exceed either -300mV or 2.4V, whichever is
more positive. However, the DC average cannot be
below +2.5V minimum.

33. Normal Output Drive Curves:

a) The full variation in driver pull-down current

from minimum to maximum process, tempera-
ture and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7, Pull-
Down Characteristics.

b) The variation in driver pull-down current

within nominal limits of voltage and tempera-
ture is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 7, Pull-Down Characteristics.

c) The full variation in driver pull-up current from

minimum to maximum process, temperature
and voltage will lie within the outer bounding
lines of the V-I curve of Figure 8, Pull-Up Char-
acteristics.

d) The variation in driver pull-up current within

nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure
8, Pull-Up Characteristics.

e) The full variation in the ratio of the maximum

to minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.

f ) The full variation in the ratio of the nominal

pull-up to pull-down current should be unity
±10 percent, for device drain-to-source volt-
ages from 0.1V to 1.0V.

Figure 7: Pull-Down Characteristics

Figure 8: Pull-Up Characteristics

160

140

OUT

(mA)

OUT

(V)

Nominal low

Minimum

Nominal high

Maximum

120

100

0.0

0.5

1.0

1.5

2.0

2.5

OUT

(V)

-20

OUT

(mA)

Nominal low

Minimum

Nominal high

Maximum

-40

-60

-80

-100

-120

-140

-160

-180

-200

0.0

0.5

1.0

1.5

2.0

2.5

Q - V

OUT

(V)

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

34. The voltage levels used are derived from a mini-

mum Vdd level and the referenced test load. In
practice, the voltage levels obtained from a prop-
erly terminated bus will provide significantly dif-
ferent voltage values.

35. VIH overshoot: V

(

MAX

) = V

Q + 1.5V for a

pulse width

£ 3ns and the pulse width can not be

greater than 1/3 of the cycle rate. V

undershoot:

(

MIN

) = -1.5V for a pulse width

£ 3ns and the

pulse width can not be greater than 1/3 of the
cycle rate.

36. V

and V

Q must track each other.

37. This maximum value is derived from the refer-

enced test load. In practice, the values obtained
in a typical terminated design may reflect up to
310ps less for

HZ (MAX) and the last DVW.

(MAX) will prevail over

DQSCK MAX) +

RPST

(MAX) condition.

LZ(MIN) will prevail over

DQSCK (MIN) +

RPRE (MAX) condition.

38. For slew rates greater than 1V/ns the (LZ) transi-

tion will start about 310ps earlier.

39. During initialization, V

Q, V

, and Vref must be

equal to or less than V

+ 0.3V. Alternatively, V

may be 1.35V maximum during power up, even if
V

Q are 0V, provided a minimum of 42

W of

series resistance is used between the V

supply

and the input pin.

40. The current Micron part operates below the slow-

est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.

41. Random addressing changing and 50 percent of

data changing at every transfer.

42. Random addressing changing and 100 percent of

data changing at every transfer.

43. CKE must be active (high) during the entire time a

refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until

REF later.

44. I

specifies the DQ, DQS, and DM to be driven

to a valid high or low logic level. IDD2Q is similar
to I

except I

specifies the address and

control inputs to remain stable. Although I

, and I

are similar, I

is "worst

case."

45. Whenever the operating frequency is altered, not

including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.

46. Leakage number reflects the worst case leakage

possible through the module pin, not what each
memory device contributes.

47. This is the DC voltage supplied at the DRAM and

is inclusive of all noise up to 20 MHz. Any noise
above 20MHz at the DRAM generated from any
source other than the DRAM istelf may not exceed
the DC voltage range of +2.6V ±0.1V.

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

SPD Clock and Data Conventions

Data states on the SDA line can change only during

SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 9, Data Validity, and Figure 10, Defini-
tion of Start and Stop).

SPD Start Condition

All commands are preceded by the start condition,

which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.

SPD Stop Condition

All communications are terminated by a stop condi-

tion, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.

SPD Acknowledge

Acknowledge is a software convention used to indi-

cate successful data transfers. The transmitting device,
either master or slave, will release the bus after trans-
mitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Fig-
ure 11, Acknowledge Response From Receiver).

The SPD device will always respond with an

acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE oper-
ation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subse-
quent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowl-
edge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will termi-
nate further data transmissions and await the stop
condition to return to standby power mode.

Figure 9: Data Validity

Figure 10: Definition of Start and Stop

Figure 11: Acknowledge Response From Receiver

SCL

SDA

DATA STABLE

DATA
CHANGE

SCL

SDA

START
BIT

STOP
BIT

SCL from Master

Data Output
from Transmitter

Data Output
from Receiver

Acknowledge

128MB, 256MB (x64), PC3200

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

Figure 12: SPD EEPROM Timing Diagram

Table 16: EEPROM Device Select Code

Most significant bit (b7) is sent first

SELECT CODE

DEVICE TYPE IDENTIFIER

CHIP ENABLE

Memory Area Select Code (two arrays)

SA2

SA1

SA0

Protection Register Select Code

SA2

SA1

SA0

Table 17: EEPROM Operating Modes

MODE

RW BIT

BYTES

INITIAL SEQUENCE

Current Address Read

or V

START, Device Select, RW = "1"

Random Address Read

or V

START, Device Select, RW = "0", Address

or V

reSTART, Device Select, RW = "1"

Sequential Read

or V

³ 1

Similar to Current or Random Address Read

Byte Write

START, Device Select, RW = "0"

Page Write

£ 16

START, Device Select, RW = "0"

SCL

SDA IN

SDA OUT

tLOW

tSU:STA

tHD:STA

tHIGH

tBUF

tDH

tAA

tSU:STO

tSU:DAT

tHD:DAT

UNDEFINED

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NOTE:

1. To aviod spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of

SDA.

2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.

4. The SPD EEPROM WRITE cycle time (

WRC) is the time from a valid stop condition of a write sequence to the end of the

EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains
HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.

Table 18: Serial Presence-Detect EEPROM DC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V to +3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

SUPPLY VOLTAGE

DDSPD

2.3

3.6

INPUT HIGH VOLTAGE: Logic 1; All inputs

DDSPD

´ 0.7 V

DDSPD

+ 0.5

INPUT LOW VOLTAGE: Logic 0; All inputs

-1

DDSPD

´ 0.3

OUTPUT LOW VOLTAGE: I

OUT

= 3mA

0.4

INPUT LEAKAGE CURRENT: V

= GND to V

µA

OUTPUT LEAKAGE CURRENT: V

OUT

= GND to V

µA

STANDBY CURRENT: SCL = SDA = V

- 0.3V; All other inputs = V

or V

µA

POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz

Table 19: Serial Presence-Detect EEPROM AC Operating Conditions

All voltages referenced to V

; V

DDSPD

= +2.3V

+3.6V

PARAMETER/CONDITION

SYMBOL

MIN

MAX

UNITS

NOTES

SCL LOW to SDA data-out valid

0.2

0.9

µs

Time the bus must be free before a new transition can start

BUF

1.3

µs

Data-out hold time

200

SDA and SCL fall time

300

Data-in hold time

HD:DAT

µs

Start condition hold time

HD:STA

0.6

µs

Clock HIGH period

HIGH

0.6

µs

Noise suppression time constant at SCL, SDA inputs

Clock LOW period

LOW

1.3

µs

SDA and SCL rise time

0.3

µs

SCL clock frequency

SCL

400

KHz

Data-in setup time

SU:DAT

100

Start condition setup time

SU:STA

0.6

µs

Stop condition setup time

SU:STO

0.6

µs

WRITE cycle time

WRC

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Table 20: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY(VERSION)

MT8VDDT1664A

MT8VDDT3264A

Number of SPD Bytes Used by Micron

128

Total Number of Bytes in SPD Device

256

Fundamental Memory Type

SDRAM DDR

Number of Row Addresses on Assembly

12, 13

Number of Column Addresses on Assembly

Number of Physical Ranks on DIMM

Module Data Width

Module Data Width (Continued)

Module Voltage Interface Levels

SSTL 2.5V

SDRAM Cycle Time, (

CK)

(CAS Latency = 3)

5ns (-40B)

SDRAM Access From Clock,(

AC)

(CAS Latency = 3)

0.7ns (-40B)

Module Configuration Type

None

Refresh Rate/Type

15.62µs, 7.8µs/SELF

SDRAM Device Width (Primary DDR SDRAM)

Error-Checking DDR SDRAM Data Width

None

Minimum Clock Delay, Back-to-Back Random
Column Access

1 clock

Burst Lengths Supported

2, 4, 8

Number of Banks on DDR SDRAM Device

CAS Latencies Supported

3, 2.5, 2

CS Latency

WE Latency

SDRAM Module Attributes

Unbuffered/Diff.

Clock

SDRAM Device Attributes: General

Fast/Concurrent AP

SDRAM Cycle Time, (

CK)

CAS Latency = 2.5

6ns (for PC2700

system compatibility)

SDRAM Access From CK, (

AC)

CAS Latency = 2.5

0.7ns (for PC 2700

system compatibility)

SDRAM Cycle Time, (

CK)

CAS Latency =2

7.5ns (for PC 2100

and PC 1600 system

compatibility)

SDRAM Access From CK , (

AC)

CAS Latency = 2

0.75ns (for PC 2100

and PC 1600 system

compatibility)

Minimum Row Precharge Time, (

RP)

15ns (-40B)

Minimum Row Active to Row Active, (

RRD)

10ns (-40B)

Minimum Ras# to CAS# Delay, (

RCD)

15ns (-40B)

Minimum RAS# Pulse Width, (

RAS)

40ns (-40B)

Module Rank Density

128MB, 256MB

Address and Command Setup Time, (

IS)

0.6ns (-40B)

Address and Command Hold Time, (

IH)

0.6ns (-40B)

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

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Data/Data Mask Input Setup Time, (

DS)

0.4ns (-40B)

Data/Data Mask Input Hold Time, (

DH)

0.4ns (-40B)

36-40

Reserved

Min Active Auto Refresh Time (

RC)

55ns (-40B)

Minimum Auto Refresh to Active/ Auto Refresh

Command Period, (

RFC)

70ns (-40B)

SDRAM Device Max Cycle Time (

MAX

)

12ns (-40B)

SDRAM Device Max DQS-DQ Skew Time (

DQSQ)

0.4ns (-40B)

SDRAM Device Max Read Data Hold Skew Factor

(

QHS)

0.5ns (-40B)

Reserved

DIMM Height

4861

Reserved

SPD Revision

Release 1.1

Checksum For Bytes 0-62

-40B

Manufacturer's JEDEC ID Code

MICRON

65-71

Manufacturer's JEDEC ID Code

(Continued)

Manufacturing Location

0112

010C

73-90

Module Part Number (ASCII)

Variable Data

PCB Identification Code

1-9

01-09

Identification Code (Continued)

Year of Manufacture in BCD

Variable Data

Week of Manufacture in BCD

Variable Data

95-98

Module Serial Number

Variable Data

99-127

Manufacturer-specific Data (RSVD)

Table 20: Serial Presence-Detect Matrix

"1"/"0": Serial Data, "driven to HIGH"/"driven to LOW"

BYTE

DESCRIPTION

ENTRY(VERSION)

MT8VDDT1664A

MT8VDDT3264A

128MB, 256MB (x64), PC3200

184-PIN DDR SDRAM DIMM

09005aef80867a99

Micron Technology, Inc., reserves the right to change products or specifications without notice..

DDA8C16_32x64AG_C.fm - Rev. C 8/03 EN

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

All other trademarks are the property of their respective owners.

Figure 13: 184-Pin DIMM Dimensions

NOTE:

All dimensions in inches (millimeters) with

or typical where noted.

Data Sheet Designation

Released (No Mark): This data sheet contains mini-

mum and maximum limits specified over the complete
power supply and temperature range for production

devices. Although considered final, these specifica-
tions are subject to change, as further product devel-
opment and data characterization sometimes occur.

No Components This Side of Module

U10

1.255 (31.88)
1.245 (31.62)

PIN 1

0.700 (17.78)

TYP.

0.098 (2.50) D

(2X)

0.091 (2.30) TYP.

0.250 (6.35) TYP.

4.750 (120.65)

0.050 (1.27)

TYP.

0.091 (2.30)

TYP.

0.040 (1.02)

TYP.

0.079 (2.00) R

(4X)

0.035 (0.90) R

PIN 92

FRONT VIEW

BACK VIEW

0.054 (1.37)
0.046 (1.17)

5.256 (133.50)
5.244 (133.20)

2.55 (64.77)

1.95 (49.53)

PIN 184

PIN 93

0.150 (3.80)

TYP.

0.394 (10.00)

TYP.

0.125 (3.18)

MAX

MIN

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