CDC1631F-E
ADVANCE INFORMATION
2
June 11, 2003; 6251-617-1AI
Micronas
Contents
Page
Section
Title
3
1.
Introduction
3
1.1.
Features
7
1.2.
Abbreviations
9
2.
Package and Pins
9
2.1.
Package Outline Dimensions
10
2.2.
Pin Assignment
11
2.3.
External Components
12
3.
Electrical Characteristics
12
3.1.
Absolute Maximum Ratings
13
3.2.
Recommended Operating Conditions
14
3.3.
Characteristics differing from Characteristics described in document "CDC16xxF-E Auto-
motive Controller Family User Manual"
15
3.4.
Recommended Crystal Characteristics
16
4.
CPU, RAM, ROM and Banking
17
5.
Core Logic
17
5.1.
Control Register CR
18
6.
Hardware Options
18
6.1.
Functional Description
20
7.
Data Sheet History
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1. Introduction
The IC is a single-chip controller for use in automotive applications. The CPU on the chip is an upgrade of the 65C02 with 16-bit internal data and 24-bit address
bus. The chip consists of timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver, CAN interfaces and PWM outputs.
This document provides device-specific information. General information on operating the IC can be found in the document "CDC16xxF-E Automotive Controller
Family User Manual" (6251-606-2AI).
1.1. Features
Table 11: CDC16xxF Family Feature List
This Device:
Item
CDC1605F-E
EMU
CDC1607F-E
MCM Flash
CDC1631F-E
MASK ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
Core
CPU
16-bit 65C816, featuring software compatibility with its 8-bit NMOS and CMOS 6500-series predecessors
CPU-Active Operation
Modes
FAST, SLOW and DEEP SLOW
FAST and SLOW
Power Saving Modes
(CPU Inactive)
WAKE and IDLE
-
EMI Reduction Mode
selectable in FAST mode
Oscillators
4 MHz to 12 MHz Quartz, RC
4 MHz to 12 MHz Quartz
RAM
6 KB 2 KB
6 KB 2.75 KB
4 KB
6 KB
ROM
ROMless,
external pro-
gram storage
with up to
16 MB, internal
2 KB Boot
ROM
256 KB Flash,
bottom boot
configuration,
internal 2 KB
Boot ROM
64 KB
ROMless,
external pro-
gram storage
with up to
16 MB, internal
2 KB Boot
ROM
256 KB Flash,
bottom boot
configuration,
internal 2 KB
Boot ROM
90 KB
128 KB
216 KB
Multiplier, 8 by 8 bit
-
CDC
163
1F-E
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NCE
INFORM
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T
ION
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Digital Watchdog
Central Clock Divider
Interrupt Controller
expanding NMI
16 inputs,15 priority levels
Port Interrupts including
Slope Selection
4 inputs
Port Wake-Up Inputs
including Slope / Level
Selection
10
-
Patch Module
10 ROM locations
5 ROM loca-
tions
10 ROM locations
5 ROM loca-
tions
6 ROM locations
Boot System
allows in-system downloading of
code and data into RAM via serial
link
-
allows in-system downloading of
code and data into RAM via serial
link
-
Analog
Reset/Alarm
Combined Input for Regulator Input Supervision
Clock and Supply
Supervision
10-bit ADC, charge
balance type
9 channels (5 channels selectable as digital input)
ADC Reference
VREF Pin
Comparators
P06COMP with 1/2 AVDD reference
LCD
Internal processing of all analog voltages for the LCD driver
Table 11: CDC16xxF Family Feature List, continued
This Device:
Item
CDC1605F-E
EMU
CDC1607F-E
MCM Flash
CDC1631F-E
MASK ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
A
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A
NCE
INFORMA
T
ION
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Communication
DMA
1 DMA Channel for serving the
Graphics Bus interface
-
1 DMA Channel for serving the
Graphics Bus interface
-
1 DMA Channel for serving the
Graphics Bus interface
UART
3: UART0, UART1 and UART2
1: UART0
3: UART0, UART1 and UART2
1: UART0
3: UART0, UART1 and UART2
Synchronous Serial
Peripheral Interfaces
2: SPI0 and SPI1
1: SPI0
2: SPI0 and SPI1
1: SPI0
2: SPI0 and SPI1
Full CAN modules V2.0B
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN000F)
1: CAN0 with
256-byte object
RAM
(LCAN000F)
3: CAN0, CAN1 and CAN2 with
256-byte object RAM each
(LCAN0009)
1: CAN0 with
256-byte object
RAM
(LCAN0009)
2: CAN0 and CAN1 with 256-byte
object RAM each (LCAN0009)
DIGITbus
1 master module
-
1 master module
-
1 master module
Input & Output
Universal Ports select-
able as 4:1 mux LCD
Segment/Backplane lines
or Digital I/O Ports
up to 52 I/O or 48 LCD segment lines (=192 segments),
in groups of two, configurable as I/O or LCD
Universal Port Slew Rate
HW preselectable
Stepper Motor Control
Modules with High-Cur-
rent Ports
5 Modules, 24 dI/dt controlled ports
8-bit PWM Modules
5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
3 Modules:
PWM0, PWM1,
PWM2
5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
2 Modules:
PWM0, PWM1
5 Modules: PWM0, PWM1,
PWM2, PWM3 and PWM4
Audio Module with auto-
decay
SW selectable Clock out-
puts
2
Polling/Flash Timer Out-
put
1 High-Current Port output operable in Power Saving
Mode
-
Table 11: CDC16xxF Family Feature List, continued
This Device:
Item
CDC1605F-E
EMU
CDC1607F-E
MCM Flash
CDC1631F-E
MASK ROM
CDC1605F-C
EMU
CDC1607F-C
MCM Flash
CDC1641F-C
Mask ROM
CDC1652F-C
Mask ROM
CDC1672F-C
Mask ROM
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