DDP 3310B
Display and Deflection
Processor
Edition July 9, 1999
6251-464-1AI
ADVANCE INFORMATION
MICRONAS
MICRONAS
DDP 3310B
ADVANCE INFORMATION
2
Micronas
Contents
Page
Section
Title
4
1.
Introduction
4
1.1.
Main Features
5
1.2.
System Architecture
5
1.3.
System Application
6
2.
Functional Description
6
2.1.
Display Part
6
2.1.1.
Input Interface
6
2.1.2.
Horizontal Scaler
6
2.1.3.
Luma Processing
7
2.1.4.
Dynamic Peaking
8
2.1.5.
Soft Limiter
8
2.1.6.
Chroma Input
9
2.1.7.
Chroma Interpolation
9
2.1.8.
Chroma Transient Improvement
9
2.1.9.
Inverse Matrix and Digital RGB Processing
10
2.1.10.
Picture Frame Generator
10
2.1.11.
Scan Velocity Modulation
12
2.2.
Analog Back-End
12
2.2.1.
Analog RGB Insertion
12
2.2.2.
Half-Contrast Control
13
2.2.3.
Fast-Blank Monitor
13
2.2.4.
CRT Measurement and Control
15
2.2.5.
Average Beam Current Limiter
16
2.3.
Synchronization and Deflection
16
2.3.1.
Deflection Processing
16
2.3.2.
Security Unit for H-Drive
17
2.3.3.
Soft Start/Stop of Horizontal Drive
18
2.3.4.
Horizontal Phase Adjustment
18
2.3.5.
Vertical Synchronization
18
2.3.6.
Vertical and East/West Deflection
19
2.3.7.
Vertical Zoom
19
2.3.8.
EHT Compensation
19
2.3.9.
Protection Circuitry
20
2.3.10.
Display Frequency Doubling
20
2.3.11.
General-purpose D/A Converter
20
2.3.12.
Clock and Reset
20
2.3.13.
Reset and Power-On
21
3.
Serial Interface
21
3.1.
I
2
C-Bus Interface
21
3.2.
I
2
C Control and Status Registers
22
3.3.
XDFP Control and Status Registers
34
3.3.1.
Scaler Adjustment
Contents, continued
Page
Section
Title
ADVANCE INFORMATION
DDP 3310B
Micronas
3
35
4.
Specifications
35
4.1.
Outline Dimensions
35
4.2.
Pin Connections and Short Descriptions
38
4.3.
Pin Description
41
4.4.
Pin Configuration
42
4.5.
Pin Circuits
44
4.6.
Electrical Characteristics
44
4.6.1.
Absolute Maximum Ratings
44
4.6.2.
Recommended Operating Conditions
45
4.6.3.
Recommended Crystal Characteristics
45
4.6.4.
Characteristics
45
4.6.4.1.
General Characteristics
46
4.6.4.2.
Line-locked Clock Inputs: LLC1, LLC2
46
4.6.4.3.
Luma, Chroma Inputs
47
4.6.4.4.
Reset Input, Test Input
47
4.6.4.5.
Half-Contrast Input
48
4.6.4.6.
I
2
C-Bus Interface
49
4.6.4.7.
Horizontal and Vertical Sync Inputs and Clock and Freqency Select Pins
49
4.6.4.8.
Horizontal Flyback Input
49
4.6.4.9.
FIFO Control Signals
50
4.6.4.10.
PWM Outputs
50
4.6.4.11.
Horizontal Drive Output
50
4.6.4.12.
Vertical Protection Input
51
4.6.4.13.
Horizontal Safety Input
51
4.6.4.14.
Vertical and East/West D/A Converter Output
51
4.6.4.15.
Sense A/D Converter Input
52
4.6.4.16.
Analog RGB and Fast-Blank Inputs
53
4.6.4.17.
Analog RGB Outputs, D/A Converters
56
4.6.4.18.
Scan Velocity Modulation Output
56
4.6.4.19.
DAC Reference, Beam Current Safety
57
5.
Application Circuit
60
6.
Data Sheet History
DDP 3310B
ADVANCE INFORMATION
4
Micronas
Display and Deflection Processor
1. Introduction
The DDP 3310B is a single-chip digital Display and
Deflection Processor designed for high-quality back-
end applications in 100/120-Hz TV sets with 4:3- or
16:9 picture tubes. The IC can be combined with mem-
bers of the DIGIT 3000 IC family (VPC 32xx,
TPU 3040), or it can be used with third-party products.
The IC contains the entire digital video component and
deflection processing and all analog interface compo-
nents.
1.1. Main Features
Video processing
linear horizontal scaling (0.25 ... 4)
non-linear horizontal scaling "panoramavision"
dynamic peaking
soft limiter (gamma correction)
color transient improvement
programmable RGB matrix
picture frame generator
two analog RGB/Fast-Blank inputs
Deflection processing
scan velocity modulation output
high-performance H/V deflection
EHT compensation for vertical / East/West
soft start/stop of H-Drive
vertical angle and bow
differential vertical output
vertical zoom via deflection
horizontal and vertical protection circuit
adjustable horizontal frequency for VGA/SVGA dis-
play
Miscellaneous
selectable 4:1:1/4:2:2 YC
r
C
b
input
selectable 27 /32-MHz line-locked clock input
crystal oscillator for horizontal protection
automatic picture tube adjustment (cutoff, white-
drive)
single 5-V power supply
hardware for simple 50/60-Hz to 100/120-Hz con-
version (display frequency doubling)
two I
2
C-controlled PWM outputs
beam current limiter
Fig. 11: Block diagram of the DDP 3310B
Y Features
C Features
Digital
RGB
Matrix
DACs
Display
Frequency
Doubling
Hori-
zontal
Scaler
I
2
C
Inter-
face
3 x DAC
(10 Bit)
Tube Control
Analog
RGB
Switch
Picture
Frame
Generator
Measure-
ment
ADC
RGB
Out
2xRGB/FB
In
SDA/SCL
Sense
Input
HDrive
V & E/W
YC
r
C
b
4:2:2/4:1:1
2H / 2V
FIFO
Controlling
Clock
Gen.
Line-locked
Clock
27/32 MHz
(1H/1V)
PWM
PWM
1&2
SVM
Scan
Velocity
Modulation
H / V
Deflection
Security
Unit
HFlyback
ADVANCE INFORMATION
DDP 3310B
Micronas
5
1.2. System Architecture
The DDP 3310B is a mixed-signal IC containing the
entire digital video component processing such as
chroma transient improvement (CTI), adaptive luma
peaking, and a non-linear `Panorama' aspect ratio con-
version. All deflection related signals can be adapted
to different scan rates. The analog section contains all
analog interface components and an ADC, to compen-
sate long term changes of the picture tube parameters
and extreme high-tension effects. Fig. 11 shows the
block diagram of the single-chip Display and Deflection
Processor.
1.3. System Application
Fig. 12 depicts several DDP applications. Since the
DDP functions as a video back-end, it must be comple-
mented with additional functionality to form a complete
TV set.
The VPC 32xx family processes all worldwide analog
video signals (including the European PALplus) and
allows non-linear Panorama aspect ratio conversion.
Thus, 4:3 and 16:9 systems can easily be configured
by software. The aspect ratio scaling is also used as a
sample rate converter to provide a line-locked digital
component output bus (YC
r
C
b
) compliant to ITU-R-601.
All video processing and line-locked clock/data gener-
ation is derived from a single 20.25-MHz crystal. An
optional adaptive 2H/4H comb filter (VPC 32xx) per-
forms Y/C separation for PAL and NTSC and all of their
substandards.
The VPC 32xxD and the CIP 3250A provide a high-
quality analog RGB interface with character insertion
capability. This allows appropriate processing of exter-
nal sources such as MPEG 2 set-top boxes in trans-
parent (4:2:2) quality. Furthermore, it translates RGB/
Fast-Blank signals to the common digital video bus
and makes those signals available for 100-Hz process-
ing. In some European countries (Italy), this feature is
mandatory.
The IP indicates memory-based image processing,
such as scan rate conversion, vertical processing
(Zoom), or PAL+ reconstruction.
Examples:
Europe: 15 kHz/ 50 Hz
32 kHz/100 Hz interlaced
US: 15 kHz/60 Hz
31 kHz/120 Hz non-interlaced
Note: The DDP 3310B and the VPC 32xx families
support memory-based applications through line-
locked clocks, syncs, and data. The CIP 3250A may
run either with the native DIGIT3000 clock but also
with a line-locked clock system.
Fig. 12: DDP 3310B applications
IP
Comb Filt
er
16
:
9
Vi
d
e
o
RGB S
a
tura
t
i
on
Sc
a
n
V
e
loc
i
t
y
M
odula
t
ion
F
a
st
Blan
k
Mix
i
n
g
IP
VPC
32xx
PAL+
100 Hz
CVBS
RGB
DDP
3310B
CIP
3250A
RGB
H/V
Defl.
FIFO
VPC
32xx
CVBS
DDP
3310B
RGB
H/V
Defl.
VPC 32xxD
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