Document Outline

• Twelve Port T3/E3/STS-1 Line Interface Unit
• Contents
• Figures
• Tables
• 1.0 Pin Description
  • 1.1 Pin Assignments
    • Figure 1-1. Bottom View of the M28335
    • Table 1-1. M28335 Pin Definitions (1 of 16)
  • 1.2 Logic Diagrams
    • Figure 1-2. Hardware Mode Logic Diagram
    • Figure 1-3. Bus Mode Logic Diagram
    • Figure 1-4. Serial Mode Logic Diagram
• 2.0 Functional Description
  • 2.1 Overview
    • Figure 2-1. Typical Application of Single M28335 Channel
  • 2.2 Configuration and Control
    • 2.2.1 Hardware Mode
      • Table 2-1. Pin Redefinition
      • Table 2-2. Port Configuration in Hardware Mode
    • 2.2.2 Bus Mode
    • 2.2.3 Serial Mode
      • Figure 2-2. Device Serial Port Signals
  • 2.3 Transmitter
    • 2.3.1 AMI B3ZS/HDB3 Encoder
    • 2.3.2 Pulse Shaper
      • Figure 2-3. Pulse Shaper
    • 2.3.3 Line Driver
      • Figure 2-4. Pulse Power Measurement Points
      • 2.3.3.1 Transmit Pulse Mask Templates
        • Figure 2-5. Transmit Pulse Mask for DS3 Rates
        • Table 2-3. DS3 Transmit Template Specifications
        • Figure 2-6. Transmit Pulse Mask for STS-1 Rates
        • Table 2-4. STS-1 Transmit Template Specifications
        • Figure 2-7. Transmit Pulse Mask for E3 Rate
    • 2.3.4 Alarm Indication Signal (AIS) Generator
      • Figure 2-8. AIS Signal
    • 2.3.5 Transmit Monitor Block
      • Figure 2-9. Direct Connection of Monitor Signal to Transmit Signal
    • 2.3.6 Jitter Generation (Intrinsic)
  • 2.4 Receiver
    • 2.4.1 Receive Sensitivity
      • Table 2-5. Receiver Sensitivity (Length of Cable) for DS3/E3/STS-1
    • 2.4.2 AGC/VGA Block
    • 2.4.3 Receive Equalizer
    • 2.4.4 The PLL Clock Recovery Circuit
    • 2.4.5 Loss Of Signal (LOS) Detector
      • Table 2-6. RLOS Threshold Control Bits
    • 2.4.6 B3ZS/HDB3 Decoder With Bipolar Violation Detector
    • 2.4.7 Data Squelching
  • 2.5 Jitter Tolerance
    • Figure 2-10. Minimum Jitter Tolerance Requirement
    • 2.5.1 Jitter Transfer
      • Figure 2-11. Maximum Jitter Transfer Curve Requirement
  • 2.6 Additional M28335 Functions
    • 2.6.1 Bias Generator
    • 2.6.2 External Reset
    • 2.6.3 Power-On Reset (POR)
    • 2.6.4 Interrupt
    • 2.6.5 Loopback Multiplexers (MUXes)
      • Figure 2-12. Remote Loopback Diagram
      • Figure 2-13. Local Loopback Diagram
  • 2.7 Mechanical Specifications
    • Figure 2-14. M28335 Mechanical Drawing (35 mm TBGA)�Dimensions
    • 2.7.1 Moisture Sensitivity
  • 2.8 Electrical/Thermal Characteristics
    • 2.8.1 Absolute Maximum Ratings
      • Table 2-7. Absolute Maximum Ratings
    • 2.8.2 ESD Ratings
      • Table 2-8. ESD Ratings
    • 2.8.3 Recommended Operating Conditions
      • Table 2-9. Recommended Operating Conditions
    • 2.8.4 DC Characteristics
      • Table 2-10. DC Characteristics
    • 2.8.5 DS3 Electrical Characteristics
      • Table 2-11. DS3 Receiver Characteristics
    • 2.8.6 E3 Electrical Characteristics
      • Table 2-12. E3 Receiver Characteristics
    • 2.8.7 STS-1 Electrical Characteristics
      • Table 2-13. STS-1 Receiver Characteristics
    • 2.8.8 AC Characteristics
      • Table 2-14. AC Characteristics (Logic Timing)
      • Figure 2-15. Timing Diagram
      • Table 2-15. Bus Mode Timing�Read Cycles
      • Figure 2-16. Bus Mode Read Timing
      • Table 2-16. Bus Mode Timing�Write Cycles
      • Figure 2-17. Bus Mode Write Timing
      • Table 2-17. Serial Mode Timing
      • Figure 2-18. Serial Mode Register Read (see Note below)
      • Figure 2-19. Serial Mode Register Write (see Note below)
• 3.0 Registers
  • 3.1 Address Map
    • Table 3-1. Register Address Map(1 of 2)
  • 3.2 Global Register
  • 3.3 Per Port Registers
  • 3.4 Alarm Registers
  • 3.5 Interrupt Status Registers
  • 3.6 Interrupt Enable Registers
  • 3.7 RLOS Threshold Control Registers
  • 3.8 RLOS Data Squelch Disable Registers
• 4.0 Applications
  • 4.1 Line Interface Example
    • Figure 4-1. DS3 Line Interface Example
  • 4.2 Interface Example to CX28365 in Bus Mode
    • Figure 4-2. Interface to CX28365 in Bus Mode
  • 4.3 Interface Example to CX28365 in Hardware Mode
    • Figure 4-3. Interface to CX28365 in Hardware Mode
  • 4.4 Serial Mode Interface Example
    • Figure 4-4. Serial Mode Interface Example
  • 4.5 PCB Design Considerations for the M28335
    • 4.5.1 Power Supply and Ground Plane
    • 4.5.2 Component Placement
      • 4.5.2.1 RBIAS Resistor
      • 4.5.2.2 VGG Decoupling
      • 4.5.2.3 Termination Resistors and Capacitors
        • Figure 4-5. TX/RX Terminations
    • 4.5.3 Impedance Matching
    • 4.5.4 Other Passive Parts
    • 4.5.5 IBIS Models
    • 4.5.6 Recommended Vendors
• Appendix A: Applicable Standards
• Appendix B: Power Sequencing
  • Figure B-1. Power -up sequence of VGG and VDD.
  • Figure B-2. Power-down sequence of VGG and VDD.