8-45

Description

The MT9123 Voice Echo Canceller implements a
cost effective solution for telephony voice-band echo
cancellation conforming to ITU-T G.165
requirements. The MT9123 architecture contains two
echo cancellers which can be configured to provide
dual channel 64 millisecond echo cancellation or
single channel 128 millisecond echo cancellation.

The MT9123 operates in two major modes:
Controller or Controllerless. Controller mode allows
access to an array of features for customizing the
MT9123 operation. Controllerless mode is for
applications where default register settings are
sufficient.

Features

Dual channel 64ms or single channel 128ms
echo cancellation

Conforms to ITU-T G.165 requirements

Narrow-band signal detection

Programmable double-talk detection threshold

Non-linear processor with adaptive suppression
threshold and comfort noise insertion

Offset nulling of all PCM channels

Controllerless mode or Controller mode with
serial interface

ST-BUS or variable-rate SSI PCM interfaces

Selectable

/A-Law ITU-T G.711;

/A-Law Sign

Mag; linear 2's complement

Per channel selectable 12 dB attenuator

Transparent data transfer and mute option

19.2 MHz master clock operation

Applications

Wireless Telephony

Trunk echo cancellers

Figure 1 - Functional Block Diagram

Linear/

/A-Law

Non-Linear

Processor

Offset

Null

Linear/

/A-Law

Linear/

/A-Law

Microprocessor

Interface

Double-Talk

Detector

Adaptive

Filter

Control

Narrow-Band

Detector

Linear/

/A-Law

Offset

Null

12dB

Attenuator

Echo Canceller A

Echo Canceller B

VDD

VSS

PWRDN

IC1

F0od

F0i

BCLK/C4i

MCLK

Sout

Rin
ENA1
ENB1

CONFIG1
CONFIG2
S1/DATA1
S2/DATA2
S3/CS
S4/SCLK

Sin

Rout

ENA2
ENB2

NLP

LAW

FORMAT

IC3
IC4

Programmable

Bypass

IC2

ISSUE 1

October 1996

Ordering Information

MT9123AP

28 Pin PLCC

MT9123AE

28 Pin PDIP

-40

C to + 85

MT9123

Dual Voice Echo Canceller

Preliminary Information

CMOS

MT9123

Preliminary Information

8-46

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

ENA1

SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.

For SSI, this strobe must be present for frame synchronization. This is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for Echo Canceller A
on Rin/Sout pins. Strobe period is 125 microseconds.

For ST-BUS, this pin, in conjunction with the ENB1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.

ENB1

SSI Enable Strobe / ST-BUS Mode for Rin/Sout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.

For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Rin/Sout pins. Strobe period is 125 microseconds.

For ST-BUS, this pin, in conjunction with the ENA1 pin, will select the proper ST-BUS mode for
Rin/Sout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.

ENA2

SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.

For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller A on Sin/Rout pins. Strobe period is 125 microseconds.

For ST-BUS, this pin, in conjunction with the ENB2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.

1
2
3
4
5
6
7
8
9

10
11
12
13
14

28
27
26
25
24
23
22
21

S2/DATA2

VDD
F0od

IC4

S1/DATA1

S4/SCLK

Sout

Rout

BCLK/C4i

CONFIG1

CONFIG2

Sin

Rin

NLP

VSS

ENB2

ENB1

F0i

FORMAT

IC2

LAW

ENA1

PWRDN

IC3

ENA2

MCLK

S3/CS

ENB2

ENB1

ENA1

ENA2

BCLK/

C4i

CONFIG1

CONFIG2

Sin

Rin

NLP

VSS

IC2

MCLK

FORMA

PWRDN

IC3

IC4

S4/SCLK

S3/

S2/DATA2

VDD
F0od
S1/DATA1

Sout

Rout

F0i

PLCC

5
6
7
8
9
10
11

25
24
23
22
21
20
19

PDIP

IC1

Preliminary Information

MT9123

8-47

ENB2

SSI Enable Strobe / ST-BUS Mode for Sin/Rout (Input). This pin has dual functions
depending on whether SSI or ST-BUS is selected.

For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial
PCM data transfer for Echo Canceller B on Sin/Rout pins. Strobe period is 125 microseconds.

For ST-BUS, this pin, in conjunction with the ENA2 pin, will select the proper ST-BUS mode for
Sin/Rout pins (see ST-BUS Operation description). The selected mode applies to both Echo
Canceller A and B.

Rin

Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2's complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Receive Input reference channels for Echo Cancellers
A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.

Sin

Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2's complement linear format. Two PCM channels are time-
multiplexed on this pin. These are the Send Input channels (after echo path) for Echo
Cancellers A and B. Data bits are clocked in following SSI or ST-BUS timing requirements.

VSS

Digital Ground. Nominally 0 volts.

MCLK

Master Clock (Input). Nominal 20 MHz Master Clock input. May be connected to an
asynchronous (relative to frame signal) clock source.

IC1

Internal Connection 1 (Input). Must be tied to Vss.

NLP

Non-Linear Processor Control (Input).
Controllerless Mode: An active high enables the Non-Linear Processors in Echo Cancellers A
and B. Both NLP's are disabled when low. Intended for conformance testing to G.165 and it is
usually tied to Vdd for normal operation.

Controller Mode: This pin is ignored (tie to Vdd or Vss). The non-linear processor operation is
controlled by the NLPDis bit in Control Register 2. Refer to the Register Summary.

IC2

Internal Connection 2 (Input). Must be tied to Vss.

LAW

Law Select (Input). An active low selects

µ-

Law companded PCM. When high, selects

A-Law companded PCM. This control is for both echo cancellers and is valid for both
controller and controllerless modes.

FORMAT ITU-T/Sign Mag (Input). An active low selects sign-magnitude PCM code. When high,

selects ITU-T (G.711) PCM code. This control is for both echo cancellers and is valid for both
controller and controllerless modes.

PWRDN

Power-down (Input). An active low resets the device and puts the MT9123 into a low-power
stand-by mode.

IC3

Internal Connection 3 (Output). Must be left unconnected.

IC4

Internal Connection 4 (Output). Must be left unconnected.

17/18

S4/S3

SCLK

Selection of Echo Canceller B Functional States (Input).
Controllerless Mode: Selects Echo Canceller B functional states according to Table 2.

Controller Mode: S4 and S3 pins become SCLK and CS pins respectively.

Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.

Chip Select (Input). Enables serial microport interface data transfers. Active low.

Pin Description (continued)

Pin #

Name

Description

MT9123

Preliminary Information

8-48

Notes:

1. All unused inputs should be connected to logic low or high unless otherwise stated. All outputs should be left open circuit when not used.

2. All inputs have TTL compatible logic levels except for MCLK, Sin and Rin pins which have CMOS compatible logic levels and PWRDN

pin which has Schmitt trigger compatible logic levels.

3. All outputs are CMOS pins with CMOS logic levels.

19/20

S2/S1

DATA2

DATA1

Selection of Echo Canceller A Functional States (Input).
Controllerless Mode: Selects Echo Canceller A functional states according to Table 2.

Controller Mode: S2 and S1 pins become DATA2 and DATA1 pins respectively.

Serial Data Receive (Input).
In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In
Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd.

Serial Data Port (Bidirectional).
In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In
Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data.

F0od

Delayed Frame Pulse Output (Output). In ST-BUS operation, this pin generates a delayed
frame pulse after the 4th channel time slot and is used for daisy-chaining multiple ST-BUS
devices. See Figures 5 to 8.

In SSI operation, this pin outputs logic low.

VDD

Positive Power Supply. Nominally 5 volts.

Sout

Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream. Data
may be in either companded or 2's complement linear PCM format. Two PCM channels are
time-multiplexed on this pin. These are the Send Out signals after echo cancellation and Non-
linear processing. Data bits are clocked out following SSI or ST-BUS timing requirements.

Rout

Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2's complement linear PCM format. Two PCM channels
are time-multiplexed on this pin. This output pin is provided for convenience in some
applications and may not always be required. Data bits are clocked out following SSI or ST-
BUS timing requirements.

F0i

Frame Pulse (input). In ST-BUS operation, this is a frame alignment low going pulse. SSI
operation is enabled by connecting this pin to Vss.

BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit

clock. This clock must be synchronous with ENA1, ENA2, ENB1 and ENB2 enable strobes.

In ST-BUS operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27/28 CONFIG1/

CONFIG2

Device Configuration Pins (Inputs). When CONFIG1 and CONFIG2 pins are both logic 0,
the MT9123 serial microport is enabled. This configuration is defined as Controller Mode.
When CONFIG1 and CONFIG2 pins are in any other logic combination, the MT9123 is
configured in Controllerless Mode. See Table 3.

Pin Description (continued)

Pin #

Name

Description

Preliminary Information

MT9123

8-49

Functional Description

The MT9123 architecture contains two individually
controlled echo cancellers (Echo Canceller A and B).
They can be set in three distinct configurations:
Normal, Back-to-Back and Extended Delay (see
Figure 3). Under Normal configuration, the two echo
cancellers are positioned in parallel providing 64
millisecond echo cancellation in two channels
simultaneously. In Back-to-Back configuration, the
two echo cancellers are positioned to cancel echo
coming from both directions in a single channel. In
Extended-Delay configuration, the two echo
cancellers are internally cascaded into one 128
millisecond echo canceller.

Each echo canceller contains the following main
elements (see Figure 1).

Adaptive Filter for estimating the echo channel

Subtracter for cancelling the echo

Double-Talk detector for disabling the filter
adaptation during periods of double-talk

Non-Linear Processor for suppression of
residual echo

Narrow-Band Detector for preventing Adaptive
Filter divergence caused by narrow-band
signals

Offset Null filters for removing the DC
component in PCM channels

12dB attenuator for signal attenuation

Serial controller interface compatible with
Motorola, National and Intel microcontrollers

PCM encoder/decoder compatible with

/A-

Law ITU-T G.711,

/A-Law Sign-Mag or linear

2's complement coding

The MT9123 has two modes of operation:
Controllerless and Controller. Controllerless mode is
intended for applications where customization is not
required. Controller mode allows access to all
registers for customizing the MT9123 operation.
Refer to Table 7 for a complete list. Controller mode
is selected when CONFIG1 and CONFIG2 pins are
both connected to Vss.

Each echo canceller in the MT9123 has four
functional states:

Mute, Bypass, Disable Adaptation

and

Enable Adaptation. These are explained in the

section entitled Echo Canceller Functional States.

Figure 3 - Device Configuration

Rin

Rout

Sout

Sin

echo
path A

Optional -12dB pad

PORT 2

PORT 1

echo

path B

channel A

channel B

E.C.A

E.C.B

a) Normal Configuration (64ms)

channel A

E.C.A

Sin

Sout

Rout

Rin

b) Extended Delay Configuration (128ms)

PORT 2

PORT 1

E.C.A

Sin

Sout

Rout

Rin

c) Back-to-Back Configuration (64ms)

E.C.B

echo

path

PORT 2

PORT 1

echo

path A

Adaptive

Filter (64ms)

Adaptive

Filter (64ms)

Optional -12dB pad

Adaptive

Filter (64ms)

Optional -12dB pad

Adaptive

Filter (64ms)

Optional -12dB pad

Adaptive Filter

(128 ms)

Optional -12dB pad

8-50

MT9123

Preliminary Information

Adaptive Filter

The adaptive filter is a 1024 tap FIR filter which is
divided into two sections. Each section contains 512
taps providing 64ms of echo estimation. In Normal
configuration, the first section is dedicated to
channel A and the second section to channel B. In
Extended Delay configuration, both sections are
cascaded to provide 128ms of echo estimation in
channel A.

Double-Talk Detector

Double-Talk is defined as those periods of time when
signal energy is present in both directions
simultaneously. When this happens, it is necessary
to disable the filter adaptation to prevent divergence
of the adaptive filter coefficients. Note that when
double-talk is detected, the adaptation process is
halted but the echo canceller continues to cancel
echo.

A double-talk condition exists whenever the Sin
signal level is greater than the expected return echo
level. The relative signal levels of Rin (Lrin) and Sin
(Lsin) are compared according to the following
expression to identify a double-talk condition:

Lsin > Lrin + 20log

(DTDT)

where DTDT is the Double-Talk Detection Threshold.
Lsin and Lrin are the relative signal levels expressed
in dBm0.

A different method is used when it is uncertain
whether Sin consists of a low level double-talk signal
or an echo return. During these periods, the
adaptation process is slowed down but it is not
halted.

Controllerless Mode
In G.165 standard, the echo return loss is expected
to be at least 6dB. This implies that the Double-Talk
Detector Threshold (DTDT) should be set to 0.5
(-6dB). However, in order to get additional
guardband, the DTDT is set internally to 0.5625
(-5dB). In controllerless mode, the Double-Talk
Detector is always active.

Controller Mode
In some applications the return loss can be higher or
lower than 6dB. The MT9123 allows the user to
change the detection threshold to suit each
application's need. This threshold can be set by
writing the desired threshold value into the DTDT
register.

The DTDT register is 16 bits wide. The register value
in hexadecimal can be calculated with the following
equation:

DTDT

(hex)

= hex(DTDT

(dec)

* 32768)

where 0 < DTDT

(dec)

< 1

Example:

For DTDT = 0.5625 (-5dB), the
hexadecimal value becomes

hex(

0.5625 * 32768

)

= 4800h

Non-Linear Processor (NLP)

After echo cancellation, there is always a small
amount of residual echo which may still be audible.
The MT9123 uses an NLP to remove residual echo
signals which have a level lower than the Adaptive
Suppression Threshold (TSUP in G.165). This
threshold depends upon the level of the Rin (Lrin)
reference signal as well as the programmed value of
the Non-Linear Processor Threshold register
(NLPTHR). TSUP can be calculated by the following
equation:

TSUP = Lrin + 20log

(NLPTHR)

where NLPTHR is the Non-Linear Processor
Threshold register value and Lrin is the relative
power level expressed in dBm0.

When the level of residual error signal falls below
TSUP, the NLP is activated further attenuating the
residual signal to less than -65dBm0. To prevent a
perceived decrease in background noise due to the
activation of the NLP, a spectrally-shaped comfort
noise, equivalent in power level to the background
noise, is injected. This keeps the perceived noise
level constant. Consequently, the user does not hear
the activation and de-activation of the NLP.

Controllerless Mode
The NLP processor can be disabled by connecting
the NLP pin to Vss.

Controller Mode
The NLP processor can be disabled by setting the
NLPDis bit to 1 in Control Register 2.

The NLPTHR register is 16 bits wide. The register
value in hexadecimal can be calculated with the
following equation:

Preliminary Information

MT9123

8-51

NLPTHR

(hex)

= hex(NLPTHR

(dec)

* 32768)

where 0 < NLPTHR

(dec)

< 1

The comfort noise injection can be disabled by
setting the INJDis bit to 1 in Control Register 1.

It should be noted that the NLPTHR is valid and the
comfort noise injection is active only when the NLP is
enabled.

Narrow Band Signal Detector (NBSD)

Single or dual frequency tones (e.g. DTMF tones)
present in the reference input (Rin) of the echo
canceller for a prolonged period of time may cause
the adaptive filter to diverge. The Narrow Band
Signal Detector (NBSD) is designed to prevent this
divergence by detecting single or dual tones of
arbitrary frequency, phase, and amplitude. When
narrow band signals are detected, the adaptation
process is halted but the echo canceller continues to
cancel echo.

Controllerless Mode
The NBSD is always active and automatically
disables the filter adaptation process when narrow
band signals are detected.

Controller Mode
The NBSD can be disabled by setting the NBDis bit
to 1 in Control Register 2.

Offset Null Filter

Adaptive filters in general do not operate properly
when a DC offset is present on either the reference
signal (Rin) or the echo composite signal (Sin). To
remove the DC component, the MT9123
incorporates Offset Null filters in both Rin and Sin
inputs.

Controllerless Mode
The Offset Null filters are always active.

Controller Mode
The offset null filters can be disabled by setting the
HPFDis bit to 1 in Control Register 2.

Echo Canceller Functional States

Each echo canceller has four functional states: Mute,
Bypass, Disable Adaptation and Enable Adaptation.
Mute:
The Mute state forces the echo canceller to
transmit quiet code and halts the filter adaptation
process.

In Normal configuration, the PCM output data on
Rout is replaced with the quiet code according to
the following table.

In Back-to-Back configuration, both echo cancellers
are combined to implement a full duplex echo
canceller. Therefore muting Echo Canceller A
causes quiet code to be transmitted on Rout, while
muting Echo Canceller B causes quiet code to be
transmitted on Sout.

In Extended Delay configuration, both echo
cancellers are cascaded to make one 128ms echo
canceller. In this configuration, muting Echo
Canceller A causes quiet code to be transmitted on
Rout.

Bypass:
The Bypass state directly transfers PCM codes from
Rin to Rout and from Sin to Sout. When Bypass state
is selected, the adaptive filter coefficients are reset
to zero.

Disable Adaptation:
When the Disable Adaptation state is selected, the
adaptive filter coefficients are frozen at their current
value. In this state, the adaptation process is halted
however the MT9123 continues to cancel echo.

Enable Adaptation:
In Enable Adaptation state, the adaptive filter
coefficients are continually updated. This allows
the echo canceller to model the echo return path
characteristics in order to cancel echo. This is the
normal operating state.

Controllerless Mode
The four functional states can be selected via S1,
S2, S3, and S4 pins as shown in the following table.

LINEAR

16 bits

2's

complement

SIGN/

MAGNITUDE

-Law

A-Law

CCITT (G.711)

-Law

A-Law

+Zero

(quiet code)

0000h

80h

FFh

D5h

Table 1 - Quiet PCM Code Assignment

8-52

MT9123

Preliminary Information

(1) Filter coefficients are frozen (adaptation disabled)
(2) The adaptive filter coefficients are reset to zero
(3) The MT9123 cancels echo

Table 2 - Functional States Control Pins

Controller Mode
The echo canceller functions are selected in Control
Register 1 and Control Register 2 through four
control bits: MuteS, MuteR, Bypass and AdaptDis.
See Register Summary for details.

MT9123 Throughput Delay

The throughput delay of the MT9123 varies
according to the data path and the device
configuration. For all device configurations, except
for Bypass state, Rin to Rout has a delay of two
frames and Sin to Sout has a delay of three frames.
In Bypass state, the Rin to Rout and Sin to Sout
paths have a delay of two frames. In ST-BUS
operation, the D and C channels have a delay of
one frame.

Power Down

Forcing the PWRDN pin to logic low, will put the
MT9123 into a power down state. In this state all
internal clocks are halted, the DATA1, Sout and Rout
pins are tristated and the F0od pin output high.

The device will automatically begin the execution of
its initialization routines when the PWRDN pin is
returned to logic high and a clock is applied to the
MCLK pin. The initialization routines execute for one
frame and will set the MT9123 to default register
values.

Device Configuration

Normal Configuration:
In this configuration, the two echo cancellers (Echo
Canceller A and B) are positioned in parallel, as
shown in Figure 3a, providing 64 milliseconds of
echo cancellation in two channels simultaneously.

In SSI operation, both channels are available in
different timeslots on the same TDM (Time Division
Multiplexing) bus. For Echo Canceller A, the ENA1
enable strobe pin defines the Rin/Sout (PORT1) time
slot while the ENA2 enable strobe pin defines the
Sin/Rout (PORT2) time slot. The ENB1 and ENB2
enable strobes perform the same function for Echo
Canceller B.

In ST-BUS operation, the ENA1, ENA2, ENB1 and
ENB2 pins are used to determine the PCM data
format and the channel locations. See Table 4.

Back-to-Back Configuration:
In this configuration, the two echo cancellers are
positioned to cancel echo coming from both
directions in a single channel providing full duplex 64
millisecond echo-cancellation. See Figure 3c. This
configuration uses only one timeslot on PORT1 and
PORT2, allowing a no-glue interface for applications
where bidirectional echo cancellation is required.
In SSI operation, ENA1 and ENA2 enable pins are
used to strobe data on Rin/Sout and Sin/Rout
respectively. In ST-BUS operation, ENA1, ENA2,
ENB1 and ENB2 inputs are used to select the ST-
BUS mode according to Table 4.

Examples of Back-to-Back configuration include
positioning the MT9123 between a codec and a
transmission device or between two codecs for echo
control on analog trunks.

Extended Delay configuration:
In this configuration, the two echo cancellers are
internally cascaded into one 128 millisecond echo
canceller. See Figure 3b. In SSI operation, ENA1
and ENA2 enable pins are used to strobe data on
Rin/Sout and Sin/Rout respectively. In ST-BUS
operation, ENA1, ENA2, ENB1 and ENB2 inputs are
used to select the ST-BUS mode according to Table
4.

Controllerless Mode
The three configurations can be selected through the
CONFIG1 and CONFIG2 pins as shown in the
following table.

Echo

Canceller A

S2/S1

Functional State

Echo

Canceller B

S4/S3

Mute

(1)

Bypass

(2)

Disable Adaptation

(1,3)

Enable Adaptation

(3)

Preliminary Information

MT9123

8-53

Table 3 - Configuration in Controllerless Mode

Controller Mode
In Control Register 1, the Normal configuration can
be programmed by setting both BBM and Extended-
Delay bits to 0. Back-to-Back configuration can be
programmed by setting the BBM bit to 1 and
Extended-Delay bit to 0. Extended-Delay
configuration can be programmed by setting the
Extended-Delay bit to 1 and BBM bit to 0. Both BBM
and Extended-Delay bits in Control Register 1 can
not be set to 1 at the same time.

PCM Data I/O

The PCM data transfer for the MT9123 is provided
through two PCM ports. PORT1 consists of Rin and
Sout pins while PORT2 consists of Sin and Rout Pins.
The Data is transferred through these ports
according to either ST-BUS or SSI conventions. The
device determines the mode of operation by
monitoring the signal applied to the F0i pin. When a
valid ST-BUS frame pulse is applied to the F0i pin,
the MT9123 will assume ST-BUS operation. If F0i is
tied continuously to Vss the MT9123 will assume SSI
operation.

ST-BUS Operation

The ST-BUS PCM interface conforms to Mitel's ST-
BUS standard and it is used to transport 8 bit
companded PCM data (using one timeslot) or 16 bit
2's complement linear PCM data (using two
timeslots). Pins ENA1 and ENB1 select timeslots on
PORT1 while pins ENA2 and ENB2 select timeslots
on PORT2. See Table 4 and Figures 5 to 8.

Table 4 - ST-BUS Mode Select

Note that if the device is in back-to-back or extended
delay configurations, the second timeslot in any ST-
BUS Mode contains undefined data. This means that
the following timeslots contain undefined data:
timeslot 1 in ST-BUS Mode 1; timeslot 3 in ST-BUS
Modes 2 & 3 and timeslots 2 and 3 in ST-BUS Mode
4.

SSI Operation

The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and four enable pins
(ENA1,ENB1, ENA2 and ENB2) to provide strobes
for data transfers. The active high enable may be
either 8 or 16 BCLK cycles in duration. Automatic
detection of the data type (8 bit companded or 16 bit
2's complement linear) is accomplished internally.
The data type cannot change dynamically from one
frame to the next.

In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 9). The other enable strobes (ENB1, ENA2
and ENB2) are used for parsing input/output data
and they must pulse within 125 microseconds of the
rising edge of ENA1. If they are unused, they must
be tied to Vss.

In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2's complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).

CONFIG1

CONFIG2

CONFIGURATION

(selects Controller Mode)

Extended Delay Mode

Back-to-Back Mode

Normal Mode

PORT1

Rin/Sout

ST-BUS Mode

Selection

PORT2

Sin/Rout

Enable Pins

ENB1

ENA1

ENB2

ENA2

Mode 1. 8 bit companded PCM I/O on
timeslots 0 & 1.

Mode 2. 8 bit companded PCM I/O on
timeslots 2 & 3.

Mode 3. 8 bit companded PCM I/O on
timeslots 2 & 3. Includes D & C chan-
nel bypass in timeslots 0 & 1.

Mode 4. 16 bit 2's complement linear
PCM I/O on timeslots 0 - 3.

8-54

MT9123

Preliminary Information

Table 5 - SSI Enable Strobe Pins

PCM Law and Format Control (LAW, FORMAT)

The PCM companding/coding law used by the
MT9123 is controlled through the LAW and FORMAT
pins. ITU-T G.711 companding curves for

-Law and

A-Law are selected by the LAW pin. PCM coding
ITU-T G.711 and Sign-Magnitude are selected by the
FORMAT pin. See Table 6.

Linear PCM

The 16-bit 2's complement PCM linear coding
permits a dynamic range beyond that which is
specified in ITU-T G.711 for companded PCM. The
echo-cancellation algorithm will accept 16 bits 2's
complement linear code which gives a dynamic
range of +15dBm0.

Linear PCM data must be formatted as 14-bit, 2's
complement data with three bits of sign extension in
the most significant positions (i.e.: S,S,S,12,11,
...1,0) for a total of 16 bits where "S" is the extended
sign bit. When A-Law is converted to 2's complement
linear format, it must be scaled up by 6dB (i.e. left
shifted one bit) with a zero inserted into the least
significant bit position. See Figure 8.

Enable Strobe Pin

Echo Canceller

Port

ENA1

ENB1

ENA2

ENB2

PCM Code

Sign-Magnitude

FORMAT=0

ITU-T (G.711)

FORMAT=1

/A-LAW

LAW = 0 or 1

-LAW

LAW = 0

A-LAW

LAW =1

+ Full Scale

1111 1111

1000 0000

1010 1010

+ Zero

1000 0000

1111 1111

1101 0101

- Zero

0000 0000

0111 1111

0101 0101

- Full Scale

0111 1111

0000 0000

0010 1010

Table 6 - Companded PCM

Bit Clock (BCLK/C4i)

The BCLK/C4i pin is used to clock the PCM data in
both SSI (BCLK) and ST-BUS (C4i) operations.

In SSI operation, the bit rate is determined by the
BCLK frequency. This input must contain either eight
or sixteen clock cycles within the valid enable strobe
window. BCLK may be any rate between 128 KHz to
4.096 MHz and can be discontinuous outside of the
enable strobe windows defined by ENA1, ENB1,
ENA2 and ENB2 pins. Incoming PCM data (Rin, Sin)
are sampled on the falling edge of BCLK while
outgoing PCM data (Sout, Rout) are clocked out on
the rising edge of BCLK. See Figure 17.

In ST-BUS operation, connect the system C4
(4.096MHz) clock to the C4i pin.

Master Clock (MCLK)

A nominal 20MHz master clock (MCLK) is required
for execution of the MT9123 algorithms. The MCLK
input may be asynchronous with the 8KHz frame. If
only one channel operation is required, (Echo
Canceller A only) the MCLK can be as low as
9.6MHz.

Microport

The serial microport provides access to all MT9123
internal read and write registers and it is enabled
when CONFIG1 and CONFIG2 pins are both set to
logic 0. This microport is compatible with Intel MCS-
51 (mode 0), Motorola SPI (CPOL=0, CPHA=0), and
National Semiconductor Microwire specifications.
The microport consists of a transmit/receive data pin
(DATA1), a receive data pin (DATA2), a chip select
pin (CS) and a synchronous data clock pin (SCLK).

The MT9123 automatically adjusts its internal timing
and pin configuration to conform to Intel or Motorola/
National requirements. The microport dynamically
senses the state of the SCLK pin each time CS pin
becomes active (i.e. high to low transition). If SCLK
pin is high during CS activation, then Intel mode 0
timing is assumed. In this case DATA1 pin is defined
as a bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during CS activation, then Motorola/National timing
is assumed and DATA1 is defined as the data
transmit pin while DATA2 becomes the data receive
pin. The MT9123 supports Motorola half-duplex
processor mode (CPOL=0 and CPHA=0). This
means that during a write to the MT9123, by the
Motorola processor, output data from the DATA1 pin

Preliminary Information

MT9123

8-55

must be ignored. This also means that input data on
the DATA2 pin is ignored by the MT9123 during a
valid read by the Motorola processor.

All data transfers through the microport are two bytes
long. This requires the transmission of a Command/
Address byte followed by the data byte to be written
or read from the addressed register. CS must remain
low for the duration of this two-byte transfer. As
shown in Figures 10 and 11, the falling edge of CS
indicates to the MT9123 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT9123 and the microcontroller. At the
end of the two-byte transfer, CS is brought high again
to terminate the session. The rising edge of CS will
tri-state the DATA1 pin. The DATA1 pin will remain tri-
stated as long as CS is high.

Intel processors utilize Least Significant Bit (LSB)
first transmission while Motorola/National processors
use Most Significant Bit (MSB) first transmission.
The MT9123 microport automatically accommodates
these two schemes for normal data bytes. However,
to ensure timely decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel and Motorola/National operations.
Refer to the relative timing diagrams of Figures 10
and 11.

Receive data is sampled on the rising edge of SCLK
while transmit data is clocked out on the falling edge
of SCLK. Detailed microport timing is shown in
Figure 19 and Figure 20.

MT9123

Preliminary Information

8-56

Function

Controllerless

selected when pins CONFIG1 & 2

Controller

selected when pins CONFIG1 & 2 = 00

Normal Configuration Set pins CONFIG1 to 1 and CONFIG2 1 to select this

configuration.

Set bits Extended-Delay to 0 and BBM to 0 in Control Reg-
ister 1 to select.

Back-to-Back
Configuration

Set pins CONFIG1 to 1 and CONFIG2 to 0 to select
this configuration.

Set bit BBM to 1 in Control Register 1 to select.

Extended Delay
Configuration

Set pins CONFIG1 to 0 and CONFIG2 to 1 to select
this configuration.

Set bit Extended-Delay to 1 in Control Register 1 to select.

Mute

Set pins S2/S1 to 00 and S4/S3 to 00 to select for Echo
Canceller A and Echo Canceller B respectively.

Set bit MuteR to 1 or MuteS to 1 in Control Register 2 to
select.

Bypass

Set pins S2/S1 to 01 and S4/S3 to 01 to select for Echo
Canceller A and Echo Canceller B, respectively.

Set bit Bypass to 1 in Control Register 1 to select.

Disable Adaptation

Set pins S2/S1 to 10 and S4/S3 to 10 to select for Echo
Canceller A and Echo Canceller B, respectively.

Set bit AdaptDis to 1 in Control Register 1 to select.

Enable Adaptation

Set pins S2/S1 to 11 and S4/S3 to 11 to select for Echo
Canceller A and Echo Canceller B, respectively.

Set bits AdaptDis to 0 and Bypass to 0 in Control Register
1 to select.

SSI

Tie pin F0i to VSS to select.

ST-BUS

Apply a valid ST-BUS frame pulse to F0i pin to select.

12dB Attenuator

Always disabled.

Set bit PAD to 1 in Control Register 1 to enable.

Double-Talk
Detector

Continuously enabled which disables filter adaptation
when double-talk is detected.

The detection threshold can be controlled via Double-Talk
Detection Threshold Register 1 and 2.

Non-Linear
Processor

Set pin NLP to 1 to enable.

Set bit NLPDis to 1 to disable.

PCM Law

Set pin LAW to 1 or 0 to select A-Law or

-Law

respectively.

Set pin LAW to 1or 0 to select A-Law or

-Law

respectively.

PCM Format

Set pin FORMAT to 0 or 1 to select Sign-Magnitude or
ITU-T format respectively.

Narrow-Band Signal
Detector

Continuously enabled which disables the filter adapta-
tion when narrow band signal is detected.

Set bit NBDis to 1 in Control Register 2 to disable.

Offset Null Filter

Continuously enabled which removes the DC compo-
nent in the PCM input.

Set bit HPFDis to 1 in Control Register 2 to disable.

Table 7 - MT9123 Function Control Summary

Preliminary Information

MT9123

8-57

Figure 5 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 0 & 1 (Mode 1)

Figure 6 - ST-BUS 8 Bit Companded PCM I/O on Timeslots 2 & 3 (Mode 2)

C4i

F0i

Sin

Rout

Rin

Sout

F0od

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

outputs=High impedance

inputs = don't care

ECA

ECB

In ST-BUS Mode 1, both echo canceller I/O channels are assigned to ST-BUS timeslots 0 and 1. Note that the user
could configure PORT1 and PORT2 into different ST-BUS modes. The pin F0od is always delayed 4 time slots to permit
a more flexible interleave of ST-BUS modes.

PORT1

PORT2

ECA

ECB

C4i

F0i

Sin

Rout

Rin

Sout

F0od

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

7 6 5 4

7 6 5 4 3 2 1 0

3 2 1 0

ECA

ECB

In ST-BUS Mode 2, both echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Note that the user
could configure PORT1 and PORT2 into different ST-BUS modes. The pin F0od is always delayed 4 time slots to permit
a more flexible interleave of ST-BUS modes.

ECA

ECB

PORT1

PORT2

outputs=High impedance

inputs = don't care

MT9123

Preliminary Information

8-58

Figure 7 - ST-BUS 8 Bit Companded PCM I/O with D and C channels (Mode 3)

Figure 8 - ST-BUS 16 Bit 2's complement linear PCM I/O (Mode 4)

C4i

F0i

Rin

Sout

ECA

ECB

F0od

Sin

Rout

ECA

ECB

PORT1

PORT2

indicates that an input channel is bypassed to an output channel

ST-BUS Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and both
echo canceller I/O channels are assigned to ST-BUS timeslots 2 and 3. Both PORT1 and PORT2 must be configured in
ST-BUS Mode 3.

outputs=High impedance

inputs = don't care

7 6 5 4 3 2 1 0

C4i

F0i

Rin

Sout

ECA

ECB

F0od

7 6 5 4 3 2 1 0

Sin

Rout

PORT1

PORT2

S S S 12 11 10 9 8

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

ECA

ECB

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

7 6 5 4 3 2 1 0

S S S 12 11 10 9 8

ST-BUS Mode 4 allows 16 bits 2's complement linear data to be transferred using ST-BUS I/O timing. Note that PORT1
and PORT2 need not necessarily both be in mode 4.

outputs=High impedance

inputs = don't care

Preliminary Information

MT9123

8-59

Figure 9 - SSI Operation

Figure 10 - Serial Microport Timing for Intel Mode 0

BCLK

ENA1

ENB1

Rin

Sout

ECA

ECB

8 or 16 bits

PORT1

PORT2

ECA

ECB

8 or 16 bits

ENA2

ENB2

Sin

Rout

Note that the two ports are independent so that, for example, PORT1 can operate with 8 bit enable strobes and PORT2
can operate with 16 bit enable strobes.

outputs=High impedance

inputs = don't care

R/W

COMMAND/ADDRESS

DATA INPUT/OUTPUT

DATA 1

SCLK

Delays due to internal processor timing which are transparent to the MT9123.

The MT9123:

outputs transmit data on the falling edge of SCLK

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

The COMMAND/ADDRESS byte contains:

1 bit - Read/Write

6 bits - Addressing Data
1 bit - Unused

latches receive data on the rising edge of SCLK

MT9123

Preliminary Information

8-60

Figure 11 - Serial Microport Timing for Motorola Mode 00 or National Microwire

R/W

COMMAND/ADDRESS

DATA INPUT

DATA 2
Receive

DATA 1
Transmit

SCLK

Delays due to internal processor timing which are transparent to the MT9123.

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

6 bits - Addressing Data
1 bit - Unused

High Impedance

DATA OUTPUT

The MT9123:

outputs transmit data on the falling edge of SCLK

latches receive data on the rising edge of SCLK

Preliminary Information

MT9123

8-61

Register Summary

Extended-

When high, Echo Cancellers A and B are internally cascaded into one 128ms echo canceller.

When low, Echo Cancellers A and B operate independently.
Do not enable both Extended-Delay and BBM configurations at the same time.

AdaptDis

When high, echo canceller adaptation is disabled.

When low, the echo canceller dynamically adapts to the echo path characteristics.

Bypass

When high, Sin data is by-passed to Sout and Rin data is by-passed to Rout.

When low, output data on both Sout and Rout is a function of the echo canceller algorithm.

PAD

When high, 12dB of attenuation is inserted into the Rin to Rout path.

When low the Rin to Rout path gain is 0dB.

BBM

When high the Back to Back configuration is enabled.

When low the Normal configuration is enabled. Do not enable Extended-Delay and BBM configurations at the same time.
Always set both BBM bits of the two echo cancellers to the same logic value to avoid conflict.

INJDis

When high, the noise injection process is disabled. When low noise injection is enabled.

Reset

When high, the power-up initialization is executed presetting all register bits including this bit.

Note: Bits marked as "1" or "0" are reserved bits and should be written as indicated.

Echo Canceller A, Control Register 1

ADDRESS = 00h WRITE/READ VERIFY

Power Reset Value

0000 0000

INJDis

BBM

PAD

AdaptDis

Extended

Bypass

Reset

Power Reset Value

0000 0010

INJDis

BBM

PAD

AdaptDis

Bypass

Reset

Echo Canceller B, Control Register 1

ADDRESS = 20h WRITE/READ VERIFY

Delay

CRA1

CRB1

MuteR

When high, data on Rout is muted to quiet code. When low, Rout carries active code.

MuteS

When high, data on Sout is muted to quiet code. When low, Sout carries active code.

HPFDis

When high, the offset nulling high pass filters are bypassed in the Rin and Sin paths.

When low, the offset nulling filters are active and will remove DC offsets on PCM input signals.

NBDis

When high, the narrow-band detector is disabled. When low, the narrow-band detector is enabled.

NLPDis

When high, the non-linear processor is disabled.

When low, the non-linear processors function normally. Useful for G.165 conformance testing.

Note: Bits marked as "0" are reserved bits and should be written as indicated.

Echo Canceller A, Control Register 2

ADDRESS = 01h WRITE/READ VERIFY

Power Reset Value

0000 0000

NLPDis

HPFDis

MuteS

MuteR

Echo Canceller B, Control Register 2

ADDRESS = 21h WRITE/READ VERIFY

NBDis

CR2

Logic high indicates the presence of a narrow-band signal on Rin.

Active

Logic high indicates that the power level on Rin is above the threshold level (i.e., low power condition).

Down

Decision indicator for the non-linear processor gain adjustment.

Conv

Decision indicator for rapid adaptation convergence. Logic high indicates a rapid convergence state.

DTDet

Logic high indicates the presence of a double-talk condition.

Power Reset Value

0000 0000

DTDet

Conv

Active

Echo Canceller A, Status Register

ADDRESS = 02h READ

Echo Canceller B, Status Register

ADDRESS = 22h READ

Down

MT9123

Preliminary Information

8-62

Power Reset Value

00h

Echo Canceller A, Flat Delay Register

ADDRESS = 04h WRITE/READ VERIFY

Echo Canceller B, Flat Delay Register

ADDRESS = 24h WRITE/READ VERIFY

Power Reset Value

00h

Echo Canceller A, Decay Step Number Register

ADDRESS = 07h WRITE/READ VERIFY

Echo Canceller B, Decay Step Number Register

ADDRESS = 27h WRITE/READ VERIFY

Power Reset Value

04h

SSC

Echo Canceller A, Decay Step Size Control Register

ADDRESS = 06h WRITE/READ VERIFY

Echo Canceller B, Decay Step Size Control Register

ADDRESS = 26h WRITE/READ VERIFY

Note: Bits marked with "0" are reserved bits and should be written "0".

SSC

Amplitude of MU

Time

Flat Delay (FD

7-0

)

Step Size (SS)

1.0

-16

FIR Filter Length (512 or 1024 taps)

Number of Steps (NS

7-0

)

The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation
step-size (MU) to be programmed over the length of the FIR filter. A programmable MU profile allows the performance of the echo
canceller to be optimized for specific applications. For example, if the characteristic of the echo response is known to have a flat
delay of several milliseconds and a roughly exponential decay of the echo impulse response, then the MU profile can be
programmed to approximate this expected impulse response thereby improving the convergence characteristics of the adaptive
filter. Note that in the following register descriptions, one tap is equivalent to 125

s (64ms/512 taps).

7-0

Flat Delay: This register defines the flat delay of the MU profile, (i.e., where the MU value is 2

-16

). The delay is defined

as FD

7-0

x 8 taps. For example; if FD

7-0

= 5, then MU=2

-16

for the first 40 taps of the echo canceller FIR filter. The valid

range of FD

7-0

is: 0 <= FD

7-0

<= 64 in normal mode and 0 <= FD

7-0

<= 128 in extended-delay mode. The default value of

7-0

is zero.

SSC

2-0

Decay Step Size Control: This register controls the step size (SS) to be used during the exponential decay of MU. The
decay rate is defined as a decrease of MU by a factor of 2 every SS taps of the FIR filter, where SS = 4 x2

SSC

2-0

. For

example; If SSC

2-0

= 4, then MU is reduced by a factor of 2 every 64 taps of the FIR filter. The default value of SSC

2-0

is 04h.

7-0

Decay Step Number: This register defines the number of steps to be used for the decay of MU where each step has a
period of SS taps (see SSC

2-0

). The start of the exponential decay is defined as:

Filter Length (512 or 1024) - [ Decay Step Number (NS

7-0

) x Step Size (SS) ] where SS = 4 x2

SSC

2-0

For example, if NS

7-0

=4 and SSC

2-0

=4, then the exponential decay start value is 512 - [NS

7-0

x SS] = 512 - [4 x (4x2

)] =

256 taps for a filter length of 512 taps.

Preliminary Information

MT9123

8-63

Power Reset Value

N/A

Echo Canceller A, Rin Peak Detect Register 2

ADDRESS = 0Dh READ

Echo Canceller B, Rin Peak Detect Register 2

ADDRESS = 2Dh READ

Power Reset Value

N/A

Echo Canceller A, Rin Peak Detect Register 1

ADDRESS = 0Ch READ

Echo Canceller B, Rin Peak Detect Register 1

ADDRESS = 2Ch READ

These peak detector registers allow the user to monitor the receive in signal (Rin) peak signal level. The information is in 16-bit 2's
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.

Power Reset Value

N/A

Echo Canceller A, Sin Peak Detect Register 2

ADDRESS = 0Fh READ

Echo Canceller B, Sin Peak Detect Register 2

ADDRESS = 2Fh READ

Power Reset Value

N/A

Echo Canceller A, Sin Peak Detect Register 1

ADDRESS = 0Eh READ

Echo Canceller B, Sin Peak Detect Register 1

ADDRESS = 2Eh READ

These peak detector registers allow the user to monitor the send in signal (Sin) peak signal level. The information is in 16-bit 2's
complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low
byte is in Register 1.

Power Reset Value

N/A

Echo Canceller A, Error Peak Detect Register 2

ADDRESS = 11h READ

Echo Canceller B, Error Peak Detect Register 2

ADDRESS = 31h READ

Power Reset Value

N/A

Echo Canceller A, Error Peak Detect Register 1

ADDRESS = 10h READ

Echo Canceller B, Error Peak Detect Register 1

ADDRESS = 30h READ

These peak detector registers allow the user to monitor the error signal peak level. The information is in 16-bit 2's complement
linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in Register 2 and the low byte is in
Register 1.

MT9123

Preliminary Information

8-64

Power Reset Value

48h

DTDT

Echo Canceller A, Double-Talk Detection Threshold Register 2

ADDRESS = 15h WRITE/READ VERIFY

Echo Canceller B, Double-Talk Detection Threshold Register 2

ADDRESS = 35h WRITE/READ VERIFY

Power Reset Value

00h

DTDT

Echo Canceller A, Double-Talk Detection Threshold Register 1

ADDRESS = 14h WRITE/READ VERIFY

Echo Canceller B, Double-Talk Detection Threshold Register 1

ADDRESS = 34h WRITE/READ VERIFY

This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2's complement linear
value defaults to 4800h= 0.5625 or -5dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in Register 2 and
the low byte is in Register 1.

DTDT

Power Reset Value

08h

NLP

Echo Canceller A, Non-Linear Processor Threshold Register 2

ADDRESS = 19h WRITE/READ VERIFY

Echo Canceller B, Non-Linear Processor Threshold Register 2

ADDRESS = 39h WRITE/READ VERIFY

Power Reset Value

00h

NLP

Echo Canceller A, Non-Linear Processor Threshold Register 1

ADDRESS = 18h WRITE/READ VERIFY

Echo Canceller B, Non-Linear Processor Threshold Register 1

ADDRESS = 38h WRITE/READ VERIFY

This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit 2's complement
linear value defaults to 0800h = 0.0625 or -24.1dB. The maximum value is 7FFFh = 0.9999 or 0 dB. The high byte is in
Register 2 and the low byte is in Register 1.

NLPTHR

Power Reset Value

40h

Echo Canceller A, Adaptation Step Size (MU) Register 2

ADDRESS = 1Bh WRITE/READ VERIFY

Echo Canceller B, Adaptation Step Size (MU) Register 2

ADDRESS = 3Bh WRITE/READ VERIFY

Power Reset Value

00h

Echo Canceller A, Adaptation Step Size (MU) Register 1

ADDRESS = 1Ah WRITE/READ VERIFY

Echo Canceller B, Adaptation Step Size (MU) Register 1

ADDRESS = 3Ah WRITE/READ VERIFY

This register allows the user to program the level of MU. MU is a 16 bit 2's complement value which defaults to 4000h = 1.0
The high byte is in Register 2 and the low byte is in Register 1.

Preliminary Information

MT9123

8-65

Applications

Figure 12 - (Basic Rate ISDN) Wireless Application Diagram

Figure 13 - (Analog Trunk) Wireless Application Diagram

F0b

DSTo

DSTi

C4o

F0i

MCLK

EN1
EN2

ADPCMo

ADPCMi

Din
Dout

STB1

Sin

Rout

BCLK

C20

BCLK

Sout

Rin

DSTi

DSTo

ENA
ENB

MT9123

MT9125 ADPCM

Dual RF Section

MT8910 2B1Q
MT8972 Bi-Phase
MT8931 S-INT

echo

paths

MT9123 is in SSI mode

F0i

Din

Dout

Clockin

MT8941 PLL

MT9160 5V CODEC

F0i

MCLK

EN1
EN2

ADPCMo

ADPCMi

Din
Dout

STB1

C20

BCLK

DSTi

DSTo

MT9125 ADPCM

Dual RF Section

F0i

Din

Dout

Clockin

MT9160 5V CODEC

MT9123 is in SSI mode

Sin

Rout

BCLK

Sout

Rin

ENA
ENB

MT9123

echo

path

echo

path

MT9123

Preliminary Information

8-66

Figure 14 - (Analog Trunk) Wireless Application Diagram

Figure 15 - (Basic Rate ISDN) Wired Telephone Application Diagram

F0i

Din

Dout

Clockin

MT9160 5V CODEC

F0i

MCLK

EN1

ADPCMo

ADPCMi

Din
Dout

STB1

C20

BCLK

DSTi

DSTo

MT9125 ADPCM

Dual RF Section

echo

path

echo
path

F0i

Din

Dout

Clockin

MT9160 5V CODEC

MT9123 connected in ST-BUS mode 1

Sin

Rout

Sout

Rin

MT9123

MT8941 PLL

F0i

C4i

F0b

DSTo

DSTi

C4o

F0i

MCLK

Sin

Sout

Rout

Rin

DSTi

DSTo

MT9123

MT909x Digital Phone

MT8910 2B1Q
MT8972 Bi-phase
MT8931 S-INT

echo

path

F0i

C4i

MT9123 in ST-BUS mode 1

using D&C channel bypass

Back-To-Back Configuration

Handset

Preliminary Information

MT9123

8-67

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

* DC Electrical Characteristics are over recommended temperature and supply voltage.

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

Supply Voltage

-V

-0.3

7.0

Voltage on any digital pin

i/o

-0.3

+ 0.3

Continuous Current on any digital pin

i/o

Storage Temperature

-65

150

Package Power Dissipation

500

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

4.5

5.0

5.5

TTL Input High Voltage

2.4

400mV noise margin

TTL Input Low Voltage

0.4

400mV noise margin

CMOS Input High Voltage

4.5

CMOS Input Low Voltage

0.5

Operating Temperature

-40

+85

DC Electrical Characteristics*

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Conditions/Notes

Supply Current

100

PWRDN = 0
PWRDN = 1, clocks active

Input HIGH voltage (TTL)

2.0

All except MCLK,Sin,Rin

Input LOW voltage (TTL)

0.8

All except MCLK,Sin,Rin

Input HIGH voltage (CMOS)

IHC

3.5

MCLK,Sin,Rin

Input LOW voltage (CMOS)

ILC

1.5

MCLK,Sin,Rin

Input leakage current

0.1

to V

High level output voltage

0.9

=2.5mA

Low level output voltage

0.1V

=5.0mA

High impedance leakage

to V

Output capacitance

Input capacitance

PWRDN

Positive Threshold Voltage
Hysteresis
Negative Threshold Voltage

V+
V

V-

3.75

1.0

1.25

V
V
V

MT9123

Preliminary Information

8-68

Timing is over recommended temperature and power supply voltages.

AC Electrical Characteristics

- Serial Data Interfaces (see Figures 17 and 18)

Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Max

Units

Test Notes

MCLK Clock High

MCH

MCLK Clock Low

MCL

MCLK Frequency

Dual Channel
Single Channel

DCLK

SCLK

19.15

9.58

20.5

MHz
MHz

BCLK/C4i Clock High

BCH,

C4H

BCLK/C4i Clock Low

BLL,

C4L

BCLK/C4i Period

BCP

240

7900

SSI Enable Strobe to Data Delay (first
bit)

=150pF

SSI Data Output Delay (excluding first
bit)

=150pF

SSI Output Active to High Impedance

AHZ

=150pF

SSI Enable Strobe Signal Setup

SSS

BCP

-15

SSI Enable Strobe Signal Hold

SSH

BCP

-10

SSI Data Input Setup

DIS

SSI Data Input Hold

DIH

F0i Setup

F0iS

150

F0i Hold

F0iH

150

ST-BUS Data Output delay

DSD

=150pF

ST-BUS Output Active to High
Impedance

ASHZ

=150pF

ST-BUS Data Input Hold time

DSH

ST-BUS Data Input Setup time

DSS

F0od Delay

DFD

=150pF

F0od Pulse Width Low

DFW

200

=150pF

Preliminary Information

MT9123

8-69

Timing is over recommended temperature range and recommended power supply voltages.

Table 8 - Reference Level Definition for Timing Measurements

Figure 16 Master Clock - MCLK

Notes: 1. CMOS output

2. TTL input compatible
3. CMOS input
(see Table 8 for symbol definitions)

AC Electrical Characteristics

- Microport Timing (see Figure 17)

Characteristics

Sym

Min

Max

Units

Test Notes

Input Data Setup

IDS

100

Input Data Hold

IDH

Output Data Delay

ODD

100

=150pF

Serial Clock Period

SCP

500

SCLK Pulse Width High

SCH

250

SCLK Pulse Width Low

SCL

250

CS Setup-Intel

CSSI

200

CS Setup-Motorola

CSSM

100

CS Hold

CSH

100

CS to Output High Impedance

OHZ

100

=150pF

Characteristic

Symbol

TTL Pin

CMOS Pin

Units

TTL reference level

1.5

CMOS reference level

0.5*V

Input HIGH level

2.4

0.9*V

Input LOW level

0.4

0.1*V

Rise/Fall HIGH measurement point

2.0

0.7*V

Rise/Fall LOW measurement point

0.8

0.3*V

MCLK

(3)

MCH

MCL

MT9123

Preliminary Information

8-70

Figure 17 - SSI Data Port Timing

Notes: 1. CMOS output

2. TTL input compatible
3. CMOS input
(see Table 8 for symbol definitions)

Figure 18 - ST-BUS Data Port Timing

Notes: 1. CMOS output

2. TTL input compatible
3. CMOS input
(see Table 8 for symbol definitions)

Sout/Rout

(1)

BCLK

(2)

ENA1/ENA2

(2)

Rin/Sin

(3)

SSS

AHZ

SSH

DIS

DIH

BCP

BCH

BCL

Bit 0

Bit 1

Bit 0

Bit 1

or
ENB1/ENB2

(2)

Sout/Rout

(1)

C4i

(2)

F0i

(2)

Rin/Sin

(3)

F0od

(1)

F0iS

F0iH

DSS

DSH

DSD

ASHZ

DFD

DFW

C4H

C4L

Bit 0

Bit 1

Bit 0

Bit 1

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Suffix

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

DIM

8-Pin

16-Pin

18-Pin

20-Pin

Plastic

Min

Max

Min

Max

Min

Max

Min

Max

0.210 (5.33)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.008

(0.203)

0.014 (0.356)

0.008 (0.203)

0.014(0.356)

0.008 (0.203)

0.014 (0.356)

0.008 (0.203)

0.014 (0.356)

0.355 (9.02)

0.400 (10.16)

0.780 (19.81)

0.800 (20.32)

0.880 (22.35)

0.920 (23.37)

0.980 (24.89)

1.060 (26.9)

0.005 (0.13)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.100 BSC (2.54)

0.300 BSC (7.62)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.430 (10.92)

0.060 (1.52)

n-2 n-1 n

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)

General-8

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Suffix

DIM

22-Pin

24-Pin

28-Pin

40-Pin

Plastic

Min

Max

Min

Max

Min

Max

Min

Max

0.210 (5.33)

0.250 (6.35)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.045 (1.15)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

1.050 (26.67)

1.120 (28.44)

1.150 (29.3)

1.290 (32.7)

1.380 (35.1)

1.565 (39.7)

1.980 (50.3)

2.095 (53.2)

0.005 (0.13)

0.390 (9.91)

0.430 (10.92)

0.600 (15.24)

0.670 (17.02)

0.600 (15.24)

0.670 (17.02)

0.600 (15.24)

0.670 (17.02)

0.290 (7.37)

.330 (8.38)

0.330 (8.39)

0.380 (9.65)

0.485 (12.32)

0.580 (14.73)

0.485 (12.32)

0.580 (14.73)

0.485 (12.32)

0.580 (14.73)

0.246 (6.25)

0.254 (6.45)

0.100 BSC (2.54)

0.400 BSC (10.16)

0.600 BSC (15.24)

0.300 BSC (7.62)

0.430 (10.92)

0.115 (2.93)

0.160 (4.06)

0.115 (2.93)

0.200 (5.08)

0.115 (2.93)

0.200 (5.08)

0.115 (2.93)

0.200 (5.08)

n-2 n-1 n

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)

Shaded areas for 300 Mil Body Width 24 PDIP only

Package Outlines

Plastic J-Lead Chip Carrier - P-Suffix

Dim

20-Pin

28-Pin

44-Pin

68-Pin

84-Pin

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

0.165

(4.20)

0.180

(4.57)

0.165

(4.20)

0.180

(4.57)

0.165

(4.20)

0.180

(4.57)

0.165

(4.20)

0.200

(5.08)

0.165

(4.20)

0.200

(5.08)

0.090

(2.29)

0.120

(3.04)

0.090

(2.29)

0.120

(3.04)

0.090

(2.29)

0.120

(3.04)

0.090

(2.29)

0.130

(3.30)

0.090

(2.29)

0.130

(3.30)

D/E

0.385

(9.78)

0.395

(10.03)

0.485

(12.32)

0.495

(12.57)

0.685

(17.40)

0.695

(17.65)

0.985

(25.02)

0.995

(25.27)

1.185

(30.10)

1.195

(30.35)

0.350

(8.890)

0.356

(9.042)

0.450

(11.430)

0.456

(11.582)

0.650

(16.510)

0.656

(16.662)

0.950

(24.130)

0.958

(24.333)

1.150

(29.210)

1.158

(29.413)

0.290

(7.37)

0.330

(8.38)

0.390

(9.91)

0.430

(10.92)

0.590

(14.99)

0.630

(16.00)

0.890

(22.61)

0.930

(23.62)

1.090

(27.69)

1.130

(28.70)

0.004

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.026

(0.661)

0.032

(0.812)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.013

(0.331)

0.021

(0.533)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.020

(0.51)

0.020

(0.51)

0.020

(0.51)

0.020

(0.51)

0.020

(0.51)

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) For D & E add for allowable Mold Protrusion 0.010"

e: (lead coplanarity)

General-10

TECHNICAL DOCUMENTATION - NOT FOR RESALE

World Headquarters - Canada

Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America

Asia/Pacific

Europe, Middle East,

Tel: +1 (770) 486 0194

Tel: +65 333 6193

and Africa (EMEA)

Fax: +1 (770) 631 8213

Fax: +65 333 6192

Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

http://www.mitelsemi.com

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively "Mitel") is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this
publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel's
conditions of sale which are available on request.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT9123

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