7-77

Features

Programmable

-Law/A-Law Codec and Filters

Programmable CCITT (G.711)/sign-magnitude
coding

Programmable transmit, receive and side-tone
gains

Fully differential interface to handset
transducers - including 300 ohm receiver driver

Flexible digital interface including ST-BUS/SSI

Serial microport or default controllerless mode

Single 5 volt supply

Low power operation

CCITT G.714 compliant

Applications

Digital telephone sets

Cellular radio sets

Local area communications stations

Pair Gain Systems

Line cards

Description

The MT9160 5V Multi-featured Codec incorporates a
built-in Filter/Codec, gain control and programmable
sidetone path as well as on-chip anti-alias filters,
reference voltage and bias source. The device
supports both A-Law and

-Law requirements.

Complete telephony interfaces are provided for
connection to handset transducers. Internal register
access is provided through a serial microport
compatible with various industry standard
micro-controllers. The device also supports
controllerless operation utilizing the default register
conditions.

The MT9160 is fabricated in Mitel's ISO

-CMOS

technology ensuring low power consumption and
high reliability.

Ordering Information

MT9160AE

24 Pin Plastic DIP

MT9160AS

20 Pin SOIC

-40°C to +85°C

Figure 1 - Functional Block Diagram

AAAA

M -

M +

HSPKR +

HSPKR -

FILTER/CODEC GAIN

ENCODER

DECODER

7dB

-7dB

Transducer

Interface

Flexible

Digital

Interface

Timing

ST-BUS

C & D

Channels

Serial Microport

/IRQ

VSSD

VDD

VSSA

VBias

VRef

Din

Dout

STB/F0i

CLOCKin

PWRST

DATA1

DATA2

SCLK

ISSUE 3

May 1995

MT9160

5 Volt Multi-Featured Codec (MFC)

ISO

-CMOS

Preliminary Information

MT9160

Preliminary Information

7-78

Figure 2 - Pin Connections

Pin Description

Pin #

SOIC DIP

Name

Description

Bias

Bias Voltage (Output). (V

/2) volts is available at this pin for biasing external

amplifiers. Connect 0.1 µF capacitor to V

SSA

Ref

Reference Voltage for Codec (Output). Nominally [(V

/2)-1.5] volts. Used

internally. Connect 0.1 µF capacitor to V

SSA

PWRST

Power-up Reset (Input). CMOS compatible input with Schmitt Trigger (active low).

Internal Connection. Tie externally to V

for normal operation.

/IRQ

- When internal control bit DEn = 0 this CMOS level compatible input pin governs

the companding law used by the filter/Codec;

-Law when tied to V

and A-Law

when tied to V

. Logically OR'ed with A/

IRQ - When internal control bit DEn = 1 this pin becomes an open-drain interrupt
output signalling valid access to the D-Channel registers in ST-BUS mode.

SSD

Digital Ground. Nominally 0 volts.

Chip Select (Input). This input signal is used to select the device for microport data
transfers. Active low. TTL level compatible.

SCLK

Serial Port Synchronous Clock (Input). Data clock for microport. TTL level
compatible.

DATA 1

Bidirectional Serial Data. Port for microprocessor serial data transfer. In Motorola/
National mode of operation, this pin becomes the data transmit pin only and data
receive is performed on the DATA 2 pin. Input TTL level compatible.

DATA 2

Serial Data Receive. In Motorola/National mode of operation, this pin is used for
data receive. In Intel mode, serial data transmit and receive are performed on the
DATA 1 pin and DATA 2 is disconnected. Input TTL level compatible.

24 PIN PDIP

M -

M +

VBias

VRef

VSSD

SCLK

DATA1
DATA2

Din
Dout

VSSA

HSPKR +
HSPKR -
VDD

1
2
3
4
5
6
7
8
9

10
11
12

24
23
22
21
20
19
18
17

PWRST

/IRQ

STB/F0i

CLOCKin

M -

M +

VBias

VRef

VSSD

SCLK

DATA1
DATA2

Din
Dout

VSSA

HSPKR +
HSPKR -

VDD

1
2
3
4
5
6
7
8
9

20
19
18
17

PWRST

/IRQ

STB/F0i

CLOCKin

20 PIN SOIC

Preliminary Information

MT9160

7-79

out

Data Output. A high impedance three-state digital output for 8 bit wide channel data
being sent to the Layer 1 transceiver. Data is shifted out via this pin concurrent with
the rising edge of the bit clock during the timeslot defined by STB, or according to
standard ST-BUS timing.

Data Input. A digital input for 8 bit wide channel data received from the Layer 1
transceiver. Data is sampled on the falling edge of the bit clock during the timeslot
defined by STB, or according to standard ST-BUS timing. Input level is CMOS
compatible.

STB/F0i

Data Strobe/Frame Pulse (Input). For SSI mode this input determines the 8 bit
timeslot used by the device for both transmit and receive data. This active high signal
has a repetition rate of 8 kHz. Standard frame pulse definitions apply in ST-BUS
mode (refer to Figure 11). CMOS level compatible input.

CLOCKin Clock (Input). (CMOS level compatible). The clock provided to this input pin is used

for the internal device functions. For SSI mode connect the bit clock to this pin when
it is 512 kHz or greater. Connect a 4096 kHz clock to this input when the available bit
clock is 128 kHz or 256 kHz. For ST-BUS mode connect C4i to this pin.

Positive Power Supply (Input). Nominally 5 volts.

HSPKR-

Inverting Handset Speaker (Output). Output to the handset speaker (balanced).

HSPKR+ Non-Inverting Handset Speaker (Output). Output to the handset speaker

(balanced).

SSA

Analog Ground (Input). Nominally 0 volts.

M-

Inverting Microphone (Input). Inverting input to microphone amplifier from the
handset microphone.

M+

Non-Inverting Microphone (Input). Non-inverting input to microphone amplifier
from the handset microphone.

3,9,

16,21

No Connect. (DIP Package only).

Pin Description (continued)

Pin #

SOIC DIP

Name

Description

MT9160

Preliminary Information

7-80

Overview

The 5V Multi-featured Codec (MFC) features
complete Analog/Digital and Digital/Analog
conversion of audio signals (Filter/Codec) and an
analog interface to a standard handset transmitter
and receiver (Transducer Interface). The receiver
amplifier is capable of driving a 300 ohm load.

Each of the programmable parameters within the
functional blocks is accessed through a serial
microcontroller port compatible with Intel MCS-51

Motorola SPI

and National Semiconductor

Microwire

specifications. These parameters

include: gain control, power down, mute, B-Channel
select (ST-BUS mode), C&D channel control/access,
law control, digital interface programming and
loopback. Optionally the device may be used in a
controllerless mode utilizing the power-on default
settings.

Functional Description

Filter/Codec

The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are CCITT
G.711 A-law or

-Law, with true-sign/ Alternate Digit

Inversion or true-sign/Inverted Magnitude coding,
respectively. Optionally, sign- magnitude coding may
also be selected for proprietary applications.

The Filter/Codec block also implements transmit and
receive audio path gains in the analog domain. A
programmable gain, voice side-tone path is also
included to provide proportional transmit speech
feedback to the handset receiver. This side tone path
feature is disabled by default. Figure 3 depicts the
nominal half-channel and side-tone gains for the
MT9160.

In the event of PWRST, the MT9160 defaults such
that the side-tone path is off, all programmable gains
are set to 0dB and CCITT

-Law is selected. Further,

the digital port is set to SSI mode operation at 2048
kb/s and the FDI and driver sections are powered up.
(See Microport section.)

The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 5 volt supply

design. This fully differential architecture is
continued into the Transducer Interface section to
provide full chip realization of these capabilities for
the handset functions.

A reference voltage (V

Ref

), for the conversion

requirements of the Codec section, and a bias
voltage (V

Bias

), for biasing the internal analog

sections, are both generated on-chip. V

Bias

is also

brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1

capacitor must be connected from V

Bias

to analog

ground at all times. Likewise, although V

Ref

may only

be used internally, a 0.1

F capacitor from the V

Ref

pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V

Ref

and V

Bias

pins are situated on adjacent pins.

The transmit filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0 dB). Gain control allows the output
signal to be increased up to 7 dB. An anti-aliasing
filter is included. This is a second order lowpass
implementation with a corner frequency at 25 kHz.

The receive filter is designed to meet CCITT G.714
specifications. The nominal gain for this filter is 0 dB
(gain control = 0dB). Gain control allows the output
signal to be attenuated up to 7 dB. Filter response is
peaked to compensate for the sinx/x attenuation
caused by the 8 kHz sampling rate.

Side-tone is derived from the input of the Tx filter and
is not subject to the gain control of the Tx filter
section. Side-tone is summed into the receive
handset transducer driver path after the Rx filter gain
control section so that Rx gain adjustment will not
affect side-tone levels. The side-tone path may be
enabled/disabled with the gain control bits located in
Gain Control Register 2 (address 01h).

Transmit and receive filter gains are controlled by the
TxFG

-TxFG

and RxFG

-RxFG

control bits,

respectively. These are located in Gain Control
Register 1 (address 00h). Transmit filter gain is
adjustable from 0 dB to +7 dB and receive filter gain
from 0dB to -7 dB, both in 1 dB increments.

Side-tone filter gain is controlled by the STG

-STG

control bits located in Gain Control Register 2
(address 01h). Side-tone gain is adjustable from
-9.96 dB to +9.96 dB in 3.32 dB increments.

Intel® and MCS-51® are registered trademarks of Intel Corporation
Motorola® and SPI® are registered trademarks of Motorola Corporation
National® and Microwire® are trademarks of National Semiconductor Corporation

Preliminary Information

MT9160

7-81

Companding law selection for the Filter/Codec is
provided by the A/µ companding control bit while
the coding scheme is controlled by the Smag/CCITT
control bit. The A/

control bit is logically OR'ed with

the A/

pin providing access in both controller and

controllerless modes. Both A/

and Smag/CCITT

reside in Control Register 2 (address 04h). Table 1
illustrates these choices.

Table 1

Transducer Interfaces

Standard handset transducer interfaces are provided
by the MT9160. These are:

· The handset microphone inputs (transmitter),

pins M+/M-. The nominal transmit amplifier gain
may be adjusted to either 6.0 dB or 15.3 dB.

Code

Sign/

Magnitude

CCITT (G.711)

µ-Law

A-Law

+ Full Scale

1111 1111

1000 0000

1010 1010

+ Zero

1000 0000

1111 1111

1101 0101

-Zero

(quiet code)

0000 0000

0111 1111

0101 0101

- Full Scale

0111 1111

0000 0000

0010 1010

Control of this gain is provided by the TxINC
control bit (Gain Control register 1, address 00h).

· The handset speaker outputs (receiver), pins

HSPKR+/HSPKR-. This internally compensated
fully differential output driver is capable of driving
the load shown in Figure 4. The nominal handset
receive path gain may be adjusted to either 0 dB,
-6 dB or -12 dB. Control of this gain is provided
by the RxINC control bit (Gain Control register 1,
address 00h). This gain adjustment is in addition
to the programmable gain provided by the receive
filter.

Figure 4 - Handset Speaker Driver

HSPKR +

HSPKR -

150 ohm

load

(speaker)

MT9160

Figure 3 - Audio Gain Partitioning

Serial Port

Filter/Codec and Transducer Interface

Handset

Receiver

(150

)

PCM

Receive

Filter Gain

0 to -7 dB

(1 dB steps)

Side-tone

-9.96 to

+9. 96 dB

-11 dB

(3.32 dB steps)

-6 dB

Receiver

Driver

-6.0 dB or

0 dB

HSPKR +

HSPKR -

INTERNAL TO DEVICE

EXTERNAL TO DEVICE

Default Bypass

M+

M-

Transmit

Gain

6.37 dB

Transmit Gain

-0.37 dB or 8.93 dB

Transmit Filter
Gain
0 to +7 dB
(1 dB steps)

PCM

Transmitter

Microphone

out

Transmit Filter

Gain

0 to +7 dB

(1 dB steps)

f
a

t S

i
d

-
t
o

ne o

f
f

MT9160

Preliminary Information

7-82

Microport

The serial microport, compatible with Intel MCS-51
(mode 0), Motorola SPI (CPOL=0,CPHA=0) and
National Semiconductor Microwire specifications
provides access to all MT9160 internal read and
write registers. This microport consists of a transmit/
receive data pin (DATA1), a receive data pin
(DATA2), a chip select pin (CS) and a synchronous
data clock pin (SCLK). For D-channel contention
control, in ST-BUS mode, this interface provides an
open-drain interrupt output (IRQ).

The microport dynamically senses the state of the
serial clock (SCLK) each time chip select becomes
active. The device then automatically adjusts its
internal timing and pin configuration to conform to
Intel or Motorola/National requirements. If SCLK is
high during chip select activation then Intel mode 0
timing is assumed. The DATA1 pin is defined as a
bi-directional (transmit/receive) serial port and
DATA2 is internally disconnected. If SCLK is low
during chip select activation then Motorola/National
timing is assumed. Motorola processor mode
CPOL=0, CPHA=0 must be used. DATA1 is defined
as the data transmit pin while DATA2 becomes the
data receive pin. Although the dual port Motorola
controller configuration usually supports full-duplex
communication, only half-duplex communication is
possible in the MT9160. The micro must discard
non-valid data which it clocks in during a valid write
transfer to the MT9160. During a valid read transfer
from the MT9160 data simultaneously clocked out by
the micro is ignored by the MT9160.

All data transfers through the microport are two-byte
transfers requiring the transmission of a Command/
Address byte followed by the data byte written or
read from the addressed register. CS must remain
asserted for the duration of this two-byte transfer. As
shown in Figures 5 and 6 the falling edge of CS
indicates to the MT9160 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT9160 and the microcontroller. At the
end of the two-byte transfer CS is brought high again
to terminate the session. The rising edge of CS will
tri-state the output driver of DATA1 which will remain
tri-stated as long as CS is high.

Intel processors utilize least significant bit first
transmission while Motorola/National processors
employ most significant bit first transmission. The
MT9160 microport automatically accommodates

these two schemes for normal data bytes. However,
to ensure decoding of the R/W and address
information, the Command/Address byte is defined
differently for Intel operation than it is for Motorola/
National operation. Refer to the relative timing
diagrams of Figures 5 and 6.

Receive data is sampled on the rising edge of SCLK
while transmit data is made available concurrent with
the falling edge of SCLK.

Flexible Digital Interface

A serial link is required to transport data between the
MT9160 and an external digital transmission device.
The MT9160 utilizes the ST-BUS architecture
defined by Mitel Semiconductor but also supports a
strobed data interface found on many standard
Codec devices. This interface is commonly referred
to as Synchronous Serial Interface (SSI). The
combination of ST-BUS and SSI provides a Flexible
Digital Interface (FDI) capable of supporting all Mitel
basic rate transmission devices as well as many
other 2B+D transceivers.

The required mode of operation is selected via the
CSL2-0 control bits (Control Register 2, address
04h). Pin definitions alter dependent upon the
operational mode selected, as described in the
following subsections as well as in the Pin
Description tables.

Quiet Code

The FDI can be made to send quiet code to the
decoder and receive filter path by setting the RxMute
bit high. Likewise, the FDI will send quiet code in the
transmit path when the TxMute bit is high. Both of
these control bits reside in Control Register 1 at
address 03h. When either of these bits are low their
respective paths function normally. The -Zero entry
of Table 1 is used for the quiet code definition.

ST-BUS Mode

The ST-BUS consists of output (DSTo) and input
(DSTi) serial data streams, in FDI these are named
Dout and Din respectively, a synchronous clock input
signal CLOCKin (C4i), and a framing pulse input
(F0i). These signals are direct connections to the
corresponding pins of Mitel basic rate devices. The
CSL2, CSL1 and CSL0 bits are set to 1 for ST-BUS
operation.

Preliminary Information

MT9160

7-83

The data streams operate at 2048 kb/s and are Time
Division Multiplexed into 32 identical channels of 64
kb/s bandwidth. A frame pulse (a 244 nSec low going
pulse) is used to parse the continuous serial data
streams into the 32 channel TDM frames. Each
frame has a 125 µSecond period translating into an 8
kHz frame rate. A valid frame begins when F0i

logic low coincident with a falling edge of

C4i. Refer

to Figure 11 for detailed ST-BUS timing. C4i

has a

frequency (4096 kHz) which is twice the data rate.
This clock is used to sample the data at the 3/4
bit-cell position on DSTi and to make data available
on DSTo at the start of the bit-cell. C4i

is also used to

clock the MT9160 internal functions (i.e., Filter/

Figure 5 - Serial Port Relative Timing for Intel Mode 0

Figure 6 - Serial Port Relative Timing for Motorola Mode 00/National Microwire

R/W

Delays due to internal processor timing which are transparent.

The MT9160:-latches received data on the rising edge of SCLK.

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

The COMMAND/ADDRESS byte contains:

COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 1
RECEIVE

DATA 1
TRANSMIT

SCLK

-outputs transmit data on the falling edge of SCLK.

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused

COMMAND/ADDRESS

DATA INPUT/OUTPUT

COMMAND/ADDRESS:

DATA 2
RECEIVE

DATA 1
TRANSMIT

SCLK

R/W

Delays due to internal processor timing which are transparent .

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

The COMMAND/ADDRESS byte contains:

subsequent byte is always data until terminated via CS returning high.

1 bit - Read/Write
3 bits - Addressing Data
4 bits - Unused

The MT9160:-latches received data on the rising edge of SCLK.

-outputs transmit data on the falling edge of SCLK.

MT9160

Preliminary Information

7-84

Codec, Digital gain and tone generation) and to
provide the channel timing requirements.

The MT9160 uses only the first four channels of the
32 channel frame. These channels are always
defined, beginning with Channel 0 after the frame
pulse, as shown in Figure 7 (ST-BUS channel
assignments).

The first two (D & C) Channels are enabled for use
by the DEN and CEN bits respectively, (Control
Register 2, address 04h). ISDN basic rate service
(2B+D) defines a 16 kb/s signalling (D) Channel. The
MT9160 supports transparent access to this
signalling channel. ST-BUS basic rate transmission
devices, which may not employ a microport, provide
access to their internal control/status registers
through the ST-BUS Control (C) Channel. The
MT9160 supports microport access to this
C-Channel.

DEN - D-Channel

In ST-BUS mode access to the D-Channel (transmit
and receive) data is provided through an 8-bit read/
write register (address 06h). D-Channel data is
accumulated in, or transmitted from this register at
the rate of 2 bits/frame for 16 kb/s operation (1 bit/
frame for 8 kb/s operation). Since the ST-BUS is
asynchronous, with respect to the microport, valid
access to this register is controlled through the use
of an interrupt (IRQ) output. D-Channel access is
enabled via the (DEn) bit.

DEn:

When 1, ST-BUS D-channel data (1 or 2 bits/frame
depending on the state of the D8 bit) is shifted into/
out of the D-channel (READ/WRITE) register.

When 0, the receive D-channel data (READ) is still
shifted into the proper register while the DSTo
D-channel timeslot and IRQ outputs are tri-stated
(default).

D8:

When 1, D-Channel data is shifted at the rate of 1 bit/
frame (8 kb/s).

When 0, D-Channel data is shifted at the rate of 2
bits/frame (16 kb/s default).

16 kb/s D-Channel operation is the default mode
which allows the microprocessor access to a full byte
of D-Channel information every fourth ST-BUS
frame. By arbitrarily assigning ST-BUS frame n as
the reference frame, during which the
microprocessor D-Channel read and write operations
are performed, then:

(a) A microport read of address 04 hex will result in a
byte of data being extracted which is composed of
four di-bits (designated by roman numerals I,II,III,IV).
These di-bits are composed of the two D-Channel
bits received during each of frames n, n-1, n-2 and
n-3. Referring to Fig. 8a: di-bit I is mapped from
frame n-3, di-bit II is mapped from frame n-2, di-bit III
is mapped from frame n-1 and di-bit IV is mapped
from frame n.

The D-Channel read register is not preset to any
particular value on power-up (PWRST) or software
reset (RST).

(b) A microport write to Address 04 hex will result in
a byte of data being loaded which is composed of
four di-bits (designated by roman numerals I, II, III,
IV). These di-bits are destined for the two D-Channel
bits transmitted during each of frames n+1, n+2, n+3,
n+4. Referring to Fig. 8a: di-bit I is mapped to frame
n+1, di-bit II is mapped to frame n+2, di bit III is
mapped to frame n+3 and di bit IV is mapped to
frame n+4.

If no new data is written to address 04 hex , the
current D-channel register contents will be
continuously re-transmitted. The D-Channel write
register is preset to all ones on power-up (PWRST)
or software reset (RST).

Figure 7 - ST-BUS Channel Assignment

F0i

DSTi,
DSTo

LSB first

for D-

Channel

MSB first for C, B1- & B2-

Channels

CHANNEL 0
D-channel

CHANNEL 1
C-channel

CHANNEL 2
B1-channel

CHANNEL 3
B2-channel

CHANNELS 4-31

Not Used

125

Preliminary Information

MT9160

7-85

Figure 8a - D-Channel 16 kb/s Operation

Figure 8b - IRQ Timing Diagram

Figure 8c - D-Channel 8 kb/s Operation

n-3

n-2

n-1

n+1

n+2

n+3

n+4*

Microport Read/Write Access

III

Di-bit Group

Transmit

D-Channel

No preset value

Power-up reset to 1111 1111

* note that frame n+4 is equivalent to frame n of the next cycle.

IRQ

DSTo/
DSTi

Di-bit Group
Receive
D-Channel

Microport Read/Write Access

=500 nsec max

pullup

= 10 k

=500 nsec max

Reset coincident with

Read/Write of Address 04 Hex

or next FP, whichever occurs first

C4i

IRQ

8 kb/s operation

16 kb/s operation

DSTo/
DSTi

n-7

n-6

n-5

n-4

n-3

n-2

n-1

n+1

n+2

n+3

n+4

n+5

n+6

n+7

n+8

III

VII

VIII
D7

III

VII

VIII
D7

No preset value

Di-bit Group
Receive
D-Channel

Power-up reset to 1111 1111

IRQ

Microport Read/Write Access

D-Channel

Di-bit Group

Transmit

D-Channel

MT9160

Preliminary Information

7-86

An interrupt output is provided (IRQ) to synchronize
microprocessor access to the D-Channel register
during valid ST-BUS periods only. IRQ will occur
every fourth (eighth in 8 kb/s mode) ST-BUS frame
at the beginning of the third (second in 8 kb/s mode)
ST-BUS bit cell period. The interrupt will be removed
following a microprocessor Read or Write of Address
04 hex or upon encountering the following frames's
FP input, whichever occurs first. To ensure
D-Channel data integrity, microport read/write
access to Address 04 hex must occur before the
following frame pulse. See Figure 8b for timing.

8 kb/s operation expands the interrupt to every eight
frames and processes data one-bit-per-frame.
D-Channel register data is mapped according to
Figure 8c.

CEn - C-Channel

Channel 1 conveys the control/status information for
the Layer 1 transceiver. C-Channel data is
transferred MSB first on the ST-BUS by the MT9160.
The full 64 kb/s bandwidth is available and is
assigned according to which transceiver is being
used. Consult the data sheet for the selected
transceiver for its C-Channel bit definitions and order
of bit transfer.

When CEN is high, data written to the C-Channel
register (address 05h) is transmitted, most
significant bit first, on DSTo. On power-up reset
(PWRST) or software reset (Rst, address 03h) all
C-Channel bits default to logic high. Receive
C-Channel data (DSTi) is always routed to the read
register regardless of this control bit's logic state.

When low, data transmission is halted and this
timeslot is tri-stated on DSTo.

B1-Channel and B2-Channel

Channels 2 and 3 are the B1 and B2 channels,
respectively. B-channel PCM associated with the
Filter/Codec and transducer audio paths is selected
on an independent basis for the transmit and receive
paths. TxBSel and RxBSel (Control Register 1,
address 03h) are used for this purpose.

If no valid transmit path has been selected then the
timeslot output on DSTo is tri-stated (see PDFDI and
PDDR control bits, Control Register 1 address 03h).

SSI Mode

The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). The frame strobe must be synchronous with,
and eight cycles of, the bit clock. A 4.096 MHz
master clock is also required for SSI operation if the
bit clock is less than 512 kHz. The timing
requirements for SSI are shown in Figures 12 & 13.

In SSI mode the MT9160 supports only B-Channel
operation. The internal C and D Channel registers
used in ST-BUS mode are not functional for SSI
operation. The control bits TxBSel and RxBSel, as
described in the ST-BUS section, are ignored since
the B-Channel timeslot is defined by the input STB
strobe. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.

The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.

SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the internal MT9160 functions allowing synchronous
operation. If the available bit clock is 128 kHz or 256
kHz, then a 4096 kHz master clock is required to
derive clocks for the internal MT9160 functions.

Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT9160 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control bits CSL2, CSL1 and CSL0 in Control
Register 2 (address 04h) are used to program the bit
rates.

For synchronous operation data is sampled, from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on
Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid but PDFDI
and PDDR are not true, then quiet code will be
transmitted on Dout during the valid strobe period.
There is no frame delay through the FDI circuit for
synchronous operation.

For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not

Preliminary Information

MT9160

7-87

affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the FDI circuit for asynchronous
operation. Refer to the specifications of Figures 12
& 13 for both synchronous and asynchronous SSI
timing.

PWRST/Software Reset (Rst)

While the MT9160 is held in PWRST no device
control or functionality is possible. While in software
reset (Rst=1, address 03h) only the microport is
functional. Software reset can only be removed by
writing Rst logic low or by setting the PWRST pin.

After Power-up reset (PWRST) or software reset
(Rst) all control bits assume their default states;

-Law functionality, usually 0 dB programmable

gains as well as the device powered up in SSI mode
2048 kb/s operation with Dout tri-stated while there

is no strobe active on STB. If a valid strobe is
supplied to STB, then Dout will be active, during the
defined channel.

To attain complete power-down from a normal
operating condition, write PDFDI = 1 and PDDR = 1
(Control Register 1, address 03h) or put PWRST pin
low.

5V Multi-featured Codec Register Map

RxINC

RxFG

TxINC

TxFG

Gain Control

STG

Gain Control

DrGain

Path Control

PDFDI

PDDR

RST

Mute

Bsel

Control

CEN

DEN

Smag/
CCITT

CSL

Control

C-Channel

D-Channel

PCM/

ANALOG

loopen

Loop Back

MT9160

Preliminary Information

7-88

Register Summary

Receive Gain

Setting (dB)

RxFG

Transmit Gain

Setting (dB)

TxFG

(default)

-1

-2

-3

-4

-5

-6

-7

(default) 0

Gain Control Register 1

ADDRESS = 00h WRITE/READ VERIFY

Power Reset Value

1000 0000

RxINC RxFG

RxFG

TxFG

TxINC

RxFG

= Receive Filter Gain bit n

TxFG

= Transmit Filter Gain bit n

RxINC: When high, the receiver driver nominal gain is set to 0 dB. When low, this gain is -6.0 dB.

TxINC: When high, the transmit amplifier nominal gain is set to 15.3 dB. When low, this gain is 6.0 dB.

Side-tone Gain

Setting (dB)

STG

(default) OFF

-9.96
-6.64
-3.32

3.32
6.64
9.96

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Gain Control Register 2

ADDRESS = 01h WRITE/READ VERIFY

Power Reset Value

XXXX X000

STG

= Side-tone Gain bit n

Note: Bits marked "-" are reserved bits and should be written with logic "0"

Preliminary Information

MT9160

7-89

DrGain

When high, the receiver driver gain is set to -6 dB, with sidetone.

When low, the receiver driver gain is set to 0 dB, with no sidetone.

Path Control

ADDRESS = 02h WRITE/READ VERIFY

Power Reset Value

XX00 0000

DrGain

PDFDI

When high, the FDI PLA and the Filter/Codec are powered down. When low, the FDI is active (default).

PDDR

When high, the ear driver and Filter/Codec are powered down. In addition, in ST-BUS mode, the selected output

channel is tri-stated. In SSI mode the PCM output code will be -zero code during the valid strobe period. The output will
be tri-stated outside of the valid strobe and for the whole frame if no strobe is supplied. When low, the driver and Filter/
Codec are active if PDFDI is low (default).

Rst

When high, a software reset occurs performing the same function as the hardware reset (PWRST) except that the

microport is not affected. A software reset can be removed only by writing this bit low or by a PWRST. When low, the
reset condition is removed.

TxMute

When high the transmit PCM stream is interrupted and replaced with quiet code; thus forcing the output code into a

mute state (only the output code is muted, the transmit microphone and transmit Filter/Codec are still functional). When
low the full transmit path functions normally (default).

RxMute

When high the received PCM stream is interrupted and replaced with quiet code; thus forcing the receive path into a

mute state. When low the full receive path functions normally (default).

TxBsel

When high, the transmit B2 channel is functional in ST-BUS mode. When low, the transmit B1 channel is functional in

ST-BUS mode. Not used in SSI mode.

RxBsel

When high, the receive B2 channel is functional in ST-BUS mode. When low, the receive B1 channel is functional in

ST-BUS mode. Not used in SSI mode.

Control Register 1

ADDRESS = 03h WRITE/READ VERIFY

Power Reset Value

0000 0000

PDFDI PDDR

TxBsel RxBsel

Rst

TxMute RxMute

Note: Bits marked "-" are reserved bits and should be written with logic "0"

MT9160

Preliminary Information

7-90

CEn

When high, data written into the C-Channel register (address 05h) is transmitted during channel 1 on DSTo. When
low, the channel 1 timeslot is tri-stated on DSTo. Channel 1 data received on DSTi is read via the C-Channel
register (address 05h) regardless of the state of CEn. This control bit has significance only for ST-BUS operation
and is ignored for SSI operation.

DEn

When high, data written into the D-Channel Register (address 06h) is transmitted (2 bits/frame) during channel 0

on DSTo. The remaining six bits of the D-Channel carry no information. When low, the channel 0 timeslot is
completely tri-stated on DSTo. Channel 0 data received on DSTi is read via the D-Channel register regardless of
the state of DEN. This control bit has significance only for ST-BUS mode and is ignored for SSI operation.

When high, D-channel operates at 8kb/s. When low, D-channel operates at 16kb/s (default).

A/µ

When high, A-Law encoding/decoding is selected for the MT9160. When low, µ-Law encoding/decoding is

selected.

Smag/CCITT

When high, sign-magnitude code assignment is selected for the Codec input/output. When low, CCITT code
assignment is selected for the Codec input/output; true sign, inverted magnitude (µ-Law) or true sign, alternate
digit inversion (A-Law).

CSL

External bit Clock Rate

(kHz)

CLOCKin (kHz)

Mode

not applicable

4096

ST-BUS

128

4096

SSI

256

4096 SSI

512

SSI

1536

SSI

2048

SSI (default)

4096

SSI

Control Register 2

ADDRESS = 04h WRITE/READ VERIFY

Power Reset Value

0000 0010

CEn

DEn

CSL

Smag/
CCITT

Note: Bits marked "-" are reserved bits and should be written with logic "0"

Preliminary Information

MT9160

7-91

C-Channel Register

ADDRESS = 05h WRITE/READ

Power Reset Value

1111 1111- write

Micro-port access to the ST-BUS C-Channel information read and write

XXXX XXXX - read

D7-D0

Data written to this register will be transmitted every frame, in channel 0, if the DEn control bit is set (address 04h).

Received D-Channel data is valid, regardless of the state of DEn. These bits are valid for ST-BUS mode only and are
accessible only when IRQ indicates valid access.

D-Channel Register

ADDRESS = 06h WRITE/READ

Power Reset Value

1111 1111- write

XXXX XXXX - read

PCM/ANALOG This control bit functions only when loopen is set high. It is ignored when loopen is low.

For loopback operation when this bit is high, the device is configured for digital-to-digital loopback operation. Data on

Din is looped back to Dout without conversion to the analog domain. However, the receive D/A path (from Din to
HSPKR

) still functions. When low, the device is configured for analog-to-analog operation. An analog input signal at

is looped back to the SPKR

outputs through the A/D and D/A circuits as well as through the normal transmit A/D

path (from M

to Dout).

loopen

When high, loopback operation is enabled and the loopback type is governed by the state of the PCM/ANALOG bit.

When low, loopbacks are disabled, the device operates normally and the PCM/ANALOG bit is ignored.

Loopback Register

ADDRESS = 07h WRITE/READ VERIFY

Power Reset Value

XXXX 0000

PCM/

loopen

ANALOG

Note: Bits marked "-" are reserved bits and should be written with logic "0"

MT9160

Preliminary Information

7-92

Figure 9 - Digital Telephone Set

0.1

VBias

+5V

150

+5V

DC to DC
Converter

Twisted Pair

+5V

DSTo

DSTi

Lin

Lout

10.24 MHz

4
5

F0i

C4b

VBias

+5V

330

Av = 1 + 2R

100K

VBias

511

Electret

Microphone

100K

0.1

511

/IRQ

MT9160

M+

M-

0.1

SCLK

DATA1

DATA2

DATA2 Motorola
Mode only

INTEL

MCS-51

MOTOROLA

SPI

Micro-

Controller

MT8972

DNIC

M+

+5V

330

Electret

Microphone

0.1

M-

VBias

Differential Amplifier

Single-ended Amplifier

Typical External Gain

AV= 5-10

(

)

Applications

Figure 9 shows an application in a digital phone set.

Various configurations of pair gain drops are
depicted in Figures 10a and 10b using the MT9125
and MT9126, respectively.

Preliminary Information

MT9160

7-93

1 2

4 5

1 2

4 5

1 2

4 5

.
2

910

-5

-2

meter

i
gna

I/P

ter

i
gna

DC r

i
ng

l
t
age

120V

DC r

i
ng

,
1

,
2

,
3

912

t
a

t
ic

t
r
o

SLI

Funct

i
ons

t
i
onal

DPCM

f
unct

i
onal

cont

r
o

r
i
al

i
cr

r
t

l M

-
5

Mot

r
o

l
a

SPI

t

Se

r
o

i
r
e

i
c

r
oCo

t
r
ol

l
e

74HCT

124

74HCT

124

74HCT

124

2 P

air

ain

SLIC

2 Pa

ir G

ain

SLIC 1

i
g

r
e

t
e

MT9160

Preliminary Information

7-94

1 2

4 5

1 2

4 5

1 2

4 5

160

9160

r
i
al

i
cr

r
t

l M

-
5

Mot

r
o

l
a

SPI

t
Se

r
o

i
r
e

i
c

r
o

l
:

I
C

Func

t
i
ons

t
i
onal

DPCM

f
unc

t
i
onal

cont

r
o

i
c

r
oCont

rol

l
e

C4b

-5

-2

ter

i
gna

ter

i
gnal

I/P

120

DC r

i
n

l
t
a

120V

DC r

i
ng

l
t
age

16 c

ntro

l/s

t
a

t
u

s
li

s
a

r
e

1/2,

/2,

HK1/

,

RC

1/2 - 8

2 S

I
C

'
s

c
ont

rol li

s
for QADPC

,
s

e
opti

ona

s
i
gna

l
s

fo

i
c
r
opor

t a

r
e
:

t
a

,

IR

, C

, CS

D-Cha

nne

l a

c
c

e
s
s
th

rough Cod

c
1

r
o

port a

s
we

l
l
a

C-Ch

l c

ontro

l of MT

891

0/MT

8972

2 Pa

ir G

ain S

LIC 1

2 Pa

ir G

ain S

LIC 2

-5

-2

,
8

,
9,

,
23,

,
3

,
36

.
24 MH

i
gure

-

P

i
r
Ga

i
n

t
e

Preliminary Information

MT9160

7-95

* Excluding PWRST which is a Schmitt Trigger Input.

Note 1: Power delivered to the load is in addition to the bias current requirements.

Note 2: I

DDFT

is not additive to I

DDC1

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Units

Supply Voltage

- V

- 0.3

Voltage on any I/O pin

- 0.3

+ 0.3

Current on any I/O pin (transducers excluded)

± 20

Storage Temperature

- 65

+ 150

Power Dissipation (package)

750

Recommended Operating Conditions

- Voltages are with respect to V

unless otherwise stated

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

4.75

5.25

TTL Input Voltage (high)*

IHT

2.4

Includes Noise margin =
400 mV

TTL Input Voltage (low)*

ILT

0.4

Includes Noise margin =
400 mV

CMOS Input Voltage (high)

IHC

4.5

CMOS Input Voltage (low)

ILC

0.5

Operating Temperature

- 40

+ 85

Power Characteristics

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Static Supply Current (clock
disabled, all functions off, PDFDI/
PDDR=1, PWRST=0)

DDC1

350

Outputs unloaded, Input
signals static, not loaded

Dynamic Supply Current:
Total all functions enabled

DDFT

8.0

See Note 1 and 2.

MT9160

Preliminary Information

7-96

DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.

Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.

Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input HIGH Voltage TTL inputs

IHT

2.0

Input LOW Voltage TTL inputs

ILT

0.8

Input HIGH Voltage CMOS inputs

IHC

3.5

Input LOW Voltage CMOS inputs

ILC

1.5

VBias Voltage Output

Bias

Max. Load = 10k

Ref

Output Voltage

Ref

/2-1.5

No load

Input Leakage Current

0.1

µA

to V

Positive Going Threshold
Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)

T+

T-

3.7

1.3

Output HIGH Current

- 5

- 16

= 2.4V

Output LOW Current

= 0.4V

Output Leakage Current

0.01

µA

OUT

= V

and V

Output Capacitance

Input Capacitance

Clockin Tolerance Characteristics (ST-BUS Mode)

Characteristics

Min

Typ

Max

Units

Test Conditions

C4i Frequency

4095.6

4096

4096.4

kHz

(i.e., 100 ppm)

Preliminary Information

MT9160

7-97

AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: TxINC, refer to Control Register 1, address 00h.

AC Characteristics

for A/D (Transmit) Path

- 0dBm0 = 1.421V

rms

for µ-Law and 1.477V

rms

for

A-Law, at the Codec. (V

Ref

=1.0 volts and V

Bias

=2.5 volts.)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Analog input equivalent to
overload decision

Li3.17

Li3.14

5.79

6.0

Vp-p
Vp-p

-Law

A-Law
Both at Codec

Absolute half-channel gain

M ± to Dout

AX1

AX2

6.0

15.3

dB
dB

Transmit filter gain=0dB
setting.
TxINC = 0*
TxINC = 1*
@1020 Hz

Tolerance at all other transmit
filter settings
(1 to 7dB)

±0.2

Gain tracking vs. input level
CCITT G.714 Method 2

-0.3
-0.6
-1.6

0.3
0.6
1.6

dB
dB
dB

3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0

Signal to total Distortion vs. input
level.
CCITT G.714 Method 2

35
29
24

dB
dB
dB

0 to -30 dBm0
-40 dBm0
-45 dBm0

Transmit Idle Channel Noise

-71

-69

dBrnC0

dBm0p

-Law

A-Law

Gain relative to gain at 1020Hz
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz

-0.25

-0.9

-25
-30
0.0

0.25
0.25

-12.5

-25

dB
dB
dB
dB
dB
dB
dB

Absolute Delay

360

µs

at frequency of minimum
delay

Group Delay relative to D

750
380
130
750

µs
µs
µs
µs

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

Power Supply Rejection

f=1020 Hz
f=0.3 to 3 kHz
f=3 to 4 kHz
f=4 to 50 kHz

PSSR

PSSR1
PSSR2
PSSR3

37
40
35
40

dB
dB
dB
dB

±100mV peak signal on
V

-law

PSSR1-3 not production
tested

MT9160

Preliminary Information

7-98

AC Characteristics

for D/A (Receive) Path

- 0dBm0 = 1.421V

rms

for µ-Law and 1.477V

rms

for A-Law, at the Codec.

Ref

=1.0 volts and V

Bias

=2.5 volts.)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Analog output at the Codec full
scale

Lo3.17

Lo3.14

5.704
5.906

Vp-p
Vp-p

-Law

A-Law

Absolute half-channel gain.

Din to HSPKR±

AR1

AR2

AR3

AR4

-6
-6

-12

dB
dB
dB
dB

DrGain=0, RxINC =1*
DrGain=0, RxINC =0*
DrGain=1, RxINC =1*
DrGain=1, RxINC =0*
@ 1020 Hz

Tolerance at all other receive
filter settings
(-1 to -7dB)

±0.2

Gain tracking vs. input level
CCITT G.714 Method 2

-0.3
-0.6
-1.6

0.3
0.6
1.6

dB
dB
dB

3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0

Signal to total distortion vs. input
level.
CCITT G.714 Method 2

35
29
24

dB
dB
dB

0 to -30 dBm0
-40 dBm0
-45 dBm0

Receive Idle Channel Noise

-78.5

15.5

-77

dBrnC0

dBm0p

-Law

A-Law

Gain relative to gain at 1020Hz
200Hz
300 - 3000 Hz
3000 - 3400 Hz
4000 Hz
>4600 Hz

-0.25
-0.90

0.25
0.25
0.25

-12.5

-25

dB
dB
dB
dB
dB

Absolute Delay

240

µs

at frequency of min. delay

Group Delay relative to D

750
380
130
750

µs
µs
µs
µs

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

Crosstalk

D/A to A/D

A/D to D/A

-74
-80

dB
dB

G.714.16
CCITT

Preliminary Information

MT9160

7-99

Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: RxINC, refer to Control Register 1, address 00h.

AC Electrical Characteristics

for Side-tone Path

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Absolute path gain
gain adjust = 0dB

AS1

AS2

-16.63
-10.63

dB
dB

RxINC = 0*
RxINC = 1*
M± inputs to HSPKR± outputs
1000 Hz at STG2=1

Electrical Characteristics

for Analog Outputs

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

EarpIece load impedance

260

300

ohms

across HSPKR±

Allowable earpiece capacitive
load

300

each pin:

HSPKR+,

HSPKR-

Earpiece harmonic distortion

0.5

300 ohms load across
HSPKR± (tol-15%),
VO

693mV

RMS

, RxINC=1*,

Rx gain=0dB

Electrical Characteristics

for Analog Inputs

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input voltage without overloading
Codec

across M+/M-

IOLH

2.90
1.03

Vp-p
Vp-p

TxINC = 0, A/

= 0*

TxINC = 1, A/

= 1*

Tx filter gain=0dB setting

Input Impedance

M+/M- to V

MT9160

Preliminary Information

7-100

Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25 °C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions

data-data, data-HiZ, HiZ-data.

Figure 11 - ST-BUS Timing Diagram

AC Electrical Characteristics

- ST-BUS Timing (See Figure 11)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

C4i Clock Period

C4P

244

C4i Clock High period

C4H

122

C4i Clock Low period

C4L

122

C4i Clock Transition Time

F0i Frame Pulse Setup Time

F0iS

F0i Frame Pulse Hold Time

F0iH

DSTo Delay

DSToD

100

125

= 50pF, 1k

load.*

DSTi Setup Time

DSTiS

DSTi Hold Time

DSTiH

AAA

DSTo

DSTi

70%
30%

NOTE:

Levels refer to %V

C4L

C4H

C4P

1 bit cell

DSTiS

DSTiH

F0iS

F0iH

DSToD

C4i

F0i

Preliminary Information

MT9160

7-101

Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.

Figure 12 - SSI Synchronous Timing Diagram

AC Electrical Characteristics

- SSI BUS Synchronous Timing (see Figure 12)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

BCL Clock Period

BCL

244

1953

BCL=4096 kHz to 512 kHz

BCL Pulse Width High

BCLH

122

BCL=4096 kHz

BCL Pulse Width Low

BCLL

122

BCL=4096 kHz

BCL Rise/Fall Time

Note 1

Strobe Pulse Width

ENW

8 x t

BCL

Note 1

Strobe setup time before BCL falling

SSS

BCL

-80

Strobe hold time after BCL falling

SSH

BCL

-80

Dout High Impedance to Active Low
from Strobe rising

DOZL

=150 pF, R

=1K

Dout High Impedance to Active High
from Strobe rising

DOZH

=150 pF, R

=1K

10 Dout Active Low to High Impedance

from Strobe falling

DOLZ

=150 pF, R

=1K

11 Dout Active High to High Impedance

from Strobe falling

DOHZ

=150 pF, R

=1K

12 Dout Delay (high and low) from BCL

rising

=150 pF, R

=1K

13 Din Setup time before BCL falling

DIS

14 Din Hold Time from BCL falling

DIH

(BCL)

Din

Dout

STB

70%

30%

70%

30%

70%

30%

70%

30%

BCLH

BCLL

DIS

DIH

DOZL

BCL

DOZH

SSS

ENW

SSH

DOLZ

DOHZ

NOTE:

Levels refer to % V

(CMOS I/O)

CLOCKin

MT9160

Preliminary Information

7-102

Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
NOTE 1: Not production tested, guaranteed by design.

Figure 13 - SSI Asynchronous Timing Diagram

AC Electrical Characteristics

- SSI BUS Asynchronous Timing (note 1) (see Figure 13)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Bit Cell Period

DATA

7812
3906

ns
ns

BCL=128 kHz
BCL=256 kHz

Frame Jitter

600

Bit 1 Dout Delay from STB
going high

dda1

+600

=150 pF, R

=1K

Bit 2 Dout Delay from STB
going high

dda2

600+

DATA

-T

600+

DATA

600 +

DATA

=150 pF, R

=1K

Bit n Dout Delay from STB
going high

ddan

600 +

(n-1) x

DATA

-T

600 +

(n-1) x

DATA

600 +

(n-1) x

DATA

=150 pF, R

=1K

n=3 to 8

Bit 1 Data Boundary

DATA1

DATA

-T

DATA

Din Bit n Data Setup time from
STB rising

DATA

+500ns-T

+(n-1) x

DATA

n=1-8

Din Data Hold time from STB
rising

DATA

+500ns+T

+(n-1) x

DATA

Din

Dout

STB

70%

30%

70%

30%

70%

30%

dda1

NOTE:

Levels refer to % V

(CMOS I/O)

dha1

DATA1

dda2

DATA

Bit 1

Bit 2

Bit 3

DATA

Preliminary Information

MT9160

7-103

Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
* Note: All conditions

data-data, data-HiZ, HiZ-data.

Figure 14 - Microport Timing

AC Electrical Characteristics

- Microport Timing (see Figure 14)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input data setup

IDS

100

Input data hold

IDH

Output data delay

ODD

100

= 150pF, R

= 1K *

Serial clock period

CYC

500

1000

SCLK pulse width high

250

500

SCLK pulse width low

250

500

CS setup-Intel

CSSI

200

CS setup-Motorola

CSSM

100

CS hold

CSH

100

CS to output high impedance

OHZ

100

= 150pF, R

= 1K

AAAA

HiZ

DATA INPUT

DATA OUTPUT

2.0V

0.8V

90%

10%

90%

10%

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

2.0V

0.8V

IDS

IDH

CYC

ODD

CSSI

OHZ

2.0V

0.8V

CSSM

IDH

IDS

2.0V

0.8V

CYC

ODD

CSH

NOTE: % refers to % V

SCLK

Intel
Mode = 0

Motorola
Mode = 00

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT9160AS

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: MT9160AS