7-173

Features

Single 2.7-3.6 volt supply

Programmable

µ-

law/A-law Codec and filters

Fully differential to output driver

SSI digital interface

Individual transmit and receive mute controls

0dB gain in receive path

6dB gain in transmit path

Low power operation

ITU-T G.714 compliant

Applications

Cellular radio sets

Local area communications stations

Line cards

Battery operated equipment

Description

The MT91L62 3V single rail Codec incorporates a
built-in Filter/Codec, transmit anti-alias filter, a
reference voltage and bias source. The device
supports both A-law and

-law requirements. The

MT91L62 is a true 3V device employing a fully
differential architecture to ensure wide dynamic
range.

An analog output driver is provided, capable of
driving a 20k ohm load.

The MT91L62 is fabricated in Mitel's ISO

-CMOS

technology ensuring low power consumption and
high reliability.

Ordering Information

MT91L62AE

20 Pin Plastic DIP (300 mil)

MT91L62AS

20 Pin SOIC

MT91L62AN

20 Pin SSOP

-40

C to +85

Figure 1 - Functional Block Diagram

AIN+

AIN-

AOUT +

AOUT -

FILTER/CODEC GAIN

ENCODER

DECODER

6dB

0 dB

Analog

Interface

PCM

Serial

Interface

Timing

Control

VDD

VSSA

VBias

VRef

Din

Dout

STB

CLOCKin

PWRST

CSL0

CSL1 CSL2 RXMute TXMute

DS5179

ISSUE 4

August 1999

MT91L62

3 Volt Single Rail Codec

ISO

-CMOS

Advance Information

MT91L62

Advance Information

7-174

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

Bias

Bias Voltage (Output). (V

/2) volts is available at this pin for biasing external amplifiers.

Connect 0.1

F capacitor to V

Ref

Reference Voltage for Codec (Output). Nominally [(V

/2)-1.1] volts. Used internally.

Connect 0.1

F capacitor to V

PWRST Power-up Reset. Resets internal state of device via Schmitt Trigger input (active low).

Internal Connection. Tie externally to V

for normal operation.

Law Selection. CMOS level compatable input pin governs the companding law used by the

device. A-law selected when pin tied to V

-law selected when pin tied to V

RXMute Receive Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal

operation. CMOS level compatable input.

TXMute

Transmit Mute. When 1, the transmit PCM is forced to negative zero code. When 0, normal
operation. CMOS level compatable input.

20
21
22

CSL0
CSL1
CSL2

Clock Speed Select. These pins are used to program the speed of the SSI mode as well as the
conversion rate between the externally supplied MCL clock and the 512 KHz clock required by a
filter/codec. Refer to Table 2 for details. CMOS level compatable input.

out

Data Output. A tri-state digital output for 8-bit wide channel data being sent to the Layer 1
device. Data is shifted out via the pin concurrent with the rising edge of BCL during the timeslot
defined by STB.

Data Input. A digital input for 8-bit wide data from the layer 1 device. Data is sampled on the
falling edge of BCL during the timeslot defined by STB. CMOS level compatable input.

STB

Data Strobe. This input determines the 8-bit timeslot used by the device for both transmit and
receive data. This active high signal has a repetition rate of 8 kHz. CMOS level compatable
input.

CLOCKin Clock (Input). The clock provided to this input pin is used by the internal device functions.

Connect bit clock to this pin when it is 512 kHz or greater. Connect a 4096 kHz clock to this pin
when the bit clock is 128 kHz or 256 kHz. CMOS level compatable input.

Positive Power Supply. Nominally 3 volts.

AOUT-

Inverting Analog Output. (balanced).

AOUT+

Non-Inverting Analog Output. (balanced).

Ground. Nominally 0 volts.

Ain-

Inverting Analog Input. No external anti-aliasing is required.

Ain+

Non-Inverting Analog Input. Non-inverting input. No external anti-aliasing is required.

AIN-

AIN+

VBias

VRef

RXMute

CSL0
CSL1
CSL2

Din
Dout

VSS

AOUT +
AOUT -

VDD

1
2
3
4
5
6
7
8
9

20
19
18
17

PWRST

TXMute

STB

CLOCKin

20 PIN PDIP/SOIC/SSOP

Advance Information

MT91L62

7-175

Overview

The 3V Single-Rail Codec features complete Analog/
Digital and Digital/Analog conversion of audio
signals (Filter/Codec) and an analog interface to a
standard analog transmitter and receiver (analog
Interface). The receiver amplifier is capable of
driving a 20k ohm load.

Functional Description

Filter/Codec

The Filter/Codec block implements conversion of the
analog 0-3.3 kHz speech signals to/from the digital
domain compatible with 64 kb/s PCM B-Channels.
Selection of companding curves and digital code
assignment are programmable. These are ITU-T
G.711 A-law or

-Law, with true-sign/Alternate Digit

Inversion.

The Filter/Codec block also implements a transmit
audio path gain in the analog domain. Figure 3
depicts the nominal half-channel for the MT91L62.

The internal architecture is fully differential to provide
the best possible noise rejection as well as to allow a
wide dynamic range from a single 3 volt supply
design. This fully differential architecture is
continued into the Analog Interface section to
provide full chip realization of these capabilities for
the external functions.

A reference voltage (V

Ref

), for the conversion

requirements of the Codec section, and a bias
voltage (V

Bias

), for biasing the internal analog

sections, are both generated on-chip. V

Bias

is also

brought to an external pin so that it may be used for
biasing external gain setting amplifiers. A 0.1

capacitor must be connected from V

Bias

to analog

ground at all times. Likewise, although V

Ref

may only

be used internally, a 0.1

F capacitor from the V

Ref

pin to ground is required at all times. The analog
ground reference point for these two capacitors must
be physically the same point. To facilitate this the
V

Ref

and V

Bias

pins are situated on adjacent pins.

The transmit filter is designed to meet ITU-T G.714
specifications. An anti-aliasing filter is included. This
is a second order lowpass implementation with a
corner frequency at 25 kHz.

The receive filter is designed to meet ITU-T G.714
specifications. Filter response is peaked to
compensate for the sinx/x attenuation caused by the
8 kHz sampling rate.

Companding law selection for the Filter/Codec is
provided by the A/

companding control pin. Table

1 illustrates these choices.

Table 1: Law Selection

Analog Interfaces

Standard interfaces are provided by the MT91L62.
These are:

· The analog inputs (transmitter), pins AIN+/AIN-.

The maximum peak to peak input is 2.123Vpp

µ-

law across AIN+/AIN- and 2.2Vpp A-law

across these pins.

· The analog outputs (receiver), pins AOUT+/

AOUT-. This internally compensated fully
differential output driver is capable of driving a
load of 20k ohms.

PCM Serial Interface

A serial link is required to transport data between the
MT91L62 and an external digital transmission
device. The MT91L62 utilizes the strobed data
interface found on many standard Codec devices.
This interface is commonly referred to as Simple
Serial Interface (SSI).

The bit clock rate is selected by setting the CSL2-0
control pins as shown in Figure 2.

Quiet Code

The PCM serial port can be made to send quiet code
to the decoder and receive filter path by setting the
RxMute pin high. Likewise, the PCM serial port will
send quiet code in the transmit path when the

Code

ITU-T (G.711)

-Law

A-Law

+ Full Scale

1000 0000

1010 1010

+ Zero

1111 1111

1101 0101

-Zero

(quiet code)

0111 1111

0101 0101

- Full Scale

0000 0000

0010 1010

MT91L62

Advance Information

7-176

Table 2: Bit Clock Rate Selection

TxMute pin is high. When either of these pins are low
their respective paths function normally. The -Zero
entry of Table 1 is used for the quiet code definition.

SSI Mode

The SSI BUS consists of input and output serial data
streams named Din and Dout respectively, a Clock
input signal (CLOCKin), and a framing strobe input
(STB). A 4.096 MHz master clock is also required for
SSI operation if the bit clock is less than 512 kHz.
The timing requirements for SSI are shown in
Figures 5 & 6.

In SSI mode the MT91L62 supports only B-Channel
operation. Hence, in SSI mode transmit and receive
B-Channel data are always in the channel defined by
the STB input.

The data strobe input STB determines the 8-bit
timeslot used by the device for both transmit and
receive data. This is an active high signal with an 8
kHz repetition rate.

SSI operation is separated into two categories based
upon the data rate of the available bit clock. If the bit
clock is 512 kHz or greater then it is used directly by
the internal MT91L62 functions allowing
synchronous operation. If the available bit clock is
128 kHz or 256 kHz, then a 4096 kHz master clock is
required to derive clocks for the internal MT91L62
functions.

Applications where Bit Clock (BCL) is below 512 kHz
are designated as asynchronous. The MT91L62 will
re-align its internal clocks to allow operation when
the external master and bit clocks are asynchronous.
Control pins CSL2, CSL1 and CSL0 are used to
program the bit rates.

For synchronous operation, data is sampled from
Din, on the falling edge of BCL during the time slot
defined by the STB input. Data is made available, on

CSL

External

Clock Bit

Rate

(kHz)

CLOCKin

(kHz)

128

4096

256

4096

512

1536

2048

4096

Figure 3 - Audio Gain Partitioning

Serial

Port

Filter/Codec and Analog Interface

PCM

Receive

Filter Gain

0 dB

Receiver

Driver

0 dB

Aout +

Aout-

20k

Internal To Device

External To Device

Default Bypass

AIN+

AIN-

Transmit Gain

6 dB

PCM

Analog

Input

out

Decoder

Encoder

Advance Information

MT91L62

7-177

Dout, on the rising edge of BCL during the time slot
defined by the STB input. Dout is tri-stated at all
times when STB is not true. If STB is valid, then quiet
code will be transmitted on Dout during the valid
strobe period. There is no frame delay through the
PCM serial circuit for synchronous operation.

For asynchronous operation Dout and Din are as
defined for synchronous operation except that the
allowed output jitter on Dout is larger. This is due to
the resynchronization circuitry activity and will not
affect operation since the bit cell period at 128 kb/s
and 256 kb/s is relatively large. There is a one frame
delay through the PCM serial circuit for
asynchronous operation. Refer to the specifications
of Figures 5 & 6 for both synchronous and
asynchronous SSI timing.

PWRST

While the MT91L62 is held in PWRST no device
control or functionality is possible.

Applications

Figure 4 shows an application of the MT91L62 in a
line card.

Figure 4 - Line Card Application

0.1

VBias

+3V

Dout

Din

4
5

Frame Pulse

Clock

MT91L62

100k

CS2

CS1

CS0

TxMUTE

RxMUTE

Timing

Block

Output to Subscriber

Line Interface

Input from Subscriber

Line Interface

0.1

MT91L62

Advance Information

7-178

Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Note 1: Power delivered to the load is in addition to the bias current requirements.

Absolute Maximum Ratings

Parameter

Symbol

Min

Max

Units

Supply Voltage

- V

- 0.3

Voltage on any I/O pin

- 0.3

+ 0.3

Current on any I/O pin (transducers excluded)

Storage Temperature

- 65

+ 150

Power Dissipation (package)

750

Recommended Operating Conditions

- Voltages are with respect to V

unless otherwise stated

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

2.7

3.6

CMOS Input Voltage (high)

IHC

0.9*V

CMOS Input Voltage (low)

ILC

0.1*V

Operating Temperature

- 40

+ 85

Power Characteristics

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Static Supply Current (clock
disabled)

DDC1

Outputs unloaded, Input
signals static, not loaded

Dynamic Supply Current:
Total all functions enabled

DDFT

See Note 1.

Advance Information

MT91L62

7-179

DC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

* Note 1 - Magnitude measurement, ignore signs.

AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.

Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

DC Electrical Characteristics

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Input HIGH Voltage CMOS inputs

IHC

0.7*Vdd

Input LOW Voltage CMOS inputs

ILC

0.3*Vdd

VBias Voltage Output

Bias

Max. Load = 10k

Ref

Output Voltage

Ref

/2-1.1

No load

Input Leakage Current

0.1

to V

Positive Going Threshold
Voltage (PWRST only)
Negative Going Threshold
Voltage (PWRST only)
Hysteresis

T+

T-

2.2

0.65

0.7

Vdd=3V

Output HIGH Current

1.0

= 0.9*V

See Note 1

Output LOW Current

2.5

= 0.1*V

See Note 1

Output Leakage Current

0.01

OUT

= V

and V

Output Capacitance

Input Capacitance

Clockin Tolerance Characteristics

Characteristics

Min

Typ

Max

Units

Test Conditions

CLOCKin Frequency (Asynchronous
Mode)

4095.6

4096

4096.4

kHz

(i.e. 100 ppm)

MT91L62

Advance Information

7-180

AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

AC Characteristics

for A/D (Transmit) Path

- 0dBm0 = A

Lo3.17

- 3.17dB = 1.027V

rms

for

-Law and 0dBm0 =

Lo3.14

- 3.14dB =1.067V

rms

for A-Law, at the Codec. (V

Ref

=0.4 volts and V

Bias

=1.5 volts.)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Analog input equivalent to
overload decision

Li3.17

Li3.14

4.246

4.4

Vp-p
Vp-p

-Law

A-Law
Both at Codec

Absolute half-channel gain

to Dout

AX1

5.4

6.0

6.6

Transmit filter gain=0dB
setting.
@1020Hz

Gain tracking vs. input level
ITU-T G.714 Method 2

-0.3
-0.6
-1.6

0.3
0.6
1.6

dB
dB
dB

3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0

Signal to total Distortion vs. input
level.
ITU-T G.714 Method 2

35
29
24

dB
dB
dB

0 to -30 dBm0
-40 dBm0
-45 dBm0

Transmit Idle Channel Noise

-70.5

-69

dBrnC0

dBm0p

-Law

A-Law

Gain relative to gain at 1020Hz
<50Hz
60Hz
200Hz
300 - 3000 Hz
3000-3300 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
>4600 Hz

-0.25

-0.9
-0.9
-1.2

-45

-0.2
-0.6

-23
-41

-25
-30

0.0

0.25
0.25
0.25
0.25

-12.5

-25
-25

dB
dB
dB
dB
dB
dB
dB
dB
dB
dB

Absolute Delay

360

at frequency of minimum
delay

Group Delay relative to D

750
380
130
750

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

Power Supply Rejection

f=1020 Hz

PSSR

100mV peak signal on

-law

Advance Information

MT91L62

7-181

AC Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

AC Characteristics

for D/A (Receive) Path

- 0dBm0 = A

Lo3.17

- 3.17dB = 1.027V

rms

for

-Law and 0dBm0 =

Lo3.14

- 3.14dB =1.067V

rms

for A-Law, at the Codec. (V

Ref

=0.4 volts and V

Bias

=1.5 volts.)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Analog output at the Codec full
scale

Lo3.17

Lo3.14

4.183
4.331

Vp-p
Vp-p

-Law

A-Law

Analog output at the CODEC
full scale.

Lo3.17

Lo3.14

4.183
4.331

p-p

-Law

A-Law

Absolute half-channel gain.
Din to HSPKR

AR1

-0.6

0.6

@1020Hz

Gain tracking vs. input level
ITU-T G.714 Method 2

-0.3
-0.6
-1.6

0.3
0.6
1.6

dB
dB
dB

3 to -40 dBm0
-40 to -50 dBm0
-50 to -55 dBm0

Signal to total distortion vs. input
level.
ITU-T G.714 Method 2

35
29
24

dB
dB
dB

0 to -30 dBm0
-40 dBm0
-45 dBm0

Receive Idle Channel Noise

11.5

-80

-77

dBrnC0

dBm0p

-Law

A-Law

Gain relative to gain at 1020Hz
200 Hz
300 - 3000 Hz
3000 - 3300 Hz
3300 Hz
3400 Hz
4000 Hz
4600 Hz
>4600 Hz

-0.25
-0.90

-0.9
-0.9

-0.1
-0.5

-23
-41

0.25
0.25
0.25
0.25
0.25

-12.5

-25
-25

dB
dB
dB
dB
dB
dB
dB
dB

Absolute Delay

240

at frequency of min. delay

Group Delay relative to D

750
380
130
750

500-600 Hz
600 - 1000 Hz
1000 - 2600 Hz
2600 - 2800 Hz

Crosstalk

D/A to A/D

A/D to D/A

-90
-90

-74
-80

dB
dB

G.714.16
ITU-T

Electrical Characteristics

for Analog Outputs

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Output load impedance

20k

ohms

across AOUT

Allowable output capacitive
load

each pin:

AOUT+,

AOUT-

MT91L62

Advance Information

7-182

Electrical Characteristics are over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

NOTE 1: Not production tested, guaranteed by design.

Electrical Characteristics

for Analog Inputs

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Maximum input voltage without
overloading Codec

across AOUT+/AOUT-

IOLH

2.128

2.20

Vp-p
Vp-p

= 0

= 1

Input Impedance

Ain+/Ain- to V

AC Electrical Characteristics

- SSI BUS Synchronous Timing (see Figure 5)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

BCL Clock Period

BCL

244

1953

BCL=4096 kHz to 512 kHz

BCL Pulse Width High

BCLH

115

122

BCL=4096 kHz

BCL Pulse Width Low

BCLL

122

BCL=4096 kHz

BCL Rise/Fall Time

Note 1

Strobe Pulse Width

ENW

8 x t

BCL

Note 1

Strobe setup time before BCL falling

SSS

BCL

-80

Strobe hold time after BCL falling

SSH

BCL

-80

Dout High Impedance to Active Low
from Strobe rising

DOZL

=50 pF, R

=1K

Dout High Impedance to Active High
from Strobe rising

DOZH

=50 pF, R

=1K

10 Dout Active Low to High Impedance

from Strobe falling

DOLZ

=50 pF, R

=1K

11 Dout Active High to High Impedance

from Strobe falling

DOHZ

=50 pF, R

=1K

12 Dout Delay (high and low) from BCL

rising

=50 pF, R

=1K

13 Din Setup time before BCL falling

DIS

14 Din Hold Time from BCL falling

DIH

Advance Information

MT91L62

7-183

Figure 5 - SSI Synchronous Timing Diagram

Timing is over recommended temperature range & recommended power supply voltages.
Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

NOTE 1:Not production tested, guaranteed by design.

AC Electrical Characteristics

- SSI BUS Asynchronous Timing (note 1) (see Figure 6)

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Bit Cell Period

DATA

7812
3906

ns
ns

BCL=128 kHz
BCL=256 kHz

Frame Jitter

600

Bit 1 Dout Delay from STB
going high

dda1

+600

=50 pF, R

=1K

Bit 2 Dout Delay from STB
going high

dda2

600+

DATA

-T

600+

DATA

600 +

DATA

=50 pF, R

=1K

Bit n Dout Delay from STB
going high

ddan

600 +

(n-1) x

DATA

-T

600 +

(n-1) x

DATA

600 +

(n-1) x

DATA

=50 pF, R

=1K

n=3 to 8

Bit 1 Data Boundary

DATA1

DATA

-T

DATA

Din Bit n Data Setup time from
STB rising

DATA

+500ns-T

+(n-1) x

DATA

n=1-8

Din Data Hold time from STB
rising

DATA

+500ns+T

+(n-1) x

DATA

(BCL)

Din

Dout

STB

70%

30%

70%

30%

70%

30%

70%

30%

BCLH

BCLL

DIS

DIH

DOZL

BCL

DOZH

SSS

ENW

SSH

DOLZ

DOHZ

NOTE:

Levels refer to % V

(CMOS I/O)

CLOCKin

Package Outlines

Small Shrink Outline Package (SSOP) - N Suffix

Pin 1

Dim

20-Pin

24-Pin

28-Pin

48-Pin

Min

Max

Min

Max

Min

Max

Min

Max

0.079

(2)

0.079

(2)

0.079

(2)

0.095

(2.41)

0.110

(2.79)

0.002

(0.05)

0.002

(0.05)

0.002

(0.05)

0.008

(0.2)

0.016

(0.406)

0.0087

(0.22)

0.013

(0.33)

0.0087

(0.22)

0.013

(0.33)

0.0087

(0.22)

0.013

(0.33)

0.008

(0.2)

0.0135

(0.342)

0.008

(0.21)

0.008

(0.21)

0.008

(0.21)

0.010

(0.25)

0.27

(6.9)

0.295

(7.5)

0.31

(7.9)

0.33

(8.5)

0.39

(9.9)

0.42

(10.5)

0.62

(15.75)

0.63

(16.00)

0.2

(5.0)

0.22

(5.6)

0.2

(5.0)

0.22

(5.6)

0.2

(5.0)

0.22

(5.6)

0.291

(7.39)

0.299

(7.59)

0.025 BSC

(0.635 BSC)

0.025 BSC

(0.635 BSC)

0.025 BSC

(0.635 BSC)

0.025 BSC

(0.635 BSC)

0.065

(1.65)

0.073

(1.85)

0.065

(1.65)

0.073

(1.85)

0.065

(1.65)

0.073

(1.85)

0.089

(2.26)

0.099

(2.52)

0.29

(7.4)

0.32

(8.2)

0.29

(7.4)

0.32

(8.2)

0.29

(7.4)

0.32

(8.2)

0.395

(10.03)

0.42

(10.67)

0.022

(0.55)

0.037

(0.95)

0.022

(0.55)

0.037

(0.95)

0.022

(0.55)

0.037

(0.95)

0.02

(0.51)

0.04

(1.02)

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) Ref. JEDEC Standard M0-150/M0118 for 48 Pin
5) A & B Maximum dimensions include allowable mold flash

General-11

Package Outlines

Lead SOIC Package - S Suffix

NOTES: 1. Controlling dimensions in parenthesis ( ) are in millimeters.

2. Converted inch dimensions are not necessarily exact.

DIM

16-Pin

18-Pin

20-Pin

24-Pin

28-Pin

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

0.093

(2.35)

0.104

(2.65)

0.093

(2.35)

0.104

(2.65)

0.093

(2.35)

0.104

(2.65)

0.093

(2.35)

0.104

(2.65)

0.093

(2.35)

0.104

(2.65)

0.004

(0.10)

0.012

(0.30)

0.004

(0.10)

0.012

(0.30)

0.004

(0.10)

0.012

(0.30)

0.004

(0.10)

0.012

(0.30)

0.004

(0.10)

0.012

(0.30)

0.013

(0.33)

0.020

(0.51)

0.013

(0.33)

0.030

(0.51)

0.013

(0.33)

0.020

(0.51)

0.013

(0.33)

0.020

(0.51)

0.013

(0.33)

0.020

(0.51)

0.009

(0.231)

0.013

(0.318)

0.009

(0.231)

0.013

(0.318)

0.009

(0.231)

0.013

(0.318)

0.009

(0.231)

0.013

(0.318)

0.009

(0.231)

0.013

(0.318)

0.398

(10.1)

0.413

(10.5)

0.447

(11.35)

0.4625

(11.75)

0.496

(12.60)

0.512

(13.00)

0.5985

(15.2)

0.614

(15.6)

0.697

(17.7)

0.7125

(18.1)

0.291

(7.40)

0.299

(7.40)

0.291

(7.40)

0.299

(7.40)

0.291

(7.40)

0.299

(7.40)

0.291

(7.40)

0.299

(7.40)

0.291

(7.40)

0.299

(7.40)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.050 BSC

(1.27 BSC)

0.394

(10.00)

0.419

(10.65)

0.394

(10.00)

0.419

(10.65)

0.394

(10.00)

0.419

(10.65)

0.394

(10.00)

0.419

(10.65)

0.394

(10.00)

0.419

(10.65)

0.016

(0.40)

0.050

(1.27)

0.016

(0.40)

0.050

(1.27)

0.016

(0.40)

0.050

(1.27)

0.016

(0.40)

0.050

(1.27)

0.016

(0.40)

0.050

(1.27)

Pin 1

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)
4) A & B Maximum dimensions include allowable mold flash

4 mils (lead coplanarity)

General-7

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Suffix

NOTE: Controlling dimensions in parenthesis ( ) are in millimeters.

DIM

8-Pin

16-Pin

18-Pin

20-Pin

Plastic

Min

Max

Min

Max

Min

Max

Min

Max

0.210 (5.33)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.115 (2.92)

0.195 (4.95)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.045 (1.14)

0.070 (1.77)

0.008

(0.203)

0.014 (0.356)

0.008 (0.203)

0.014(0.356)

0.008 (0.203)

0.014 (0.356)

0.008 (0.203)

0.014 (0.356)

0.355 (9.02)

0.400 (10.16)

0.780 (19.81)

0.800 (20.32)

0.880 (22.35)

0.920 (23.37)

0.980 (24.89)

1.060 (26.9)

0.005 (0.13)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.300 (7.62)

0.325 (8.26)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.240 (6.10)

0.280 (7.11)

0.100 BSC (2.54)

0.300 BSC (7.62)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.115 (2.92)

0.150 (3.81)

0.430 (10.92)

0.060 (1.52)

n-2 n-1 n

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)

General-8

Package Outlines

Plastic Dual-In-Line Packages (PDIP) - E Suffix

DIM

22-Pin

24-Pin

28-Pin

40-Pin

Plastic

Min

Max

Min

Max

Min

Max

Min

Max

0.210 (5.33)

0.250 (6.35)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.125 (3.18)

0.195 (4.95)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.014 (0.356)

0.022 (0.558)

0.045 (1.15)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.030 (0.77)

0.070 (1.77)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

0.008 (0.204)

0.015 (0.381)

1.050 (26.67)

1.120 (28.44)

1.150 (29.3)

1.290 (32.7)

1.380 (35.1)

1.565 (39.7)

1.980 (50.3)

2.095 (53.2)

0.005 (0.13)

0.390 (9.91)

0.430 (10.92)

0.600 (15.24)

0.670 (17.02)

0.600 (15.24)

0.670 (17.02)

0.600 (15.24)

0.670 (17.02)

0.290 (7.37)

.330 (8.38)

0.330 (8.39)

0.380 (9.65)

0.485 (12.32)

0.580 (14.73)

0.485 (12.32)

0.580 (14.73)

0.485 (12.32)

0.580 (14.73)

0.246 (6.25)

0.254 (6.45)

0.100 BSC (2.54)

0.400 BSC (10.16)

0.600 BSC (15.24)

0.300 BSC (7.62)

0.430 (10.92)

0.115 (2.93)

0.160 (4.06)

0.115 (2.93)

0.200 (5.08)

0.115 (2.93)

0.200 (5.08)

0.115 (2.93)

0.200 (5.08)

n-2 n-1 n

Notes:
1) Not to scale
2) Dimensions in inches
3) (Dimensions in millimeters)

Shaded areas for 300 Mil Body Width 24 PDIP only

TECHNICAL DOCUMENTATION - NOT FOR RESALE

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Tel: +1 (613) 592 2122

Fax: +1 (613) 592 6909

North America

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Europe, Middle East,

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Tel: +65 333 6193

and Africa (EMEA)

Fax: +1 (770) 631 8213

Fax: +65 333 6192

Tel: +44 (0) 1793 518528

Fax: +44 (0) 1793 518581

http://www.mitelsemi.com

Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively "Mitel") is believed to be reliable. However, Mitel assumes no
liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or
service conveys any license, either express or implied, under patents or other intellectual property rights owned by Mitel or licensed from third parties by Mitel, whatsoever.
Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.

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publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
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any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel's
conditions of sale which are available on request.

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