Features

Contains two echo cancellers: 112ms acoustic
echo canceller + 16ms line echo canceller

Works with low cost voice codec. ITU-T G.711
or signed mag

/A-Law, or linear 2's comp

Each port may operate in different format

Advanced NLP design - full duplex speech with
no switched loss on audio paths

Fast re-convergence time: tracks changing
echo environment quickly

Adaptation algorithm converges even during
Double-Talk

Designed for exceptional performance in high
background noise environments

Provides protection against narrow-band signal
divergence

Howling prevention stops uncontrolled
oscillation in high loop gain conditions

Offset nulling of all PCM channels

Serial micro-controller interface

ST-BUS, GCI, or variable-rate SSI PCM
interfaces

User gain control provided for speaker path
(-24dB to +21dB in 3dB steps)

AGC on speaker path

Handles up to 0 dB acoustic echo return loss
and 0dB line ERL

Transparent data transfer and mute options

20 MHz master clock operation

Low power mode during PCM Bypass

Bootloadable for future factory software
upgrades

2.7V to 3.6V supply voltage; 5V-tolerant inputs

Applications

Full duplex speaker-phone for digital telephone

Echo cancellation for video conferencing

Handsfree in automobile environment

Full duplex speaker-phone for PC

Figure 1 - Functional Block Diagram

Rout

MD1

MD2

PORT 2

Sin

Line ECho Path

Micro

Interface

Program

RAM

Program

ROM

DS5068

ISSUE3

July 1999

Ordering Information

MT93L16AQ

36 Pin QSOP

-40

C to + 85

CMOS

MT93L16

Low-Voltage Acoustic Echo Canceller

Preliminary Information

FORMAT

inear/

/A-Law

Offset

Null

Linear

/A-Law/

Linear/

/A-Law

Adaptive

Filter

Offset

Null

VDD

VSS

RESET

F0i

BCLK/C4i

MCLK

Sout

Rin

DATA1

DATA2

SCLK

ENA2

LAW

AGC

User
Gain

ADV

-24 -> +21dB

NLP

ADV
NLP

Linear

/A-Law/

Howling

Controller

PORT 1

NBSD

Adaptive

Filter

UNIT

CONTROL

Detector

Talk

Double

NBSD

ENA1

Limiter

ACOUSTIC ECHO PATH

MT93L16

Preliminary Information

Figure 2 - Pin Connections

Pin Description

Pin #

Name

Description

ENA1

SSI Enable Strobe / ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions
depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present
for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits
wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125
microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1 pin, selects the
proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description).

MD1

ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in
conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS
and GCI Operation description). Connect this pin to Vss in SSI mode.

ENA2

SSI Enable Strobe / ST-BUS & GCI Mode for Sin/Rout (Input).This pin has dual functions
depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel
enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins.
Strobe period is 125 microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2
pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description).

MD2

ST-BUS & GCI Mode for Sin/Rout (Input).When in ST-BUS or GCI operation, this pin in
conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and
GCI Operation description). Connect this pin to Vss in SSI mode.

Rin

Receive PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data
may be in either companded or 2's complement linear format. This is the Receive Input
channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-
BUS timing requirements.

Sin

Send PCM Signal Input (Input). 128 kbit/s to 4096 kbit/s serial PCM input stream. Data may
be in either companded or 2's complement linear format. This is the Send Input channel
(from the microphone). Data bits are clocked in following SSI,GCI or ST-BUS timing
requirements.

Internal Connection (Input): Must be tied to Vss.

MCLK

Master Clock (Input): Nominal 20 MHz Master Clock input (may be asynchronous relative
to 8KHz frame signal.) Tie together with MCLK2 (pin 33).

9,10,11

Internal Connection (Input): Must be tied to Vss.

LAW

Law Select (Input). When low, selects

µ-

Law companded PCM. When high, selects A-

Law companded PCM. This control is for both serial pcm ports.

FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects

ITU-T (G.711) PCM code. This control is for both serial pcm ports.

1
2
3
4

5
6
7
8
9
10
11
12
13
14

28
27
26
25

24
23
22
21

DATA2

VDD
NC

DATA1

SCLK

Sout

Rout

BCLK/C4i

Sin

Rin

MD2

MD1

F0i

FORMAT

LAW

ENA1

RESET

ENA2

MCLK

QSOP

32
31

VSS

30
29

VSS2

VDD2

MCLK2

Preliminary Information

MT93L16

Notes: 1. All inputs have CMOS compatible, 5V-tolerant logic levels.
2. All outputs have CMOS logic levels. Rout, Sout, and DATA1 are 5V-tolerant when tristated (to withstand other 5V drivers

on a shared bus).

Glossary

Double-Talk

Simultaneous signals present on Rin and Sin.

Near-end Single-Talk

Signals only present at Sin input.

Far-end Single-Talk

Signals only present at Rin input.

ADV NLP

Advanced Non-Linear-Processor

Howling

Oscillation caused by feedback from acoustic and line echo paths

Narrowband

Any mono or dual sinusoidal signals

NBSD

Narrow Band Signal Detector

Noise-Gating

Audible switching of background noise

Offset Nulling

Removal of DC component

Reverberation time

The time duration before an echo level decays to -60dBm

ERL

Echo Return Loss

ERLE

Echo Return Loss Enhancement

AGC

Automatic Gain Control

RESET

Reset / Power-down (Input). An active low resets the device and puts the MT93L16 into a
low-power stand-by mode.

15, 16

No Connect (Output). These pins should be left un-connected.

SCLK

Serial Port Synchronous Clock (Input). Data clock for the serial microport interface.

Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low.

DATA2

Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin
is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and
must be tied to Vss or Vdd.

DATA1

Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1
pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for
transmitting and receiving data.

No Connect (Output). This pin should be left un-connected.

VDD

Positive Power Supply (Input). Nominally 3.3 volts.

Sout

Send PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2's complement linear PCM format. This is the Send
Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked
out following SSI, ST-BUS, or GCI timing requirements.

Rout

Receive PCM Signal Output (Output). 128 kbit/s to 4096 kbit/s serial PCM output stream.
Data may be in either companded or 2's complement linear PCM format. This is the Receive
out signal after line echo cancellation non-linear processing, AGC, and gain control. Data bits
are clocked out following SSI, ST-BUS, or GCI timing requirements.

F0i

Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high)
frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.

BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit

clock. This clock must be synchronous with ENA1, and ENA2 enable strobes.
In ST-BUS or GCI operation, C4i pin must be connected to the 4.096MHz (C4) system clock.

27, 28

Internal Connection (Input). Tie to Vss.

VSS2

Digital Ground (Input): Nominally 0 volts.

VDD2

Positive Power Supply (Input): Nominally 3.3 volts (tie together with VDD, pin 22).

VSS

Digital Ground (Input): Nominally 0 volts (tie together with VSS2, pin 29).

No Connect (Output). This pin should be left un-connected.

MCLK2

Master Clock (Input): Nominal 20MHz master clock (tie together with MCLK, pin 8).

34,35,36

Internal Connection (Input). Tie to Vss.

Pin Description (continued)

Pin #

Name

Description

MT93L16

Preliminary Information

Functional Description

The MT93L16 device contains two echo cancellers,
as well as the many control functions necessary to
operate the echo cancellers. One canceller is for
acoustic speaker to microphone echo, and one for
line echo cancellation. The MT93L16 provides clear
signal transmission in both audio path directions to
ensure reliable voice communication, even with low
level signals. The MT93L16 does not use variable
attenuators during double-talk or single-talk periods
of speech, as do many other acoustic echo
cancellers for speaker-phones. Instead, the
MT93L16 provides high performance full-duplex
operation similar to network echo cancellers, so that
users experience clear speech and un-interrupted
background signals during the conversation. This
prevents subjective sound quality problems
associated with "noise gating" or "noise contrasting".

The MT93L16 uses an advanced adaptive filter
algorithm that is double-talk stable, which means
that convergence takes place even while both parties
are talking

. This algorithm allows continual tracking

of changes in the echo path, regardless of double-
talk, as long as a reference signal is available for the
echo canceller.

(1. Patent Pending)

The echo tail cancellation capability of the acoustic
echo canceller has been sized appropriately (112ms)
to cancel echo in an average sized office with a
reverberation time of less than 112ms. The 16ms line
echo canceller is sufficient to ensure a high ERLE for
most line circuits.

In addition to the echo cancellers, the following
functions are supported:
·

Control of adaptive filter convergence speed
during periods of double-talk, far end single-
talk, and near-end echo path changes.

Control of Non-Linear Processor thresholds for
suppression of residual non-linear echo.

Howling detector to identify when instability is
starting to occur, and to take action to prevent
oscillation.

Narrow-Band Detector for preventing adaptive
filter divergence caused by narrow-band signals

Offset Nulling filters for removal of DC
components in PCM channels.

Limiters that introduce controlled saturation
levels.

Serial controller interface compatible with
Motorola, National and Intel microcontrollers.

PCM encoder/decoder compatible with

/A-

Law ITU-T G.711,

/A-Law Sign-Mag or linear

2's complement coding.

Automatic gain control on the receive speaker
path.

Adaptation Speed Control

The adaptation speed of the acoustic echo canceller
is designed to optimize the convergence speed
versus divergence caused by interfering near-end
signals. Adaptation speed algorithm takes into
account many different factors such as relative
double-talk condition, far end signal power, echo
path change, and noise levels to achieve fast
convergence.

Advanced Non-Linear Processor (ADV-NLP)

(2. Patent Pending)

After echo cancellation, there is likely to be residual
echo which needs to be removed so that it will not be
audible. The MT93L16 uses an NLP to remove low
level residual echo signals which are not comprised
of background noise. The operation of the NLP
depends upon a dynamic activation threshold, as
well as a double-talk detector which disables the
NLP during double-talk periods.

The MT93L16 keeps the perceived noise level
constant, without the need for any variable
attenuators or gain switching that causes audible
"noise gating". The noise level is constant and
identical to the original background noise even when
the NLP is activated.

For each audio path, the NLP can be disabled by
setting the NLP- bit to 1 in the LEC or AEC control
registers.

Narrow Band Signal Detector (NBSD)

(3. Patent Pending)

Single or multi-frequency tones (e.g. DTMF, or
signalling tones) present in the reference input of an
echo canceller for a prolonged period of time may
cause the adaptive filter to diverge. The Narrow
Band Signal Detector (NBSD) is designed to prevent
this divergence by detecting single or multi-tones of
arbitrary frequency, phase, and amplitude. When
narrow band signals are detected, the filter
adaptation process is stopped but the echo canceller
continues to cancel echo.

The NBSD can be disabled by setting the NB- bit to 1
in the MC control registers.

Preliminary Information

MT93L16

Howling Detector (HWLD)

(4. Patent Pending)

The Howling detector is part of an Anti-Howling
control, designed to prevent oscillation as a result of
positive feedback in the audio paths.

The HWLD can be disabled by setting the AH- bit to
1 in the (MC) control register.

Offset Null Filter

To ensure robust performance of the adaptive filters
at all times, any DC offset that may be present on
either the Rin signal or the Sin signal, is removed by
highpass filters. These filters have a corner
frequency placed at 40Hz.

The offset null filters can be disabled by setting the
HPF- bit to 1 in the LEC or AEC control registers.

Limiters

To prevent clipping in the echo paths, two limiters
with variable thresholds are provided at the outputs.

The Rout limiter threshold is in Rout Limiter Register
1 and 2. The Sout limiter threshold is in Sout Limiter
Register. Both output limiters are always enabled.

User Gain

The user gain function provides the ability for users
to adjust the audio gain in the receive path (speaker
path). This gain is adjustable from -24dB to +21dB in
3dB steps. It is important to use ONLY this user gain
function to adjust the speaker volume. The user gain
function in the MT93L16 is optimally placed between
the two echo cancellers such that no reconvergence
is necessary after gain changes.

The gain can be accessed through Receive Gain
Control Register.

AGC

The AGC function is provided to limit the volume in
the speaker path. The gain of the speaker path is
automatically reduced during the following
conditions:
·

When clipping of the receive signal occurs.

When initial convergence of the acoustic echo
canceller detects unusually large echo return.

When howling is detected.

The AGC can be disabled by setting the AGC- bit to
1 in MC control register.

Mute Function

A pcm mute function is provided for independent
control of the Receive and Send audio paths. Setting
the MUTE_R or MUTE_S bit in the MC register,
causes quiet code to be transmitted on the Rout or
Sout paths respectively.

Quiet code is defined according to the following
table.

Bypass Control

A PCM bypass function is provided to allow
transparent transmission of pcm data through the
MT93L16. When the bypass function is active, pcm
data passes transparently from Rin to Rout and from
Sin to Sout, with bit-wise integrity preserved.

When the Bypass function is selected, most internal
functions are powered down to provide low power
consumption.

The BYPASS control bit is located in the main control
MC register.

Adaptation Enable/Disable

Adaptation control bits are located in the AEC and
LEC control registers. When the ADAPT- bit is set to
1, the adaptive filter is frozen at the current state. In
this state, the device continues to cancel echo with
the current echo model.

When the ADAPT- bit is set to 0, the adaptive filter is
continually updated. This allows the echo canceller
to adapt and track changes in the echo path. This is
the normal operating state.

MT93L16 Throughput Delay

In all modes, voice channels always have 2 frames of
delay. In ST-BUS/GCI operation, the D and C
channels have a delay of one frame.

LINEAR

16 bits

2's

complement

SIGN/

MAGNITUDE

-Law

A-Law

CCITT (G.711)

-Law

A-Law

+Zero

(quiet code)

0000h

80h

FFh

D5h

Table 1 - Quiet PCM Code Assignment

MT93L16

Preliminary Information

Power Down / Reset

Holding the RESET pin at logic low will keep the
MT93L16 device in a power-down state. In this state
all internal clocks are halted, and the DATA1, Sout
and Rout pins are tristated.

The user should hold the RESET pin low for at least
200 msec following power-up. This will insure that
the device powers up in a proper state. Following
any return of RESET to logic high, the user must wait
for 8 complete 8 KHz frames prior to writing to the
device registers. During this time, the initialization
routines will execute and set the MT93L16 to default
operation (program execution from ROM using
default register values).

PCM Data I/O

The PCM data transfer for the MT93L16 is provided
through two PCM ports. One port consists of Rin and
Sout pins while the second port consists of Sin and
Rout pins. The data are transferred through these
ports according to either ST-BUS, GCI, or SSI
conventions, and the device automatically detects
the correct convention. The device determines the
convention by monitoring the signal applied to the
F0i pin. When a valid ST-BUS (active low) frame
pulse is applied to the F0i pin, the MT93L16 will
assume ST-BUS operation. When a valid GCI (active

high) frame pulse is applied to the F0i pin, the device
will assume GCI operation. If F0i is tied continuously
to Vss, the device will assume SSI operation.
Figures 11 to 13 show timing diagrams of these 3
PCM-interface operation conventions.

ST-BUS and GCI Operation

The ST-BUS PCM interface conforms to Mitel's ST-
BUS standard, with an active-low frame pulse. Input
data is clocked in by the rising edge of the bit clock
(C4i) three-quarters of the way into the bitcell, and
output data bit boundaries (Rout, Sout) occur every
second falling edge of the bit clock (see Figure 11.)
The GCI PCM interface corresponds to the GCI
standard commonly used in Europe, with an active-
high frame pulse. Input data is clocked in by the
falling edge of the bit clock (C4i) three-quarters of
the way into the bitcell, and output data bit
boundaries (Rout, Sout) occur every second rising
edge of the bit clock (see Figure 12.)

Either of these interfaces (STBUS or GCI) can be
used to transport 8 bit companded PCM data (using
one timeslot) or 16 bit 2's complement linear PCM
data (using two timeslots). The MD1/ENA1 pins
select the timeslot on the Rin/Sout port while the
MD2/ENA2 pin selects the timeslot on the Sin/Rout
port, as in Table 2. Figures 3 to 6 illustrate the
timeslot allocation for each of these four modes.

Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)

C4i

F0i (ST-BUS)

Sin

Rout

Rin

Sout

7 6 5 4 3 2 1 0

outputs = High impedance

inputs = don't care

In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1
and PORT2 into different modes.

PORT1

PORT2

F0i (GCI)

start of frame (stbus & GCI)

Preliminary Information

MT93L16

Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2)

Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3)

C4i

F0i (ST-BUS)

Sin

Rout

Rin

Sout

7 6 5 4 3 2 1 0

In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can configure PORT1
and PORT2 into different modes.

PORT1

PORT2

outputs = High impedance

inputs = don't care

F0i (GCI)

start of frame (stbus & GCI)

C4i

F0i (ST-BUS)

Rin

Sout

Sin

Rout

PORT1

PORT2

indicates that an input channel is bypassed to an output channel

ST-BUS/GCI Mode 3 supports connection to 2B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller
(EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be configured in Mode 3.

outputs = High impedance

inputs = don't care

7 6 5 4 3 2 1 0

F0i (GCI)

start of frame (stbus & GCI)

MT93L16

Preliminary Information

Table 2 - ST-BUS & GCI Mode Select

SSI Operation

The SSI PCM interface consists of data input pins
(Rin, Sin), data output pins (Sout, Rout), a variable
rate bit clock (BCLK), and two enable pins (ENA1,
ENA2) to provide strobes for data transfers. The
active high enable may be either 8 or 16 BCLK
cycles in duration. Automatic detection of the data
type (8 bit companded or 16 bit 2's complement
linear) is accomplished internally. The data type
cannot change dynamically from one frame to the
next.

In SSI operation, the frame boundary is determined
by the rising edge of the ENA1 enable strobe (see
Figure 7). The other enable strobe (ENA2) is used
for parsing input/output data and it must pulse within
125 microseconds of the rising edge of ENA1.

In SSI operation, the enable strobes may be a mixed
combination of 8 or 16 BCLK cycles allowing the
flexibility to mix 2's complement linear data on one
port (e.g., Rin/Sout) with companded data on the
other port (e.g., Sin/Rout).

Table 3 - SSI Enable Strobe Pins

PCM Law and Format Control (LAW, FORMAT)

The PCM companding/coding law used by the
MT93L16 is controlled through the LAW and
FORMAT pins. ITU-T G.711 companding curves for

-Law and A-Law are selected by the LAW pin. PCM

coding ITU-T G.711 and Sign-Magnitude are
selected by the FORMAT pin. See Table 4.

PORT1

Rin/Sout

ST-BUS/GCI Mode

Selection

PORT2

Sin/Rout

Enable Pins

MD1

ENA1

MD2

ENA2

Mode 1. 8 bit companded PCM I/O on
timeslot 0

Mode 2. 8 bit companded PCM I/O on
timeslot 2.

Mode 3. 8 bit companded PCM I/O on
timeslot 2. Includes D & C channel
bypass in timeslots 0 & 1.

Mode 4. 16 bit 2's complement linear
PCM I/O on timeslots 0 & 1.

Enable Strobe Pin

Designated PCM I/O Port

ENA1

Line Side Echo Path (PORT 1)

ENA2

Acoustic Side Echo Path (PORT 2)

Figure 6 - ST-BUS and GCI 16-Bit 2's complement linear PCM I/O (Mode 4)

C4i

F0i (stbus)

Rin

Sout

7 6 5 4 3 2 1 0

Sin

Rout

PORT1

PORT2

S 14 13 12 11 10 9 8

ST-BUS/GCI Mode 4 allows 16 bit 2's complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and
PORT2 need not necessarily both be in mode 4.

outputs = High impedance

inputs = don't care

7 6 5 4 3 2 1 0

S 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

S 14 13 12 11 10 9 8

7 6 5 4 3 2 1 0

S 14 13 12 11 10 9 8

F0i (GCI)

start of frame (stbus & GCI)

Preliminary Information

MT93L16

Linear PCM

The 16-bit 2's complement PCM linear coding
permits a dynamic range beyond that which is
specified in ITU-T G.711 for companded PCM. The
echo-cancellation algorithm will accept 16 bits 2's
complement linear code which gives a maximum
signal level of +15dBm0.

Bit Clock (BCLK/C4i )

The BCLK/C4i pin is used to clock the PCM data for
GCI and ST-BUS (C4i) interfaces, as well as for the
SSI (BCLK) interface.

In SSI operation, the bit rate is determined by the
BCLK frequency. This input must contain either eight
or sixteen clock cycles within the valid enable strobe
window. BCLK may be any rate between 128 KHz to
4.096 MHz and can be discontinuous outside of the
enable strobe windows defined by ENA1, ENA2 pins.
Incoming PCM data (Rin, Sin) are sampled on the
falling edge of BCLK while outgoing PCM data (Sout,
Rout) are clocked out on the rising edge of BCLK.
See Figure 13.

In ST-BUS and GCI operation, connect the system
C4 (4.096MHz) clock to the C4i pin.

Master Clock (MCLK)

A nominal 20MHz, continuously-running master
clock (MCLK) is required. MCLK may be
asynchronous with the 8KHz frame.

PCM Code

Sign-Magnitude

FORMAT=0

ITU-T (G.711)

FORMAT=1

/A-LAW

LAW = 0 or 1

-LAW

LAW = 0

A-LAW

LAW =1

+ Full Scale

1111 1111

1000 0000

1010 1010

+ Zero

1000 0000

1111 1111

1101 0101

- Zero

0000 0000

0111 1111

0101 0101

- Full Scale

0111 1111

0000 0000

0010 1010

Table 4 - Companded PCM

Figure 7 - SSI Operation

BCLK

ENA1

Rin

Sout

8 or 16 bits

PORT1

PORT2

8 or 16 bits

ENA2

Sin

Rout

Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate
with 16-bit enable strobes.

outputs = High impedance

inputs = don't care

start of frame (SSI)

MT93L16

Preliminary Information

Microport

The serial microport provides access to all MT93L16
internal read and write registers, plus write-only
access to the bootloadable program RAM (see next
section for bootload description.) This microport is
compatible with Intel MCS-51 (mode 0), Motorola
SPI (CPOL=0, CPHA=0), and National
Semiconductor Microwire specifications. The
microport consists of a transmit/receive data pin
(DATA1), a receive data pin (DATA2), a chip select
pin (CS) and a synchronous data clock pin (SCLK).

The MT93L16 automatically adjusts its internal
timing and pin configuration to conform to Intel or
Motorola/National requirements. The microport
dynamically senses the state of the SCLK pin each
time CS pin becomes active (i.e. high to low
transition). If SCLK pin is high during CS activation,
then Intel mode 0 timing is assumed. In this case
DATA1 pin is defined as a bi-directional (transmit/
receive) serial port and DATA2 is internally
disconnected. If SCLK is low during CS activation,
then Motorola/National timing is assumed and
DATA1 is defined as the data transmit pin while
DATA2 becomes the data receive pin. The MT93L16
supports Motorola half-duplex processor mode
(CPOL=0 and CPHA=0). This means that during a
write to the MT93L16, by the Motorola processor,
output data from the DATA1 pin must be ignored.
This also means that input data on the DATA2 pin is
ignored by the MT93L16 during a valid read by the
Motorola processor.

All data transfers through the microport are two bytes
long. This requires the transmission of a Command/
Address byte followed by the data byte to be written
to or read from the addressed register. CS must
remain low for the duration of this two-byte transfer.
As shown in Figures 8 and 9, the falling edge of CS
indicates to the MT93L16 that a microport transfer is
about to begin. The first 8 clock cycles of SCLK after
the falling edge of CS are always used to receive the
Command/Address byte from the microcontroller.
The Command/Address byte contains information
detailing whether the second byte transfer will be a
read or a write operation and at what address. The
next 8 clock cycles are used to transfer the data byte
between the MT93L16 and the microcontroller. At the
end of the two-byte transfer, CS is brought high again
to terminate the session. The rising edge of CS will
tri-state the DATA1 pin. The DATA1 pin will remain tri-
stated as long as CS is high.

Intel processors utilize Least Significant Bit (LSB)
first transmission while Motorola/National processors
use Most Significant Bit (MSB) first transmission.

The MT93L16 microport automatically
accommodates these two schemes for normal data
bytes. However, to ensure timely decoding of the
R/W and address information, the Command/
Address byte is defined differently for Intel and
Motorola/National operations. Refer to the relative
timing diagrams of Figure 8 and Figure 9. Receive
data bits are sampled on the rising edge of SCLK
while transmit data is clocked out on the falling edge
of SCLK. Detailed microport timing is shown in
Figure 14 and Figure 15.

Bootload Process and Execution from RAM

A bootloadable program RAM (BRAM) is available on
the MT93L16 to support factory-issued software
upgrades to the built-in algorithm. To make use of
this bootload feature, users must include 4096 X
8bits of memory in their microcontroller system (i.e.
external to the MT93L16), from which the MT93L16
can be bootloaded. Registers and program data are
loaded into the MT93L16 in the same fashion via the
serial microport. Both employ the same command /
address / data byte specification described in the
previous section on serial microport. Either intel or
motorola mode may be transparently used for
bootloading. There are also two registers relevant to
bootloading (BRC=control and SIG=signature, see
Register Summary). The effect of these register
values on device operation is summarized in Table 5.

Bootload mode is entered and exited by writing to the
bootload bit in the Bootload RAM Control (BRC)
register at address 3fh (see Register Summary).
During bootload mode, any serial microport "write"
(R/W command bit =0) to an address other than that
of the BRC register will contribute to filling the
program BRAM. Call these transactions "BRAM-fill"
writes. Although a command/address byte must still
precede each data byte (as described for the serial
microport), the values of the address fields for these
"BRAM-fill" writes are ignored (except for the value
3fh, which designates the BRC register.) Instead,
addresses are internally generated by the MT93L16
for each "BRAM-fill" write. Address generation for
"BRAM-fill" writes resumes where it left off following
any read transaction while bootload mode is
enabled. The first 4096 such "BRAM-fill" writes while
bootload is enabled will load the memory, but further
ones after that are ignored. Following the write of
the first 4096 bytes, the program BRAM will be filled.
Before bootload

mode is disabled, it is

recommended that users then read back the value
from the signature register (SIG) and compare it to
the one supplied by the factory along with the code.
Equality verifies that the correct data has been
loaded. The signature calculation uses an 8-bit MISR
which only incorporates input from "BRAM-fill"

Preliminary Information

MT93L16

writes. Resetting the bootload bit (C

) in the BRC

register to 0 (see Register Summary) exits bootload
mode, resetting the signature (SIG) register and
internal address generator for the next bootload. A
hardware reset (RESET=0) similarly returns the
MT93L16 to the ready state for the start of a
bootload.

Once the program has been loaded, to begin
execution from RAM, bootload mode must be
disabled (BOOT bit, C

=0) and execution from RAM

enabled (RAM_ROMb bit, C

=1) by setting the

appropriate bits in the BRC register. During the
bootload process, however, ROM program execution
(RAM_ROMb bit, C

=0) should be selected. See

Table 5 for the effect of the BRC register settings on
Microport accesses and on program execution.

Following program loading and enabling of execution
from RAM, it is recommended that users set the
software reset bit in the Main Control (MC) register,
to ensure that the device updates the default register
values to those of the new program in RAM. Note: it
is important to use a software reset rather than a
hardware (RESET=0) reset, as the latter will return
the device to its default settings (which includes
execution from program ROM instead of RAM.)

To verify which code revision is currently running,
users can access the Firmware Revision Code
(FRC) register (see Register Summary). This
register reflects the identity code (revision number)
of the last program to run register initialization (which
follows a software or hardware reset.)

Table 5 - Bootload RAM Control (BRC) Register States

Note: bits C

are reserved, and must be set to zero.

FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM

BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM)

BRC Register

Bits

X 1 0 0

R/W

Address

Data

3fh

(= 1 1 1 1 1 1 b)

Writes "data" to BRC reg.

- Bootload frozen; BRAM contents are NOT affected.

other than 3fh

Writes "data" to next byte in BRAM (bootloading.)

1 x x x x x b

Reads back "data" = BRC reg value.

- Bootload frozen; BRAM contents are NOT affected.

0 x x x x x b

Reads back "data" = SIG reg value.

- Bootload frozen; BRAM contents are NOT affected.

NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs)

BRC Register

Bits

X 0 0 0

R/W

Address

Data

any

Writes "data" to corresponding DREG.

any

Reads back "data" = corresponding DREG value.

PROGRAM EXECUTION MODES

0 0 0 0

Execute program in ROM, bootload mode disabled.

- BRAM address counter reset to initial (ready) state.

- SIG reg reseeded to initial (ready) state

0 1 0 0

Execute program in ROM, while bootloading the RAM.

- BRAM address counter increments on microport writes (except to 3fh)

- SIG reg recalculates signature on microport writes (except to 3fh)

1 0 0 0

Execute program in RAM, bootload mode disabled.

- BRAM address counter reset to initial (ready) state.

- SIG reg reseeded to initial (ready) state

1 1 0 0

- NOT RECOMMENDED -

(Execute program in RAM, while bootloading the RAM)

MT93L16

Preliminary Information

Figure 8 - Serial Microport Timing for Intel Mode 0

Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire

R/W

COMMAND/ADDRESS

DATA INPUT/OUTPUT

DATA 1

SCLK

This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16.

The MT93L16:

outputs transmit data on the falling edge of SCLK

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

The COMMAND/ADDRESS byte contains:

1 bit - Read/Write
6 bits - Addressing Data
1 bit - Unused

latches receive data on the rising edge of SCLK

R/W

COMMAND/ADDRESS

DATA INPUT

DATA 2
Receive

DATA 1
Transmit

SCLK

This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to MT93L16.

The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent
byte is always data followed by CS returning high.

A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again.

The COMMAND/ADDRESS byte contains: 1 bit - Read/Write

6 bits - Addressing Data
1 bit - Unused

High Impedance

DATA OUTPUT

The MT93L16:

outputs transmit data on the falling edge of SCLK

latches receive data on the rising edge of SCLK

Preliminary Information

MT93L16

* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.

Typical figures are at 25

C and are for design aid only: not guaranteed and not subject to production testing.

*DC Electrical Characteristics are over recommended temperature and supply voltage.

Absolute Maximum Ratings*

Parameter

Symbol

Min

Max

Units

Supply Voltage

-V

-0.5

5.0

Input Voltage

-0.3

5.5

Output Voltage Swing

-0.3

5.5

Continuous Current on any digital pin

i/o

Storage Temperature

-65

150

Package Power Dissipation

90 (typ)

Recommended Operating Conditions

- Voltages are with respect to ground (V

) unless otherwise stated

Characteristics

Sym

Min

Typ

Max

Units

Test Conditions

Supply Voltage

2.7

3.3

3.6

Input High Voltage

1.4

Input Low Voltage

0.4

Operating Temperature

-40

+85

Echo Return Limits

Characteristics

Min

Typ

Max

Units

Test Conditions

Acoustic Echo Return

Measured from Rout -> Sin

Line Echo Return

Measured from Sout -> Rin

DC Electrical Characteristics*

- Voltages are with respect to ground (V

) unless otherwise stated.

Characteristics

Sym

Min

Typ

Max

Units

Conditions/Notes

Standby Supply Current:

RESET = 0

Operating Supply Current:

RESET = 1, clocks active

Input HIGH voltage

0.7V

Input LOW voltage

0.3V

Input leakage current

0.1

to V

High level output voltage

0.8

=2.5mA

Low level output voltage

0.4

=5.0mA

High impedance leakage

to V

Output capacitance

Input capacitance

MT93L16

Preliminary Information

Timing is over recommended temperature and power supply voltages.

AC Electrical Characteristics

- Serial Data Interfaces -

Voltages are with respect to ground (V

) unless

otherwise stated

Characteristics

Sym

Min

Typ

Max

Units

Test Notes

MCLK Frequency

CLK

19.15

20.5

MHz

BCLK/C4i Clock High

BCH,

C4H

BCLK/C4i Clock Low

BLL,

C4L

BCLK/C4i Period

BCP

240

7900

SSI Enable Strobe to Data Delay
(first bit)

=150pF

SSI Data Output Delay (excluding
first bit)

=150pF

SSI Output Active to High
Impedance

AHZ

=150pF

SSI Enable Strobe Signal Setup

SSS

BCP

-15

SSI Enable Strobe Signal Hold

SSH

BCP

-10

SSI Data Input Setup

DIS

SSI Data Input Hold

DIH

ST-BUS/GCI F0i Setup

F0iS

150

ST-BUS/GCI F0i Hold

F0iH

150

ST-BUS/GCI Data Output delay

DSD

=150pF

ST-BUS/GCI Output Active to High
Impedance

ASHZ

=150pF

ST-BUS/GCI Data Input Hold time

DSH

ST-BUS/GCI Data Input Setup time

DSS

Preliminary Information

MT93L16

Timing is over recommended temperature range and recommended power supply voltages.

Table 8 - Reference Level Definition for Timing Measurements

Figure 10 - Master Clock - MCLK

AC Electrical Characteristics

- Microport Timing

Characteristics

Sym

Min

Typ

Max

Units

Test Notes

Input Data Setup

IDS

Input Data Hold

IDH

Output Data Delay

ODD

100

=150pF

Serial Clock Period

SCP

500

SCLK Pulse Width High

SCH

250

SCLK Pulse Width Low

SCL

250

CS Setup-Intel

CSSI

200

CS Setup-Motorola

CSSM

100

CS Hold

CSH

100

CS to Output High Impedance

OHZ

100

=150pF

Characteristic

Symbol

CMOS Level

Units

CMOS reference level

0.5*V

Input HIGH level

0.9*V

Input LOW level

0.1*V

Rise/Fall HIGH measurement point

0.7*V

Rise/Fall LOW measurement point

0.3*V

MCLK

(I)

T=1/f

CLK

Notes: O. CMOS output

I. CMOS input (5V tolerant)
(see Table 8 for symbol definitions)

MT93L16

Preliminary Information

Register Summary

Address:

00h R/W

Main Control Register (MC)

Power Up

Reset 00h

RESET

When high, the power initialization routine is executed presetting all registers to default values.
This bit automatically clears itself to'0' when reset is complete.

AH-

When high, the Howling detector is disabled and when low the Howling detector is enabled.

AGC-

When high, AGC is disabled and when low AGC is enabled.

NB-

When high, Narrowband signal detectors in Rin and Sin paths are disabled and when low the signal detectors are enabled

BYPASS

When high, the Send and Receive paths are transparently by-passed from input to output and when low the Send and
Receive paths are not bypassed

MUTE_S

When high, the Sin path is muted to quite code (after the NLP) and when low the Sin path is not muted

MUTE_R

When high, the Rin path is muted to quite code (after the NLP) and when low the Rin path is not muted

LIMIT

When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC register and when low 2-bit shift mode is
disabled

Address:

21h R/W

Acoustic Echo Canceller Control Register (AEC)

Power Up

Reset 00h

ECBY

When high, the Echo estimate from the filter is not subtracted from the input (Sin), when low the estimate is subtracted

ADAPT-

When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled

HCLR

When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared

HPF-

When high, Offset nulling filter is bypassed in the Sin/Sout path and when low the Offset nulling filter in not bypassed

INJ-

When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled

NLP-

When high, the Non Linear Processor is disabled in the Sin/Sout path and when low the NLP is enabled

ASC-

When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled

P-

When high, the Exponential weighting function for the adaptive filter is disabled and when low the weighting function is
enabled

Address:

01h R/W

Line Echo Canceller Control Register (LEC)

Power Up

Reset 00h

ECBY

When high, the Echo estimate from the filter is not substracted from the input (Rin), when low the estimate is substracted

ADAPT-

When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled

HCLR

When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared

HPF-

When high, Offset nulling filter is bypassed in the Rin/Rout path and when low the Offset nulling filter in not bypassed

INJ-

When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled

NLP-

When high, the Non Linear Processor is disabled in the Rin/Rout path and when low the NLP is enabled

ASC-

When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled

SHFT

when high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and outputs Sout, Rout are shift left by 2. This bit is
ignored when 16-bit linear mode is not selected in both ports. This bit is also ignored if bit 7 of MC register is set to zero

LIMIT

MUTE_R

MUTE_S

BYPASS

NB-

AGC-

AH-

RESET

LSB

MSB

P-

ASC-

NLP-

INJ-

HPF-

HCLR

ADAPT-

ECBY

LSB

MSB

SHFT

ASC-

NLP-

INJ-

HPF-

HCLR

ADAPT-

ECBY

LSB

MSB

Preliminary Information

MT93L16

Gain Values for Receive Gain Control Register Bit G3 to G0 (RGC)

Address:

22h Read

Acoustic Echo Canceller Status Register

(ASR)

(

* Do not write to this register

)

Power Up

Reset 00h

NBS

When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not
been detected in the Sin/Sout path

LOGICAL OR of the status bit NBS + NBR from LSR Register

When high the Double Talk is detected and when low, the Double talk is not detected

NLPDC

When high, the NLP is activated and when low the NLP is not activated

RESERVED.

HWLNG

When high, Howling is occurring in the loop and when low, no Howling is detected

ACMUND

When high, No active signal in the Rin/Rout path

RESERVED.

Address:

02h Read

Line Echo Canceller Status Register

(LSR)

(

* Do not write to this register

)

Power Up

Reset 00h

NBR

When high, a narrowband signal has been detected in the Receive (Rin) path. When low no narrowband signal is not
detected in the Rin path

This bit indicates a LOGICAL-OR of Status bits NBR + NBS (from ASR Register)

When high, double-talk is detected and when low double-talk is not detected

NLPC

When high, NLP is activated and when low NLP is not activated

RESERVED.
.

Address:

20h R/W

Receive Gain Control Register

(RGC)

Power Up

Reset 6Dh

User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB).
The hexadecimal number represents G3 to G0 value in the table below.

RESERVED

-24dB

-12dB

0 dB

+12 dB

-21dB

-9 dB

+ 3 dB

+ 15 dB

-18dB

-6 dB

+ 6 dB

+ 18 dB

-15dB

-3 dB

+9 dB

+ 21 dB

ACMUND

HWLNG

NLPDC

NBS

LSB

MSB

LSB

MSB

LSB

NBR

NLPC

MT93L16

Preliminary Information

Address:

16h Read

Receive (Rin) Peak Detect Register

1 (RIPD1)

Power Up

Reset 00h

RIPD

These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see
Figure #1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.

RIPD

Address:

17h Read

Receive (Rin) Peak Detect Register

2 (RIPD2)

Power Up

Reset 00h

RIPD

See Above Description

RIPD

Address:

18h Read

Receive (Rin) ERROR Peak Detect Register

1 (REPD1)

Power Up

Reset 00h

REPD

These peak detector registers allow the user to monitor the error signal peak level at reference point R2 (see Figure #1).
The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte is in Register
2 and the low byte is in Register 1.

REPD

Address:

19h Read

Receive (Rin) ERROR Peak Detect Register

2 (REPD2)

Power Up

Reset 00h

REPD8

See above description

REPD9

REPD10

REPD11

REPD12

REPD13

REPD14

REPD15

MSB

RIPD

LSB

MSB

RIPD

LSB

MSB

RIPD

REPD

LSB

MSB

REPD

LSB

MSB

REPD

Preliminary Information

MT93L16

Address:

3Ah Read

Receive (Rout) Peak Detect Register

1 (ROPD1)

Power Up

Reset 00h

ROPD

These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see
Figure #1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.

ROPD

Address:

3Bh Read

Receive (Rout) Peak Detect Register

2 (ROPD2)

Power Up

Reset 00h

ROPD

See Above description

ROPD

Address:

36h Read

Send (Sin) Peak Detect Register

1 (SIPD1)

Power Up

Reset 00h

SIPD

These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see
Figure #1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.

SIPD

Address:

37h Read

Send (Sin) Peak Detect Register

2 (SIPD2)

Power Up

Reset 00h

SIPD

See above description

SIPD

ROPD

LSB

MSB

ROPD

LSB

MSB

ROPD

SIPD

LSB

MSB

SIPD

LSB

MSB

SIPD

MT93L16

Preliminary Information

Address:

38h Read

Send ERROR Peak Detect Register

1 (SEPD1)

Power Up

Reset 00h

SEPD

These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2
(see Figure #1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high
byte is in Register 2 and the low byte is in Register 1.

SEPD

Address:

39h Read

Send ERROR Peak Detect Register

2 (SEPD2)

Power Up

Reset 00h

SEPD8

See Above description

SEPD9

SEPD10

SEPD11

SEPD12

SEPD13

SEPD14

SEPD15

Address:

1Ah Read

Send (Sout) Peak Detect Register

1 (SOPD1)

Power Up

Reset 00h

SOPD

These peak detector registers allow the user to monitor the Send out signal (Sout) peak level at reference point S3 (see
Figure #1). The information is in 16-bit 2's complement linear coded format presented in two 8 bit registers. The high byte
is in Register 2 and the low byte is in Register 1.

SOPD

Address:

1Bh Read

Send (Sout) Peak Detect Register

2 (SOPD2)

Power Up

Reset 00h

SOPD

See Above description

SOPD

SEPD

LSB

MSB

SEPD

LSB

MSB

SEPD

SOPD

LSB

MSB

SOPD

LSB

MSB

SOPD

Preliminary Information

MT93L16

Address:

3Ch R/W

Acoustic Echo Canceller Adaptation Speed Register

1 (A_AS1)

Power Up

Reset 00h

A_AS

This register allows the user to program control the adaptation speed of the Acoustic Echo Canceller. This register value
changes dynamically when the 'ASC-' bit in the Acoustic Echo Canceller Control Register is low. The 'ASC-' bit must be 1
when this register is under user control. The valid range is from 0000h to 7FFFh. The high byte is in Register 2 and the low
byte is in Register 1. Smaller values correspond to slower adaptation speed.

A_AS

Address:

3Dh R/W

Acoustic Echo Canceller Adaptation Speed Register

2 (A_AS2)

Power Up

Reset 10h

A_AS

See Above description

A_AS

Address:

1Ch R/W

Line Echo Canceller Adaptation Speed Register

1 (L_AS1)

Power Up

Reset 00h

L_AS

This register allows the user to program control the adaptation speed of the Line Echo Canceller. This register value
changes dynamically when the 'ASC-' bit in the Acoustic Echo Canceller Control Register is low. The 'ASC-' bit must be 1
when this register is under user control. The valid range is from 0000h to 7FFFh. The high byte is in Register 2 and the low
byte is in Register 1. Smaller values correspond to slower adaptation speed.

L_AS

Address:

1Dh Read

Line Echo Canceller Adaptation Speed Register

2 (L_AS2)

Power Up

Reset 08h

L_AS

See Above description

L_AS

A_AS

LSB

MSB

A_AS

LSB

MSB

A_AS

L_AS

LSB

MSB

L_AS

LSB

MSB

L_AS

MT93L16

Preliminary Information

Address:

24h R/W

Rout Limiter Register 1

(RL1)

Power Up

Reset 80h

RESERVED

This bit is used in conjunction with Rout Limiter Register 2. (See description below.)

Address:

25h R/W

Rout Limiter Register 2

(RL2)

Power Up

Reset 3Eh

In conjunction with bit 7 (L

) of the above (RL1) register, this register (RL2) allows the user to program the output Limiter

threshold value in the Rout path.

Default value is (1f40)h which is equal to 3.14dBmo
Maximum value is (7FC0 )h = 15 dBmo
Minimum value is (0040)h = -38 dBmo

Address:

26h R/W

Sout Limiter Register

(SL)

Power Up

Reset 3Dh

RESERVED

This register allows the user to program the output Limiter threshold value in the Rout path

Default value is (1f40)h which is equal to 3.14dBmo
Maximum value is (7F40 )h

LSB

MSB

LSB

MSB

LSB

MSB

Preliminary Information

MT93L16

Address:

03h Read

Firmware Revision Code Register

(FRC)

Power Up

Reset 00h

RESERVED

FRC

Revision code of the firmware program currently being run (default=rom=00).

FRC

Address:
3fh R / W

Bootload RAM Control Register

(BRC)

Power Up

Reset 00h

RESERVED. Must be set to zero.

BOOT bit. When high, puts device in bootload mode. When low, bootload is disabled.

RAM_ROMb bit. When high, device executes from RAM. When low, device executes from ROM.

RESERVED

Address:

07h Read

Bootload RAM Signature Register

(SIG)

Power Up

Reset FFh

SIG

This register provides the signature of the bootloaded data to verify error-free delivery into the device.
Note: this register is only accessible if BOOT bit is high (bootload mode enabled) in the above BRC register. While
bootload is disabled, the register value is held constant at its reset seed value of FFh.

SIG

LSB

MSB

FRC

LSB

MSB

BOOT

RAM_ROMb

SIG

LSB

MSB

SIG

Package Outlines

QSOP - Quad Shrink Outline Package

Dim

36-Pin

Dim

36-Pin

Min

Max

Min

Max

.096

(2.44)

.104

(2.64)

.0315 inches (ref)

0.80mm

.004

(0.10)

.012

(0.30)

.398

(10.11)

.414

(10.51)

.011

(0.28)

.020

(0.51)

0.16

(0.40)

.050

(1.27)

.0091

(0.23)

.0125

(0.32)

.598

(15.20)

.606

(15.40)

.025

(0.63)

.035

(0.89)

.291

(7.40)

.299

(7.60)

.0335 inches (ref)

0.85

Pin #1

GAGE
PLANE

(.014)

0.335

0.51 x 45

(.020)

0.20

.008

0.63

(.025)

.004

0.10

Notes:

1. Lead Coplanarity should be 0 to 0.10mm (.004") max
2. Package surface finishing

(2.1) Top Matte: (Charmilles #18-30)
(2.2) All Sides: (Charmilles #18-30)
(2.3) Bottom Matte: (Charmilles #18-30)

3. All dimensions excluding mold flashes
4. Max. deviation of center of package and center of leadrame to be 0.10mm (.004")
5. Max. misalignment between top and bottom center of package to 0.10mm (.004")
6. End flash from the package body shall not exceed 0.152 (.006") per side (D)
7. Dimension B shall not include dambar protrusion/intrusion and solder coverage.
8. Not to scale
9. Dimension in inches
10.Dimensions in (millimeters)

DETAIL - A

TECHNICAL DOCUMENTATION - NOT FOR RESALE

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Tel: +1 (613) 592 2122

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Europe, Middle East,

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liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of
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Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Mitel, or non-Mitel furnished goods or services may infringe patents or
other intellectual property rights owned by Mitel.

This publication is issued to provide information only and (unless agreed by Mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or
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publication are subject to change by Mitel without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or
service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific
piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or
data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in
any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Mitel's
conditions of sale which are available on request.

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