Description
The M32170 and M32174 Group are 32-bit single chip RISC
microcomputers designed for use in general industrial and
household equipment.
These microcomputers contains a variety of peripheral
functions ranging from16-channel A-D converters to 64chan-
nel multifunction timers, 10-channel DMAs, 6-channel serial
I/Os, 1-channel real time debugger, 1-channel Full-CAN, and
JTAG (boundary scan facility).
With lower power consumption and low noise characteristics
also considered, these microcomputers are ideal for embed-
ded equipment applications.
Features
M32R RISC CPU core
Uses the M32R family RISC CPU core (Instruction set
common to all microcomputers in the M32R family)
Five-stage pipelined processing
Sixteen 32-bit general-purpose registers
16-bit/32-bit instructions implemented
DSP function instructions (sum-of-products calculation
using 56-bit accumulator)
Built-in flash memory
Built-in flash programming boot program
Built-in RAM
PLL clock generating circuit ........... Built-in
4 PLL circuit
Maximum operating frequency of the CPU clock
40MHz(when operating at -40 to +85
o
C)
32MHz(when operating at -40 to +125
o
C)
Table 1 32170 Group Name List by type
Type Name
RAM Size
ROM Size
Package
M32170F6VFP
40K bytes
768K bytes
240QFP
M32170F4VFP
32K bytes
512K bytes
240QFP
M32170F3VFP
32K bytes
384K bytes
240QFP
M32170F6VWG
40K bytes
768K bytes
255FBGA
M32170F4VWG
32K bytes
512K bytes
255FBGA
M32170F3VWG
32K bytes
384K bytes
255FBGA
Note: 255FBGA is currently under development.
Table 2 32170 Group Name List by type
Type Name
RAM Size
ROM Size
Package
M32174F4VFP
40K bytes
512K bytes
240QFP
M32174F3VFP
40K bytes
384K bytes
240QFP
M32174F4VWG
40K bytes
512K bytes
255FBGA
M32174F3VWG
40K bytes
384K bytes
255FBGA
Note: 255FBGA is currently under development.
64-channel multijunction timers (MJT)
Multifunction timers are incorporated that support various
purposes of use.
16-bit output related timers ....................................... 35ch
16-bit input/output related timers .............................. 10ch
16-bit input related timers ......................................... 11ch
32-bit input related timers .......................................... 8ch
Flexible configuration is possible through interconnection
of timers.
The internal DMAC and A-D converter can be started by a
timer.
Real-time Debugger
Includes dedicated clock-synchronized serial I/O that can
read and write the contents of the internal RAM independently
of the CPU.
Can look up and update the data table in real time while the
program is running.
Can generate a dedicated interrupt based on RTD commu-
nication.
Abundant internal peripheral functions
In addition to the timers and real-time debugger, the micro-
computer contains the following peripheral functions.
DMAC .............................................................. 10 channels
Two independent
A-D converter .............. (10-bit converter
16 channels)
2
Serial I/O ............................................................ 6 channels
Interrupt controller ........... 31 interrupt sources, 8 priority levels
Wait controller
Full CAN .............................................................. 1 channel
JTAG (boundary scan function)
Designed to operate at high temperatures
To meet the need for use at high temperatures, the micro-
computer is designed to be able to operate in the temperature
range of -40 to +125
o
C when CPU clock operating
frequency = 32 MHz. When CPU clock operating frequency =
40 MHz, the microcomputer can be used in the temperature
range of -40 to +85
o
C.
Note: This does not guarantee continuous operation at
125
o
C. If you are considering use of the microcom
puter at 125
o
C, please consult Mitsubishi.
Applications
Automobile equipment control (e.g., Engine, ABS, AT), indus-
trial equipment system control, and high-function OA equip-
ment (e.g., PPC)
Mitsubishi Microcomputers
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
2001-5-14 Rev.1.0
Mitsubishi Microcomputers
2
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 1 Pin Layout Diagram of the 240QFP
Pin Assignment(top view)
Package 240P6Y-A
M32170F3VFP
M32170F4VFP
M32170F6VFP
2
4
3
44
43
5
6
7
8
9
35
36
37
38
39
40
22
23
24
25
26
27
2
8
2
9
30
31
32
33
34
11
12
13
1
4
15
16
17
18
19
20
21
41
42
10
1
60
59
51
52
53
54
55
56
45
46
47
48
49
50
57
58
89
90
99
98
97
96
95
94
93
92
91
103
102
101
112
111
110
109
108
107
106
105
104
120
119
118
117
116
115
114
113
63
64
66
67
68
69
70
71
72
73
74
65
84
75
76
77
78
79
80
81
82
83
85
86
87
88
61
62
100
12
4
132
130
12
9
127
121
137
14
6
14
5
144
1
43
142
141
14
0
13
9
13
8
1
55
1
54
15
3
1
52
1
51
1
50
149
148
147
15
6
1
59
1
58
157
133
136
13
5
13
4
123
122
131
12
8
12
6
12
5
1
66
165
16
4
1
63
162
1
61
17
5
17
4
173
172
171
170
169
16
8
1
67
176
179
178
177
1
60
180
195
185
184
183
182
181
186
189
188
187
194
193
192
191
190
196
199
198
197
205
204
203
202
201
200
206
209
208
207
215
214
213
212
211
210
216
239
217
219
218
225
224
223
222
221
220
226
227
229
228
230
235
234
233
232
231
236
237
238
240
P41/BLW/BLE
P157/TIN7
P156/TIN6
P155/TIN5
P154/TIN4
P153/TIN3
P152/TIN2
P151/TIN1
P150/TIN0
P147/TIN15
P146/TIN14
P145/TIN13
P144/TIN12
P143/TIN11
P142/TIN10
P141/TIN9
P140/TIN8
VSS
VCCE
P137/TIN23
P136/TIN22
P135/TIN21
P134/TIN20
P133/TIN19
P132/TIN18
P131/TIN17
P130/TIN16
VSS
VCCI
P42/BHW/BHE
P127/TCLK3
P126/TCLK2
P125/TCLK1
P124/TCLK0
P107/TO15
P106/TO14
P105/TO13
P104/TO12
VSS
V
CCI
P103/TO11
VSS
VCCI
P4
3/RD
P44
/CS
0
P45/
CS1
P14
/DB12
P37
/A22
P36/
A21
P33/
A18
P31
/A16
P30
/A1
5
P35
/A20
P3
4/
A19
P32
/A17
V
CCE
P27
/A30
P2
5/A2
8
P2
6/A2
9
P2
4/A
27
P07
/DB7
P02
/D
B2
P01/
DB1
P00
/DB0
P23
/A
26
P22
/A25
P20
/A23
P10
/D
B8
P11
/DB
9
V
SS
P15/
DB13
P13
/DB11
P12
/DB
10
P06
/DB
6
P0
4/D
B4
P03
/D
B3
P47
/A14
P21
/A24
P46/
A13
VCC
E
V
SS
P16
/DB1
4
P17
/DB1
5
P82/TXD0
VSS
VCCE
P172/TIN24
P173/TIN25
P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
P160/TO21
P161/TO22
P162/TO23
P163/TO24
P164/TO25
P165/TO26
P166/TO27
P167/TO28
VSS
VCCI
VREF0
AVCC0
AD0IN7
AD0IN6
AD0IN5
AD0IN4
AD0IN3
AD0IN2
AD0IN1
AD0IN0
AD0IN15
AD0IN14
AD0IN13
AD0IN12
AD0IN11
AD0IN10
AD0IN9
AD0IN8
AVSS0
P181/TO30
P182/TO31
P183/TO32
P184/TO33
P180/TO29
VSS
VCCE
P186/TO35
P187/TO36
P190/TIN26
P185/TO34
P194/TIN30
P195/TIN31
P196/TIN32
P197/TIN33
P191/TIN27
P192/TIN28
P193/TIN29
RE
SET
P84/SCLKI0/SCLKO0
P83/RXD0
P85/TXD1
P86/RXD1
P
87/S
CLK
I1/S
CLK
O1
V
SS
V
CCE
VCC
I
P6
2
VSS
FP
P67
/ADT
RG
P66
/SC
LKI5
/SCL
KO
5
P6
5/SC
LKI4
/SC
LK
O
4
P9
4/T
O
17
P7
4/R
TDT
XD
P7
5/R
TDR
XD
P7
6/R
TD
A
CK
P77
/R
T
DC
LK
P
61
P6
3
P11
4/T
O
4
P115
/T
O
5
P11
6/T
O
6
P117
/T
O
7
V
SS
V
CCE
MO
D1
P100
/T
O
8
P101
/T
O
9
P102
/T
O10
P110
/T
O
0
P111
/T
O
1
P112
/T
O
2
P113
/T
O
3
P95
/T
O
18
P96
/T
O1
9
P97
/T
O20
P70
/BCL
K/W
R
P71/W
AIT
P72
/
HRE
Q
P6
4/SB
I
MO
D0
P9
3/T
O
16
P73
/
HA
C
K
VCC
I
V
SS
V
DD
FV
CC
P201
/RX
D4
P202
/TX
D5
P203
/RX
D5
P200
/TX
D4
AD1IN5
AD1IN4
AD1IN3
AD1IN2
AD1IN1
AD1IN0
VREF1
AD1IN15
AD1IN14
AD1IN13
AD1IN12
AV
SS1
AD1IN6
JTDO
JTRST
JTCK
JTMS
JTDI
P212
/T
O3
9
P213
/T
O4
0
P21
4/T
O41
P21
5/T
O42
P211
/T
O
38
P210
/T
O
37
P21
6/T
O43
P217
/T
O44
VC
NT
OSC
-VCC
X
OUT
X
IN
OSC
-VSS
P221
/CR
X
P220
/CT
X
V
SS
VSS
P0
5/DB
5
AD1IN11
AD1IN10
AD1IN9
AD1IN8
AD1IN7
P222
P223
(N
ote)
P22
4/A11
(Note)
P22
5/A
12
VSS
AVCC1
M32174F3VFP
M32174F4VFP
Note: Use caution when using these pins because they nave a debug event function.
Mitsubishi Microcomputers
3
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 2 Pin Layout Diagram of the 255FBGA
Package 255FBGA
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
AD1IN12
AD1IN13
AD1IN14
AD1IN15
AVSS1
P43
/RD
P44
/CS0
P45
/CS1
P46
/A13
P47
/A14
P220
/CTX
P221
/CRX
P222
P223
P224
/A11
P225
/A12
VSS
OSC-
VSS
XIN
XOUT
OSC-
VCC
VSS
VCNT
VSS
P30
/A15
P31
/A16
P32
/A17
P33
/A18
P34
/A19
P35
/A20
TRCLK
TRSYNC
P36
/A21
P37
/A22
P20
/A23
P21
/A24
P23
/A26
P22
/A25
VCCE
VSS
P24
/A27
P25
/A28
P26
/A29
P27
/A30
P00
/DB0
P01
/DB1
P02
/DB2
P03
/DB3
P04
/DB4
P05
/DB5
P06
/DB6
P07
/DB7
VCCE
VSS
P10
/DB8
P11
/DB9
P12
/DB10
P13
/DB11
P14
/DB12
P15
/DB13
P16
/DB14
P17
/DB15
VREF0
AVCC0
AD0IN0
AD0IN1
AD0IN2
AD0IN3 AD0IN4
AD0IN5
AD0IN6
AD0IN7 AD0IN8
AD0IN9
AD0IN10
AD0IN11 AD0IN12
AD0IN13
AD0IN14
AD0IN15 AVSS0
VCCE
VSS
P180
/TO29
P181
/TO30
P182
/TO31
P183
/TO32
P184
/TO33
P185
/TO34
P186
/TO35
P187
/TO36
P190
/TIN26
P191
/TIN27
P192
/TIN28
P193
/TIN29
P194
/TIN30
P196
/TIN32
P195
/TIN31
P197
/TIN33
VCCI
VSS
P160
/TO21
P161
/TO22
P162
/TO23
P163
/TO24
P164
/TO25
P165
/TO26
P166
/TO27
P167
/TO28
P172
/TIN24
P173
/TIN25
P174
/TXD2
P175
/RXD2
P176
/TXD3
P177
/RXD3
VCCE
VSS
P82
/TXD0
P87
/SCLK1
P84
/SCLK0
P85
/TXD1
P86
/RXD1
TRDATA
0
TRDATA
1
TRDATA
2
TRDATA
3
P200
/TXD4
P201
/RXD4
P202
/TXD5
P203
/RXD5
VCCI
VSS
P83
/RXD0
VSS
P61
P62
FVCC
P64
/SBI
P65
/SCLK4
P66
/SCLK5
P63
VCCI
VSS
VCCE
P67
/ADTRG
P71
/WAIT
P72
/HREQ
P73
/HACK
P74/
RTDTXD
P75/
RTDRXD
P76/
RTDACK
P77/
RTDCLK
P93
/TO16
P94
/TO17
P95
/TO18
P96
/TO19
P97
/TO20
RESET
MOD0
MOD1
FP
VCCE
VSS
P110
/TO0
P111
/TO1
P112
/TO2
P113
/TO3
TRDATA
4
TRDATA
5
TRDATA
6
TRDATA
7
P114
/TO4
P115
/TO5
P116
/TO6
P117
/TO7
P100
/TO8
P101
/TO9
P102
/TO10
VDD
VCCI
VSS
P210
/TO37
P211
/TO38
P212
/TO39
P214
/TO41
P215
/TO42
P213
/TO40
P216
/TO43
P217
/TO44
JDBI
JTCK
JEVENT
0
JTRST
JEVENT
1
JTDO
JTDI
P103
/TO11
P104
/TO12
P105
/TO13
P106
/TO14
P107
/TO15
P124
/TCLK0
P125
/TCLK1
P126
/TCLK2
P127
/TCLK3
VCCI
VSS
P130
/TIN16
P131
/TIN17
P132
/TIN18
P133
/TIN19
P134
/TIN20
P135
/TIN21
P136
/TIN22
P137
/TIN23
VCCE
VSS
P140
/TIN8
P141
/TIN9
P142
/TIN10
P143
/TIN11
P144
/TIN12
P145
/TIN13
P146
/TIN14
P147
/TIN15
P150
/TIN0
P151
/TIN1
P152
/TIN2
P153
/TIN3
P154
/TIN4
P155
/TIN5
P156
/TIN6
P157
/TIN7
P41
/BLW
P42
/BHW
VCCI
VSS
VREF1 AVCC1
AD1IN0
AD1IN1
AD1IN2 AD1IN3
AD1IN4
AD1IN5
AD1IN6 AD1IN7
AD1IN8 AD1IN10
AD1IN9 AD1IN11
M32170F3VWG
M32170F4VWG
M32170F6VWG
M32174F3VWG
M32174F4VWG
P70
/BCLK
JTMS
N.C
N.C
Pin Assignment(top view)
Note 1: NC pin (W19, Y1) shows non-connect. Be open state.
Note 2: Use caution when using P224/A11 and P225/A12 because they have a debug event function.
Note 3: 255FBGA is currently under development.
Mitsubishi Microcomputers
4
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 3 Block diagram
PLL clock generation
circuit
Internal bus
interface
Address
Data
Internal RAM
( M32170F6 : 40KB )
( M32170F4 : 32KB )
( M32170F3 : 32KB )
Internal flash memory
( M32170F6 : 768KB )
( M32170F4 : 512KB )
( M32170F3 : 384KB )
M32R CPU core
(max 40MHz)
Multiplier-
accumulator
(32
16 + 56)
DMAC
(10 channels)
Multijunction timer
(MJT : 64 channels)
Serial I/O
(6 channels)
A-D converter
(10-bit, 16 channels)
2
Wait controller
Interrupt controller
(31 sources, 8 levels)
Real-time debugger
(RTD)
External bus
interface
Inter
nal
16-bit b
us
Inter
nal
32-bit b
us
Input/output port(JTAG) 157 lines
Full CAN
(1 channel)
32170/32174
( M32174F4 : 512KB )
( M32174F3 : 384KB )
( M32174F4 : 40KB )
( M32174F3 : 40KB )
Mitsubishi Microcomputers
5
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Table 3 Outline Performance (1/2)
Functional Block
Features
M32R CPU core
M32R family CPU core, internally configured in 32 bits
Built-in multiplier-accumulator (32
16 + 56)
Basic bus cycle : 25 ns (Internal CPU clock frequency at 40 MHz, Internal peripheral
clock frequency at 20 MHz)
Logical address space : 4G bytes, linear
General-purpose register : 32-bit register
16, Control register: 32-bit register
5
accumulator : 56 bits
External data bus
16 bits data bus
Instruction set
16-bit/32-bit instruction formats
83 instructions/ 9 addressing modes
Internal flash memory
M32170F6 : 768K bytes
M32170F4, M32174F4 : 512K bytes
M32170F3, M32174F3 : 384K bytes
Rewrite durability : 100 times
Internal RAM
M32170F6, M32174F4, M32174F3 : 40K bytes
M32170F4, M32170F3 : 32K bytes
DMAC
10 channels (DMA transfers between internal peripheral I/Os, between internal peripheral
I/O and internal RAM, and between internal RAMs)
Channels can be cascaded and can operate in combination with internal peripheral I/O
Multijunction timer
64 channels of multijunction timers.
16-bit output-related timers
35 channels (single-shot, delayed single-shot, PWM, single-shot PWM)
16-bit input/output-related timers
10 channels (event count mode, single-shot, PWM, measurement)
16-bit input-related timers
11 channels (measurement, event count mode, multiply-by-4 count 3 channels)
32-bit input-related timers
8 channels (measurement)
Flexible timer configuration is possible through interconnection of channels using the event bus.
A-D converter
2 independent 10-bit multifunction A-D converters
Input 16 channels
2
Scan-based conversion can be switched with 4, 8, and 16
Capable of interrupt conversion during scan
8-bit/10-bit readout function available
Serial I/O
6 channels (The serial I/Os can be set for synchronous serial I/O or UART.
SIO2,3 are UART mode only)
Real-time debugger (RTD)
1-channels dedicated clock-synchronized serial
The entire internal RAM can be read or rewritten from the outside without CPU intervention.
Interrupt controller
Controls interrupts from internal peripheral I/Os
(Priority can be set to one of 8 levels including interrupt disabled)
Wait controller
Controls wait when accessing external extended area
(1 to 4 wait cycles inserted + prolonged by external WAIT signal input)
CAN
16-channels message slots
JTAG
Boundary-Scan function
Mitsubishi Microcomputers
6
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Table 4 Outline Performance (2/2)
Function Block
Features
Clock
Maximum internal CPU memory clock : 40MHz (access to CPU, internal ROM, and internal RAM)
Maximum internal peripheral clock : 20MHz (access to internal peripheral module)
Maximum external input clock : 10.0MHz, Built-in multiply-by-4 PLL circuit
Power Supply Voltage
External I/O : 5V (
0.5V) or 3.3V (
0.3V)
Internal logic : 3.3V (
0.3V)
Operating temperature rang
-40 to +125
C(Internal CPU memory clock 32MHz, internal peripheral clock 16MHz)
-40 to +85
C(Internal CPU memory clock 40MHz, internal peripheral clock 20MHz)
Package
0.5mm pitches / 240-pin plastic QFP, 0.8mm pitches / 255-pin FBGA (Note)
Note: 255-pin FBGA is currently under development.
Mitsubishi Microcomputers
7
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Outline of the CPU core
The M32170 and M32174 Group uses the M32R RISC CPU
core, and has an instruction set which is common to all micro-
computers in the M32R family.
Instructions are processed in five pipelined stages consisting
of instruction fetch, decode, execution, memory access, and
write back. Thanks to its "out-of-order-completion" mechanism,
the M32R CPU allows for clock cycle efficient, instruction ex-
ecution control.
The M32R CPU internally has sixteen 32-bit general-purpose
registers. The instruction set consists of 83 discrete instruc-
tions, which come in either a 16-bit instruction or a 32-bit in-
struction format. Use of the 16-bit instruction format helps to
reduce the code size of a program. Also, the availability of 32-
bit instructions facilitates programming and increases the per-
formance at the same clock speed, as compared to
architectures with segmented address spaces.
Sum-of-products instructions comparable to DSP
The M32R CPU contains a multiplier/accumulator that can
execute 32 bits
16 bits in one cycle. Therefore, it executes a
32 bit
32 bit integer multiplication instruction in three cycles.
Also, the M32R CPU supports the following four sum-of-prod-
ucts instructions (or multiplication instructions) for DSP func-
tion use.
(1) 16 high-order register bits
16 high-order register bits
(2) 16 low-order register bits
16 low-order register bits
(3) All 32 register bits
16 high-order register bits
(4) All 32 register bits
16 low-order register bits
Furthermore, the M32R CPU has instructions for rounding the
value stored in the accumulator to 16 or 32 bits, and instruc-
tions for shifting the accumulator value to adjust digits before
storing in a register. Because these instructions also can be
executed in one cycle, DSP comparable data processing ca-
pability can be obtained by using them in combination with
high-speed data transfer instructions such as Load & Address
Update or Store & Address Update.
Built-in clock multiplier circuit
The clock multiplier circuit multiplies the frequency of the in-
put clock signal by 4 to produce the internal operating clock.
When the maximum CPU memory clock frequency = 40 MHz,
the input clock frequency is 10.0 MHz.
Three operation modes
The M32170 and M32174 Group has three operation modes:
single-chip mode, external extended mode, and processor
mode. These operation modes are changed from one to an-
other by setting the MOD0 and MOD1 pins.
Address space
The M32170 and M32174 Group's logical addresses are al-
ways handled in 32 bits, providing 4 Gbytes of linear address
space. The M32170 and M32174 Group's address space
consists of the following.
User space
A 2-Gbyte area from H'0000 0000 to H'7FFF FFFF is the user
space. Located in this space are the user ROM area, external
extended area, internal RAM area, and SFR (Special Function
Register) area (internal peripheral I/O registers). Of these, the
user ROM area and external extended area are located differ-
ently depending on mode settings.
Boot program space
A 1-Gbyte area from H'8000 0000 to H'BFFF FFFF is the boot
program area. This space contains the on-board programming
program (boot program) used in blank state by the internal flash
memory.
System space
A 1-Gbyte area from H'C000 0000 to H'FFFF FFFF is the
system area. This space is reserved for use by development
tools such as an in-circuit emulator and debug monitor, and
cannot be used by the user.
Mitsubishi Microcomputers
8
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 4 Pin Function Diagram of 240QFP
XIN
RESET
M32170F6VF
P , M32170F4
VFP , M32170F
3VFP , M32174F4VF
P , M32174F3
VFP
Clock
Reset
VCCI
VSS
6
16
P20-P27/A23-A30
P30-P37/A15-A22
P46, P47/A13, A14
Address
bus
20
P00-P07/DB0-DB7
P10-P17/DB8-DB15
Data
bus
16
P72/HREQ
P73/HACK
Bus
control
P71/WAIT
Interrupt
controller
P43/RD
P44/CS0
P45/CS1
P41/BLW/BLE
P42/BHW/BHE
Port 22
Port 2
Port 3
Port 4
Port 0
Port 1
Port 7
Port 4
XOUT
VCNT
OSC-VCC
OSC-VSS
MOD0
MOD1
Mode
P190-P197/TIN26-TIN33
P172, P173/TIN24, TIN25
P150-P157/TIN0-TIN7
P140-P147/TIN8-TIN15
P130-P137/TIN16-TIN23
34
Port 19
Port 17
Port 15
Port 14
Port 13
P124-P127/
TCLK0-TCLK 3
4
45
P210-P217/TO37-TO44
P180-P187/TO29-TO36
P160-P167/TO21-TO28
P110-P117/TO0-TO7
P100-P107/TO8-TO15
P93-P97/TO16-TO20
Port 12
Port 21
Port 18
Port 16
Port 11
Port 10
Port 9
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
Real-time
debugger
Port 7
P70/BCLK/WR
Port 7
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
Serial I/O
Port 8
16
AD1IN0-AD1IN15
A-D
converter
P67/ADTRG
AVCC0, AVCC1
AVSS0, AVSS1
Port 6
P61-P63
Port 6
AVREF0, AVREF1
VDD
FVCC
FP
VCCE
7
P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
Port 17
3.3V (Note 1)
5V
3.3V
5V
3.3V
3.3V
5V
Note 1:
: Operates with a 3.3V power supply.
: Operates with a 3.3V or 5V power supply.
16
AD0IN0-AD0IN15
2
2
2
P200/TXD4
P201/RXD4
P202/TXD5
P203/RXD5
Port 20
P220/CTX
P221/CRX
CAN
JTMS
JTCK
JTRST
JTDO
JTAG
JTDI
Port 22
P222, P223
Port 22
P224/A11 (Note 2)
P225/A12 (Note 2)
Note 2: Use caution when using this port because it has a debug event function.
P65/SCLKI4/SCLKO4
P64/SBI
Port 6
P66/SCLKI5/SCLKO5
Port 6
3
Multijunction
timer
Mitsubishi Microcomputers
9
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 5 Pin Function Diagram of 255FBGA
XIN
RESET
M32170F6VWG , M32170F4VWG , M32170F3VWG , M32174F4VWG , M32174F3VWG
Clock
Reset
VCCI
VSS
6
16
P20-P27/A23-A30
P30-P37/A15-A22
P46, P47/A13, A14
Address
bus
20
P00-P07/DB0-DB7
P10-P17/DB8-DB15
Data
bus
16
P72/HREQ
P73/HACK
Bus
control
P71/WAIT
Interrupt
controller
P43/RD
P44/CS0
P45/CS1
P41/BLW/BLE
P42/BHW/BHE
Port 22
Port 2
Port 3
Port 4
Port 0
Port 1
Port 7
Port 4
XOUT
VCNT
OSC-VCC
OSC-VSS
MOD0
MOD1
Mode
P190-P197/TIN26-TIN33
P172, P173/TIN24, TIN25
P150-P157/TIN0-TIN7
P140-P147/TIN8-TIN15
P130-P137/TIN16-TIN23
34
Port 19
Port 17
Port 15
Port 14
Port 13
P124-P127/
TCLK0-TCLK 3
4
Multijunction
timer
45
P210-P217/TO37-TO44
P180-P187/TO29-TO36
P160-P167/TO21-TO28
P110-P117/TO0-TO7
P100-P107/TO8-TO15
P93-P97/TO16-TO20
Port 12
Port 21
Port 18
Port 16
Port 11
Port 10
Port 9
P74/RTDTXD
P75/RTDRXD
P76/RTDACK
P77/RTDCLK
Real-time
debugger
Port 7
P70/BCLK/WR
Port 7
P82/TXD0
P83/RXD0
P84/SCLKI0/SCLKO0
P85/TXD1
P86/RXD1
P87/SCLKI1/SCLKO1
Serial
I/O
Port 8
16
AD1IN0-AD1IN15
A-D
converter
P67/ADTRG
AVCC0, AVCC1
AVSS0, AVSS1
Port 6
P61-P63
Port 6
AVREF0, AVREF1
VDD
FVCC
FP
VCCE
7
P174/TXD2
P175/RXD2
P176/TXD3
P177/RXD3
Port 17
3.3V (Note 1)
5V
3.3V
5V
3.3V
3.3V
5V
Note 1:
: Operates with a 3.3V power supply.
: Operates with a 3.3V or 5V power supply.
16
AD0IN0-AD0IN15
2
2
2
P200/TXD4
P201/RXD4
P202/TXD5
P203/RXD5
Port 20
P220/CTX
P221/CRX
CAN
JTMS
JTCK
JTRST
JTDO
JTAG
JTDI
Port 22
P222, P223
Port 22
P224/A11 (Note 2)
P225/A12 (Note 2)
Note 2: Use caution when using this port because it has a debug event function.
P65/SCLKI4/SCLKO4
P64/SBI
Port 6
P66/SCLKI5/SCLKO5
Port 6
3
8
TRCLK
TRSYNC
TRDATA
JDBI
JEVENTO
JEVENT1
DEBUG
Note 3: 255FBGA is currently under development.
Mitsubishi Microcomputers
10
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Table 5 Description of Pin Function (1/5 )
Type
Pin Name
Description
Input/Output
Function
Power
VCCE
Power supply
--
Supplies power (5 V or 3.3V) to external I/O ports.
supply
VCCI
Power supply
--
Supplies power (3.3 V) to the internal logic.
VDD
RAM power supply
--
nternal RAM backup power supply (3.3 V).
FVCC
Flash power supply --
Internal flash memory backup power supply (3.3 V).
VSS
Ground
--
Connect all VSS pins to ground (GND).
Clock
XIN,
Clock
Input
Clock input/output pins. These pins contain a PLL-based
XOUT
Output
frequency multiply-by-4, so input the clock whose frequency is quarter
the operating frequency. (XIN input = 10 MHz when CPU clock operates
at 40 MHz)
BCLK /
System clock
Output
When this signal is System Clock(BCLK), it outputs a clock whose is twice that of
______
WR
external inpout clock. (BCLK output = 20 MHz when CPU clock operates at 40
MHz). Use this clock when circuits are synchronized externally.
______
When this signal is Write(WR),during external write access it indicates the valid
data on the data bus to transfer.
OSC-VCC
Power supply
--
Power supply to the PLL circuit. Connect OSC-VCC to the power supply(3.3V)
OSC-VSS
Ground
--
Connect OSC-VSS to ground.
VCNT
PLL control
Input
This pin controls the PLL circuit. Connect a resistor and capacitor to this pin.
Reset
______
RESET
Reset
Input
This pin resets the internal circuits.
Mode
MOD0
Mode
Input
These pins set an operation mode.
MOD1
MOD0 MOD1
Mode
0
0
Single-chip mode
0
1
Expanded external mode
1
0
Processor mode
0
0
(Boot mode) (Note)
1
1
(Reserved)
Address
A11-A30
Address
Output
20 lines of address bus (A11-A30) are provided to accommodate two
bus
bus
channels of 2 MB memory space (max.) connected external to the chip.
A31 is not output.
In the write cycle, of the 16-bit data bus the valid byte positions to write are
_________ ________
________ _______
output as BHW/ BHE and BLW/ BLE. In read cycle, data on the entire 16-bit
data bus is read. However, only the data at the valid byte positions are
transferred to the M32R's internal circuit.
Data bus
DB0-DB15
Data bus
Input/output
This 16-bit data bus connects to external device.
Note: FP pin should be "H" level in Boot Mode.
Mitsubishi Microcomputers
11
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Table 6 Description of Pin Function (2/5)
Type
Pin type
Description
Input/Output Function
Bus
___
CS0,
Chip
Output
Chip select signals for external devices.
control
CS1
select
__
RD
Read
Output
This signal is output when reading external devices.
___
_______
BHW/ BHE
Byte high
Output
Indicates the byte positions to which valid are transferred when writing to
write
________
_______
________ _______
external devices.BHW/ BHE and BLW/ BLE correspond to the upper address
___ _______
BLW/ BLE
Byte low
Output
side(D0-D7 effective) and the lower address side(D8-D15 effective),respectivel.
write
____
WAIT
Wait
Input
_________
If WAIT input is low when the M32R accesses external devices, the wait cycle
extended.
_____
HREQ
Hold
Input
This pin is used by an external device to request control of the external bus.
request
__________
The M32R goes to a hold state when HREQ input is pulled low.
____
HACK
Hold
Output
This signal indicates to the external device that the M32R has entered a hold
acknowledge
state and relinquished control of the external bus.
Multijunction TIN0
Timer input
Input
Input pins for multijunction timer.
timer
-TIN33
TO0
Timer output
Output
Output pins for multijunction timer.
-TO44
TCLK0
Timer clock
Input
Clock input pins for multijunction timer.
-TCLK3
A-D
AVCC0,
Analog power
AVCC0 is the power supply for the A-D0 converters. AVCC1 is the power
converter
AVCC1
upply
supply for the A-D1 converters.
Connect AVCC0 and AVCC1 to the power supply (5V or 3.3V).
AVSS0,
Analog ground
AVSS0 is the analog ground for the A-D0 converters. AVSS1 is the
AVSS1
analog ground for the A-D1 converters.
Connect AVCC0 and AVCC1 to ground.
AD0IN0
Analog input
Input
One block of 16-channel analog input pin for A-D0 converter.
-AD0IN15
AD1IN0
Two blocks of 16-channel analog input pin for A-D1 converter.
-AD1IN15
VREF0,
Reference
Input
VREF0 is the reference voltage input pin (5V or 3.3V) for the A-D0 converters.
VREF1
voltage input
VREF1 is the reference voltage input pin (5V or 3.3V) for the A-D1 converters.
_____
ADTRG
Conversion
Input
Hardware trigger input pin to start A-D conversion.
trigger
Interrupt
___
SBI
SystemInput
System
break interrupt(SBI) input pin of the interrupt controller.
controller
break
interrupt
Mitsubishi Microcomputers
12
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Table 7 Description of Pin Functions (3/5)
Type
Pin name
Description
Input/output
Function
Serial
SCLKI0/
UART transmit/ Input/output
When channel 0 is in UART mode:
I/O
SCLKO0
receive clock
Clock output derived from BRG output by dividing it by 2
output or CSIO
transmit/receive
When channel 0 is in CSIO mode:
clock
Transmit/receive clock input when external clock is selected
input/output
Transmit/receive clock output when internal clock is selected
SCLKI1/
UART transmit/ Input/output
When channel 1 is in UART mode:
SCLKO1
receive clock
Clock output derived from BRG output by dividing it by 2
output or CSIO
transmit/receive
When channel 1 is in CSIO mode:
clock
Transmit/receive clock input when external clock is selected
input/output
Transmit/receive clock output when internal clock is selected
SCLKI4/
UART transmit/ Input/output
When channel 4 is in UART mode:
SCLKO4
receive clock
Clock output derived from BRG output by dividing it by 2
output or CSIO
transmit/receive
When channel 4 is in CSIO mode:
clock
Transmit/receive clock input when external clock is selected
input/output
Transmit/receive clock output when internal clock is selected
SCLKI5
UART transmit/ Input/output
When channel 5 is in UART mode:
SCLKO5
receive clock
Clock output derived from BRG output by dividing it by 2
output or CSIO
transmit/receive
When channel 5 is in CSIO mode:
clock
Transmit/receive clock input when external clock is selected
input/output
Transmit/receive clock output when internal clock is selected
TXD0
Transmit data
Outpt
Transmit data output pin for serial I/O channel 0
RXD0
Receive data
Input
Receive data input pin for serial I/O channel 0
TXD1
Transmit data
Output
Transmit data output pin for serial I/O channel 1
RXD1
Receive data
Input
Receive data input pin for serial I/O channel 1
TXD2
Transmit data
Output
Transmit data output pin for serial I/O channel 2
RXD2
Receive data
Input
Receive data input pin for serial I/O channel 2
TXD3
Transmit data
Output
Transmit data output pin for serial I/O channel 3
RXD3
Receive data
Input
Receive data input pin for serial I/O channel 3
TXD4
Transmit data
Output
Transmit data output pin for serial I/O channel 4
RXD4
Receive data
Input
Receive data input pin for serial I/O channel 4
TXD5
Transmit data
Output
Transmit data output pin for serial I/O channel 5
RXD5
Receive data
Input
Receive data input pin for serial I/O channel 5
Mitsubishi Microcomputers
13
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Table 8 Description of Pin Functions (4/5)
Type
Pin name
Description
Input/output
Function
Real-Time
RTDTXD
Transmit data
Output
Serial data output pin of the real-time debugger
Debugger
RTDRXD
Receive data
Input
Serial data input pin of the real-time debugger
RTDCLK
Clock input
Input
Serial data transmit/receive clock input pin of the real-time debugger
RTDACK
Acknowledge
Output
This pin outputs a low pulse synchronously with the real-time debugger's
first clock of serial data output word. The low pulse width indicates the
type of the command/data the realtime debugger has received.
Flash-
FP
Flash protect
Input
This pin protects the flash memory against E/W in hardware.
only
CAN
CTX
Transmit data
Output
Data output pin from CAN module.
CRX
Receive data
Input
Data input pin to CAN module.
JTAG
JTMS
Test mode
Input
Test select input for controlling the test circuit's state transition
JTCK
Clock
Input
Clock input to the debugger module and test circuit.
JTRST
Test reset
Input
Test reset input for initializing the test circuit asynchronously.
JTDO
Serial output
Output
Serial output of test instruction code or test data.
JTDI
Serial input
Input
Serial input of test instruction code or test data.
P00-P07
Input/output port 0 Input/output
Programmable input/output port.
P10-P17
Input/output port 1 Input/output
Programmable input/output port.
P20-P27
Input/output port 2 Input/output
Programmable input/output port.
P30-P37
Input/output port 3 Input/output
Programmable input/output port.
P41-P47
Input/output port 4 Input/output
Programmable input/output port.
P61-P67
Input/output port 6 Input/output
Programmable input/output port.
(However, P64 is an input-only port)
P70-P77
Input/output port 7 Input/output
Programmable input/output port.
P82-P87
Input/output port 8 Input/output
Programmable input/output port.
P93-P97
Input/output port 9 Input/output
Programmable input/output port.
P100
Input/output port 10 Input/output
Programmable input/output port.
-P107
Note: Input/output port 5 is reserved for future use.
Input/
output
port
(Note)
Mitsubishi Microcomputers
14
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Table 9 Description of Pin Functions (5/5)
Type
Pin name
Description
Input/output
Function
P110
Input/output port 11
Input/output
Programmable input/output port.
-P117
P124
Input/output port 12
Input/output
Programmable input/output port.
-P127
P130
Input/output port 13
Input/output
Programmable input/output port.
-P137
P140
Input/output port 14
Input/output
Programmable input/output port.
-P147
P150
Input/output port 15
Input/output
Programmable input/output port.
-P157
P160
Input/output port 16
Input/output
Programmable input/output port.
-P167
P172
Input/output port 17
Input/output
Programmable input/output port.
-P177
P180
Input/output port 18
Input/output
Programmable input/output port.
-P187
P190
Input/output port 19
Input/output
Programmable input/output port.
-P197
P200
Input/output port 20
Input/output
Programmable input/output port.
-P203
P210
Input/output port 21
Input/output
Programmable input/output port.
-P217
P220
Input/output port 22
Input/output
Programmable input/output port. (Note)
-P225
(However, P221 is an input-only port)
Note: Use caution when using P224 and P225 because they have a debug event function.
Input/
output
port
Mitsubishi Microcomputers
15
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 6 Address Space of the M32170F6
BOOT ROM
area
(8K bytes)
H'0000 0000
H'FFFF FFFF
< Logical space of the M32170F6 >
H'7FFF FFFF
H'8000 0000
User space
EIT vector entry
Logical address
H'BFFF FFFF
H'C000 0000
Boot
program
space
System
space
(16M bytes)
H'0000 0000
H'00FF FFFF
H'007F FFFF
H'0080 0000
SFR area
(16K bytes)
H'0080 3FFF
H'0080 4000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Internal ROM
area
768K bytes
Expanded external area
(4M bytes)
Ghost area in
units of 128K bytes
1G bytes
1G bytes
2G bytes
Ghost area
in units of
16M bytes
Ghost area in
units of 4M bytes
Internal RAM
(40K bytes)
H'0080 DFFF
H'8000 0000
H'8000 1FFF
Ghost area
in units of
16K bytes
Reserved area
(8K bytes)
Reserved area
(72K bytes)
H'0081 FFFF
H'0082 0000
H'0080 E000
H'8000 3FFF
H'8000 2000
H'8000 4000
H'BFFF FFFF
H'000B FFFF
H'0010 0000
CS1 area
CS0 area
Reserved area
(256K bytes)
H'000F FFFF
Mitsubishi Microcomputers
16
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 7 Address Space of the M32170F4
BOOT ROM
area
(8K bytes)
H'0000 0000
H'FFFF FFFF
< Logical space of the M32170F4 >
H'7FFF FFFF
H'8000 0000
User space
EIT vector entry
Logical address
H'BFFF FFFF
H'C000 0000
Boot
program
space
System
space
(16M bytes)
H'0000 0000
H'00FF FFFF
H'007F FFFF
H'0080 0000
SFR area
(16K bytes)
H'0080 3FFF
H'0080 4000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Internal ROM
area
512K bytes
Expanded external area
(4M bytes)
1G bytes
1G bytes
2G bytes
Ghost area
in units of
16M bytes
Ghost area in
units of 4M bytes
Internal RAM
(32K bytes)
H'0080 BFFF
H'8000 0000
H'8000 1FFF
Reserved area
(8K bytes)
Reserved area
(80K bytes)
H'0081 FFFF
H'0082 0000
H'0080 C000
H'8000 3FFF
H'8000 2000
H'8000 4000
H'BFFF FFFF
H'0007 FFFF
H'0010 0000
CS1 area
CS0 area
Reserved area
(512K bytes)
H'000F FFFF
Ghost area
in units of
16K bytes
Ghost area in
units of 128K bytes
Mitsubishi Microcomputers
17
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 8 Address Space of the M32170F3
BOOT ROM
area
(8K bytes)
H'0000 0000
H'FFFF FFFF
< Logical space of the M32170F3 >
H'7FFF FFFF
H'8000 0000
User space
EIT vector entry
Logical address
H'BFFF FFFF
H'C000 0000
Boot
program
space
System
space
(16M bytes)
H'0000 0000
H'00FF FFFF
H'007F FFFF
H'0080 0000
SFR area
(16K bytes)
H'0080 3FFF
H'0080 4000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Internal ROM
area
384K bytes
Expanded external area
(4M bytes)
Ghost area in
units of 128K byte
1G bytes
1G bytes
2G bytes
Ghost area in
units of 4M bytes
Internal RAM
(32K bytes)
H'0080 BFFF
H'8000 0000
H'8000 1FFF
Ghost area
in units of
16K bytes
Reserved area
(8K bytes)
Reserved area
(80K bytes)
H'0081 FFFF
H'0082 0000
H'0080 C000
H'8000 3FFF
H'8000 2000
H'8000 4000
H'BFFF FFFF
H'0005 FFFF
H'0010 0000
CS1 area
CS0 area
Reserved area
(640K bytes)
H'000F FFFF
Ghost area
in units of
16M bytes
Mitsubishi Microcomputers
18
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
BOOT ROM
area
(8K bytes)
H'0000 0000
H'FFFF FFFF
< Logical space of the M32174F4 >
H'7FFF FFFF
H'8000 0000
User space
EIT vector entry
Logical address
H'BFFF FFFF
H'C000 0000
Boot
program
space
System
space
(16M bytes)
H'0000 0000
H'00FF FFFF
H'007F FFFF
H'0080 0000
SFR area
(16K bytes)
H'0080 3FFF
H'0080 4000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Internal ROM
area
512K bytes
Expanded external area
(4M bytes)
1G bytes
1G bytes
2G bytes
Ghost area
in units of
16M bytes
Ghost area in
units of 4M bytes
Internal RAM
(40K bytes)
H'0080 DFFF
H'8000 0000
H'8000 1FFF
Ghost area
in units of
16K bytes
Reserved area
(8K bytes)
Reserved area
(72K bytes)
H'0081 FFFF
H'0082 0000
H'0080 E000
H'8000 3FFF
H'8000 2000
H'8000 4000
H'BFFF FFFF
H'0007 FFFF
H'0010 0000
CS1 area
CS0 area
Reserved area
(512 bytes)
H'000F FFFF
Ghost area in
units of 128K bytes
Figure 9 Address Space of the M32174F4
Mitsubishi Microcomputers
19
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 10 Address Space of the M32174F3
BOOT ROM
area
(8K bytes)
H'0000 0000
H'FFFF FFFF
< Logical space of the M32174F3 >
H'7FFF FFFF
H'8000 0000
User space
EIT vector entry
Logical address
H'BFFF FFFF
H'C000 0000
Boot
program
space
System
space
(16M bytes)
H'0000 0000
H'00FF FFFF
H'007F FFFF
H'0080 0000
SFR area
(16K bytes)
H'0080 3FFF
H'0080 4000
H'001F FFFF
H'0020 0000
H'003F FFFF
H'0040 0000
Internal ROM
area
384K bytes
Expanded external area
(4M bytes)
Ghost area in
units of 128K bytes
1G bytes
1G bytes
2G bytes
Ghost area
in units of
16M bytes
Ghost area in
units of 4M bytes
Internal RAM
(40K bytes)
H'0080 DFFF
H'8000 0000
H'8000 1FFF
Ghost area
in units of
16K bytes
Reserved area
(8K bytes)
Reserved area
(72K bytes)
H'0081 FFFF
H'0082 0000
H'0080 E000
H'8000 3FFF
H'8000 2000
H'8000 4000
H'BFFF FFFF
H'0005 FFFF
H'0010 0000
CS1 area
CS0 area
Reserved area
(640K bytes)
H'000F FFFF
Mitsubishi Microcomputers
20
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 11 SFR Area
H'0080 0000
H'0080 007E
H'0080 0180
Interrupt
controller
(ICU)
H'0080 0080
A-D0 converter
H'0080 00EE
Serial I/O
H'0080 0100
H'0080 0146
Wait controller
MJT (common part)
MJT (TOP)
MJT (TIO)
MJT (TMS)
H'0080 0200
H'0080 0240
H'0080 0300
H'0080 03C0
H'0080 03E0
H'0080 03FE
Note: The Real-time debugger (RTD) is an independent module operated from external circuits,
and is transparent to the CPU.
+0
address
+1
address
0
7 8
15
H'0080 0A00
to
to
to
to
to
to
to
to
+0
address
+1
address
0
7 8
15
Multijunction
timer
(MJT)
Flash control
H'0080 07E0
H'0080 07F2
H'0080 023E
H'0080 02FE
MJT (TOD0)
H'0080 078C
H'0080 07DE
to
MJT (TID0)
H'0080 0790
H'0080 078E
Multijunction
timer
(MJT)
Serial I/O
H'0080 0A26
H'0080 0A80
A-D1 converter
H'0080 0AEE
MJT (TOD1)
MJT (TOM)
H'0080 0BDE
H'0080 0C8C
H'0080 0CDE
MJT (TML1)
H'0080 0FE0
H'0080 0FFE
Multijunction
timer
(MJT)
H'0080 0400
DMAC
H'0080 0478
to
CAN
H'0080 1000
H'0080 11FE
H'0080 0700
Input/output ports
H'0080 077E
to
H'0080 03BE
H'0080 03D8
MJT (TML0)
H'0080 0B8C
MJT (TID1)
H'0080 0B8E
H'0080 0B90
H'0080 0C8E
H'0080 0C90
MJT (TID2)
to
to
to
to
to
to
to
H'0080 3FFE
Mitsubishi Microcomputers
21
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Built-in Flash Memory and RAM
32170 and 32174 Group contain Flash Memory and RAM
stated as follows.
The internal flash memory can be programmed on-board
(i.e., while being mounted on the printed circuit board). This
means that the same chip as will be used in mass-produc-
tion can be used directly from the development stage on,
allowing for system development without having to change
the printed circuit board when proceeding from trial produc-
tion to mass-production.
Table 10 Flash memory and RAM Size (32170 Group)
Type Name
ROM Size
RAM Size
M32170F6VFP
768K bytes
40K bytes
M32170F4VFP
512K bytes
32K bytes
M32170F3VFP
384K bytes
32K bytes
M32170F6VWG
768K bytes
40K bytes
M32170F4VWG
512K bytes
32K bytes
M32170F3VWG
384K bytes
32K bytes
Table 11 Flash memory and RAM Size (32174 Group)
Type Name
ROM Size
RAM Size
M32174F4VFP
512K bytes
40K bytes
M32174F3VFP
384K bytes
40K bytes
M32174F4VWG
512K bytes
40K bytes
M32174F3VWG
384K bytes
40K bytes
Built-in Virtual-flash Emulation Function
Internal flash memory, which is divided from the first address
in units of 8 Kbyte (L banks), can be replaced in 8 -Kbyte
blocks (H70080 4000-H'0080 5FFF) of the internal RAM.
And also the internal flash memory, which is divided from the
first address in units of 4-Kbyte areas (S banks), can be re-
placed in 4 Kbytes areas.
This function allows parts of the program which are fre-
quently changed during development to be altered or evalu-
ated without having to reset the microcomputer each time.
What's more, when combined with the realtime debugger,
this function helps to reduce the program evaluation period,
because data in the RAM can be rewritten without requiring
any CPU load.
Mitsubishi Microcomputers
22
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
H'0000 0000
H'0000 2000
H'0006 6000
< Internal flash >
< Internal RAM >
L bank 1
(8K bytes)
H'0080 4000
H'0080 6000
L bank 0
(8K bytes)
H'0000 4000
H'0006 4000
L bank 51
(8K bytes)
L bank 50
(8K bytes)
L bank 2
(8K bytes)
8K bytes
8K bytes
8K bytes
8K bytes
L bank 95
(8K bytes)
L bank 94
(8K bytes)
H'000B E000
H'000B C000
H'0080 8000
H'0080 A000
4K bytes
4K bytes
H'0000 0000
H'0000 1000
< Internal flash >
< Internal RAM >
S bank 1
(4K bytes)
H'0080 4000
S bank 0
(4K bytes)
H'0000 2000
S bank 2
(4K bytes)
8K bytes
S bank 191
(4K bytes)
S bank 190
(4K bytes)
H'000B F000
H'000B E000
8K bytes
8K bytes
8K bytes
4K bytes
4K bytes
H'0080 C000
H'0080 D000
Figure 12 Virtual-Flash Emulation Areas of the M32170F6VFP (Replaced in Units of 8 Kbytes)
Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled,
the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1
> FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1.
Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-3, the internal RAM
area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM
area and the virtual-flash setup area.
Figure 13 Virtual-Flash Emulation Areas of the M32170F6VFP (Replaced in Units of 4 Kbytes)
Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled,
the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1
> FELBANK2 > FELBANK3 > FESBANK0 > FESBANK1.
Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM
area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM
area and the virtual-flash setup area.
Mitsubishi Microcomputers
23
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 14 Virtual-Flash Emulation Areas of the M32170F4VFP (Replaced in Units of 8 Kbytes)
Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled,
the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1
> FELBANK2 > FESBANK0 > FESBANK1.
Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-2, the internal RAM
area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM
area and the virtual-flash setup area.
H'0000 0000
H'0000 2000
< Internal flash >
L bank 1
(8K bytes)
L bank 0
(8K bytes)
H'0000 4000
L bank 2
(8K bytes)
L bank 63
(8K bytes)
L bsnk 62
(8K bytes)
H'0007 E000
H'0007 C000
< Internal RAM >
8K bytes
8K bytes
8K bytes
4K bytes
4K bytes
H'0080 4000
H'0080 6000
H'0080 8000
The table below shows Virtual-Flash Emulation Areas of the M32170F4 and M32170F3.
Table 12 Virtual-Flash Emulation Areas of the M32170F4 and M32170F3
Type
Virtual-Flash Emulation Areas
M32170F4VFP,M32170F4VWG
H' 0000 0000 - H' 0007 FFFF
M32170F3VFP,M32170F3VWG
H' 0000 0000 - H' 0005 FFFF
Figure 15 Virtual-Flash Emulation Areas of the M32170F4VFP (Replaced in Units of 4 Kbytes)
Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled,
the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1
> FELBANK2 > FESBANK0 > FESBANK1.
Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM
area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM
area and the virtual-flash setup area.
H'0000 0000
H'0000 1000
< Internal flash >
< Internal RAM >
S bank 1
(4K bytes)
H'0080 4000
S bank 0
(4K bytes)
H'0000 2000
S bank 2
(4K bytes)
8K bytes
S bank 127
(4K bytes)
S bank 126
(4K bytes)
H'0007 F000
H'0007 E000
8K bytes
8K bytes
4K bytes
4K bytes
H'0080 A000
H'0080 B000
Mitsubishi Microcomputers
24
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 16 Virtual-Flash Emulation Areas of the M32174F4VFP (Replaced in Units of 8 Kbytes)
Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled,
the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1
> FELBANK2 > FESBANK0 > FESBANK1.
Note 2: When access is made to the 8-Kbyte area (L bank) specified with virtual-flash bank registers 0-2, the internal RAM
area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM
area and the virtual-flash setup area.
Note 3: Internal RAM area (H'0080 C000-H'0080 DFFF) cannot be used as Virtual Flash Emulation area.
The table below shows Virtual-Flash Emulation Areas of the M32174F4 and M32174F3.
Table 13. Virtual-Flash Emulation Areas of the M32174F4 and M32174F3
Type Name
Virtual-Flash Emulation Areas
M32174F4VFP,M32174F4VWG
H' 0000 0000 - H' 0007 FFFF
M32174F3VFP,M32174F3VWG
H' 0000 0000 - H' 0005 FFFF
H'0000 0000
H'0000 2000
< Internal flash >
L bank 1
(8K bytes)
L bank 0
(8K bytes)
H'0000 4000
L bank 2
(8K bytes)
L bank 63
(8K bytes)
L bank 62
(8K bytes)
H'0007 E000
H'0007 C000
< Internal RAM >
8K bytes
8K bytes
8K bytes
8K bytes
4K bytes
4K bytes
H'0080 4000
H'0080 6000
H'0080 8000
H'0080 C000
H'0080 DFFF
Figure 17 Virtual-Flash Emulation Areas of the M32174F4VFP (Replaced in Units of 4 Kbytes)
Note 1: If the same bank area is set in multiple virtual-flash bank registers and the virtual-flash emulation enable bit is enabled,
the corresponding internal RAM area is assigned to either bank register according to the priority FELBANK0 > FELBANK1
> FELBANK2 > FESBANK0 > FESBANK1.
Note 2: When access is made to the 4-Kbyte area (S bank) specified with virtual-flash bank registers 0 and 1, the internal RAM
area is accessed. During virtual-flash emulation mode, RAM data can read and written to and from both the internal RAM
area and the virtual-flash setup area.
Note 3: Internal RAM area (H'0080 C000-H'0080 DFFF) cannot be used as Virtual Flash Emulation area.
H'0000 0000
H'0000 1000
< Internal flash >
< Internal RAM >
S bank 1
(4K bytes)
H'0080 4000
S bank 0
(4K bytes)
H'0000 2000
S bank 2
(4K bytes)
8K bytes
S bank 127
(4K bytes)
S bank 126
(4K bytes)
H'0007 F000
H'0007 E000
8K bytes
8K bytes
8K bytes
4K bytes
4K bytes
H'0080 A000
H'0080 B000
H'0080 C000
H'0080 DFFF
Mitsubishi Microcomputers
25
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Input/output Ports
The microcomputer has a total of 157 input/output ports
P0-P22. (However, P5 is reserved for future use.) The input/
output ports can be used as input ports or output ports by
setting up their direction registers.
Each input/output port is a dual-function pin shared with
Table 14 Outline of Input/output Ports
Item
Specification
Number of Port
Total 157 ports
P0
:
P00 - P07
(8 lines)
P1
:
P10 - P17
(8 lines)
P2
:
P20 - P27
(8 lines)
P3
:
P30 - P37
(8 lines)
P4
:
P41 - P47
(7 lines)
P6
:
P61 - P67
(7 lines)
P7
:
P70 - P77
(8 lines)
P8
:
P82 - P87
(6 lines)
P9
:
P93 - P97
(5 lines)
P10
:
P100 - P107
(8 lines)
P11
:
P110 - P117
(8 lines)
P12
:
P124 - P127
(4 lines)
P13
:
P130 - P137
(8 lines)
P14
:
P140 - P147
(8 lines)
P15
:
P150 - P157
(8 lines)
P16
:
P160 - P167
(8 lines)
P17
:
P172 - P177
(6 lines)
P18
:
P180 - P187
(8 lines)
P19
:
P190 - P197
(8 lines)
P20
:
P200 - P203
(4 lines)
P21
:
P210 - P217
(8 lines)
P22
:
P220 - P225
(6 lines)
Port function
The input/output ports can be set for input or output mode bitwise by using the input/output port
___
direction control register. (However, P64 is an SBI input-only port, and P221 is CAN input-only port.)
Pin function
Dual-functions shared with peripheral I/O or external extended signals (or multi-functions shared with
peripheral I/Os which have multiple functions.)
Pin function
P0-4, P225, P225 : Changed by setting CPU operation mode (MOD0 and MOD1 pins)
changeover
P6-22
: Changed by setting the input/output port operation mode register.
(However, peripheral I/O pin functions are selected using the peripheral I/O register.)
Table 15 CPU Operation Modes and P0-P4, P224, and P225 Pin Functions
MOD0
MOD1
Operation mode
Pin functions of P0-P4, P224, P225
VSS
VSS
Single-chip mode
nput/output port pin
VSS
VCCE
External extended mode
VCCE
VSS
Processor mode (FP pin = VSS)
VCCE
VCC
Reserved (use inhibited)
Note: VCC and VSS are connected to +5 V and GND, respectively.
otherinternal peripheral I/O or external extended bus signal
lines. These pin functions are selected by using the chip op-
eration mode select or the input/output port operation mode
registers. These input/output ports are interfaced using a
dedicated power supply to allow for connections to the pe-
ripheral circuits operating with 5V or 3.3V.
External extended signal pin
Mitsubishi Microcomputers
26
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 18 Input/output Ports and Pin Function Assignments
P0
P1
P2
P3
P4
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P5
DB0
0
1
2
3
4
5
6
7
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
A23
A24
A25
A26
A27
A28
A29
A30
A15
A16
A17
A18
A19
A20
A21
A22
BLW
BHW
RD
CS0
CS1
A13
A14
(P61)
(P62)
(P63)
SBI
SCLKI4/
SCLKO4
ADTRG
BCLK
WAIT
HREQ
HACK
RTDTXD
RTDRXD RTDACK
RTDCLK
TXD0
RXD0
SCLKI0/
SCLKO0
TXD1
RXD1
SCLKI1/
SCLKO1
TO16
TO17
TO18
TO19
TO20
TO11
TO12
TO13
TO14
TO15
TO10
TO9
TO8
TO3
TO4
TO5
TO6
TO7
TO2
TO1
TO0
TCLK0
TCLK1
TCLK2
TCLK3
TIN16
TIN17
TIN18
TIN19
TIN20
TIN21
TIN22
TIN23
TIN8
TIN9
TIN10
TIN11
TIN12
TIN13
TIN14
TIN15
TIN0
TIN1
TIN2
TIN3
TIN4
TIN5
TIN6
TIN7
CPU
operation mode
settings (Note1)
(Reserved)
Input/output
port operation
mode register
settings
Note 1: The pin function are selected by setting the MOD0 and MOD1 pins.
Note 2: The pin function are selected by setting the MOD0 and MOD1 pins. Also, use of this pin
requires caution because it has a debug event function.
P16
TO21
TO22
TO23
TO24
TO25
TO26
TO27
TO28
P17
TIN24
TIN25
TXD2
RXD2
TXD3
RXD3
P18
P19
TO29
TO30
TO31
TO32
TO33
TO34
TO35
TO36
P20
TXD4
RXD4
RXD5
P21
TO37
TO38
TO39
TO40
TO41
TO42
TO43
TO44
P22
CTX
CRX
(P222)
(P223)
A11
(Note2)
A12
(Note2)
TIN26
TIN27
TIN28
TIN29
TIN30
TIN31
TIN32
TIN33
TXD5
SCLKI5/
SCLKO5
Mitsubishi Microcomputers
27
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Item
Content
Number of channels
10 channels
Transfer request
Software trigger
Request from internal peripheral I/O: A-D converter, multijunction timer, or serial I/O
(reception completed, transmit buffer empty)
Cascaded connection between DMA channels possible (Note)
Maximum number of times transferred
256 times
Transferable address space
64 Kbytes (address space from H'0080 0000 to H'0080 FFFF)
Transfers between internal peripheral I/Os, between internal RAM and internal peripheral IO,
and between internal RAMs are supported
Transfer data size
16 bits or 8 bits
Transfer method
Single transfer DMA (control of the internal bus is relinquished for each transfer performed),
dual-address transfer
Transfer mode
Single transfer mode
Direction of transfer
One of three modes can be selected for the source and destination of transfer:
Address fixed
Address increment
32-channel ring buffer
Channel priority
Channel 0 > channel 1 > channel 2 > channel 3 > channel 4 >
channel 5 > channel 6 > channel 7 > channel 8 > channel 9
(Fixed priority)
Maximum transfer rate
13.3 Mbytes per second (when internal peripheral clock = 20 MHz)
Interrupt request
Group interrupt request can be generated when each transfer count register underflows
Transfer area
64 Kbytes from H'0080 0000 to H'0080 FFFF (Transfer is possible in the entire internal
RAM/SFR area)
Note: The following DMA channels can be cascaded.
DMA transfer on channel 1 started at end of one DMA transfer on channel 0
DMA transfer on channel 2 started at end of one DMA transfer on channel 1
DMA transfer on channel 0 started at end of one DMA transfer on channel 2
DMA transfer on channel 4 started at end of one DMA transfer on channel 3
DMA transfer on channel 6 started at end of one DMA transfer on channel 5
DMA transfer on channel 7 started at end of one DMA transfer on channel 6
DMA transfer on channel 5 started at end of one DMA transfer on channel 7
DMA transfer on channel 9 started at end of one DMA transfer on channel 8
DMA transfer on channel 5 started at end of all DMA transfers on channel 0 (underflow of transfer count register)
Built-in 10-Channel DMAC
The microcomputer contains 10 channels of DMAC, allowing
for data transfer between internal peripheral I/Os, between
internal RAM and internal peripheral I/O, and between inter-
nal RAMs.
DMA transfer requests can be issued from the user-cre
ated software, as well as can be triggered by a signal gener-
ated by the internal peripheral I/O (A-D converter, MJT, or
serial I/O).
Table 16 Outline of the DMAC
The microcomputer also supports cascaded connection be-
tween DMA channels (starting DMA transfer on a channel at
end of transfer on another channel). This makes advanced
transfer processing possible without causing any additional
CPU load.
Mitsubishi Microcomputers
28
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 19 Block Diagram of the DMAC
DMA channel 8
Source
Destination
Transfer count
udf
Source
Destination
Transfer count
udf
udf
DMA channel 2
udf
DMA
request
selector
DMA
request
selector
A-D0 conversion completed
DMA channel 0
Software start
MJT (TIN13 input signal)
One DMA0 transfer completed
Inter
nal b
us
Software start
Software start
Serial I/O0 (reception completed)
Interrupt
request
One DMA2 transfer completed
MJT (TIO8_udf)
MJT (input event bus 2)
MJT (output event bus 0)
MJT (TIN19 input signal)
Software start
MJT (TIN18 input signal)
One DMA1 transfer completed
MJT (output event bus 0)
Software start
Serial I/O0 (transmit buffer empty)
Serial I/O1 (reception completed)
DMA channel 1
DMA channel 3
DMA channel 4
Determination block
Transfer count
udf
DMA start
MJT (TIN0 input signal)
All DMA0 transfer completed (udf)
Software start
MJT (TIN1 input signal)
One DMA5 transfer completed
Software start
Software start
Serial I/O3 (transmit buffer empty)
One DMA7 transfer completed
One DMA8 transfer completed
Serial I/O2 (reception completed)
MJT (TIN20 input signal)
Serial I/O1 (transmit buffer empty)
MJT (TIN8 input signal)
Software start
MJT (TIN2 input signal)
One DMA6 transfer completed
Serial I/O2 (transmit buffer empty)
Software start
MJT (intput event bus 0)
Serial I/O3 (reception completed)
MJT (TIN7 input signal)
udf
DMA channel 7
DMA channel 5
Interrupt
request
DMA channel 6
DMA channel 9
Determination block
DMA start
Internal bus arbitration
DMA
request
selector
udf
DMA
request
selector
Source
Destination
Transfer count
udf
Source
Destination
Transfer count
udf
DMA
request
selector
Source
Destination
Transfer count
udf
Internal bus arbitration
DMA
request
selector
DMA
request
selector
DMA
request
selector
DMA
request
selector
DMA
request
selector
One DMA3 transfer completed
Destination
Source
Source
Source
Source
Source
Destination
Destination
Destination
Destination
Transfer count
Transfer count
Transfer count
Transfer count
Mitsubishi Microcomputers
29
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Built-in 64-Channel Multijunction Timers (MJT)
The microcomputer contains a total of 64 channels of
multijunction timers consisting of 35 channels of 16-bit out-
put related timers, 10 channels of 16-bit input/output related
timers, 11 channels of 16-bit input related timers, eight chan-
nels of 32-bit input related timers. Each timer has multiple
operation modes to choose from, depending on the pur-
poses of use.
Also, the maltijunction timers internally have a clock bus, in-
put event bus, and an output event bus, so that multiple tim-
ers can be used in combination allowing for a flexible timer
configuration.
The output related timers have a correcting function that
allows the timer's count value to be incremented or
decremented as necessary while count is in progress, mak-
ing real time output control possible.
Timer
CLK
E N
E /L
PRS
Clock bus
Input event bus
E /L
Timer
CLK
E N
Interrupt output
Interrupt output
Output event bus
F/F
TO pin
TIN pin
TCLK pin
Note: This is a conceptual diagram and does not show the actual timer configuration.
E /L
PRS
: Edge/Level selector
: Prescaler
: Junction box (Selector)
: Output flip-flop
F/F
To DMAC,
A-D converter
F/F
TO pin
Output related timer : 35ch
Input/output related timer : 10ch
16-bit input related timer : 11ch
32-bit input related timer : 8ch
1/2 internal
peripheral clock
Figure 20 Conceptual Diagram of the Multijunction Timer (MJT)
Mitsubishi Microcomputers
30
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Table 17 Outline of Multijunction Timers (1/2)
Name
Type
Number of channels
Content
TOP
Output-related
11
One of three input modes can be selected in software.
(Timer Output)
16-bit timer
< With correction function >
(down-counter)
Single-shot output mode
Delayed single-shot output mode
< Without correction function >
Continuous output mode
TIO
Input/output-related
10
One of three input modes or four output modes can be
(Timer
16-bit timer
selected by software.
Input Output)
(down-counter)
< Input modes >
Measure clear input mode
Measure free-run input mode
Noise processing input mode
< Output mode without correction function
PWM output mode
Single-shot output mod
Delayed single-shot output mode
Continuous output mode
TMS
Input-related
8
16-bit input measure timer.
(Timer
16-bit timer
Measure Small)
(up counter)
TML
Input-related
8
32-bit input measure timer.
(Timer
32-bit timer
Measure Large)
(up counter)
TID
Input-related
3
One of three input modes can be selected in software.
(Timer
16-bit timer
Fixed cycle mode
Input Derivation)
(up counter)
Event count mode
Multiply-by-4 event count mode
Mitsubishi Microcomputers
31
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Name
Type
Number of channels
Content
TOD
output-related
16
One of four output modes can be selected in software.
(Timer
16-bit timer
< No correction function >
output Modification)
(down-counter)
PWM output mode
Single-shot output mode
Delayed single-shot output mode
Continuous output mode
TOM
output-related
8
One of four output modes can be selected in software.
(Timer
16-bit timer
< No correction function >
output Modification)
(down-counter)
PWM output mode
Single-shot PWM output mode
One-shot output mode
Continuous output mode
Table 18 Outline of Multijunction Timers (2/2)
Mitsubishi Microcomputers
32
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 21 Block Diagram of Multijunction Timers (MJT) (1/4)
IRQ2
IRQ12
IRQ12
IRQ12
clk
en
udf
TOP 0
Clock bus
Input event bus
clk
en
udf
TOP 1
clk
en
udf
TOP 2
clk
en
udf
TOP 3
Output event bus
TCLK0S
TO 0
IRQ9
3 2 1 0
1/2 internal
peripheral
clock
IRQ8
clk
en
udf
TOP 4
clk
en
udf
TOP 5
TCLK0
TIN0
TIN7
TCLK1
S
S
TIN0S
clk
en
udf
TOP 6
clk
en
udf
TOP 7
S
S
S
IRQ9
TIN1
IRQ9
TIN2
S
S
clk
en
udf
TOP 8
clk
en
udf
TOP 9
clk
en
udf
TOP 10
clk
en/cap
udf
TIO 0
clk
en/cap
udf
TIO 1
clk
en/cap
udf
TIO 2
clk
en/cap
udf
TIO 3
clk
en/cap
udf
TIO 4
S
S
TIN3
S
S
TIN4
TIN5
S
S
IRQ12
TIN6
PRS1
PRS0
clk
en/cap
udf
TIO 5
S
S
IRQ8
TIN8
TCLK2
clk
en/cap
udf
TIO 6
S
S
IRQ8
TIN9
clk
en/cap
udf
TIO 7
S
S
IRQ8
TIN10
S
S
clk
en/cap
udf
TIO 8
clk
en/cap
udf
TIO 9
IRQ8
TIN11
S
S
F/F0
F/F1
F/F2
F/F3
F/F4
F/F5
F/F6
F/F7
F/F8
F/F9
F/F10
F/F11
F/F12
F/F13
F/F14
F/F15
S
F/F16
F/F17
F/F18
F/F19
F/F20
S
: Selector
F/F
: Output flip-flop
PRS0-5
: Prescaler
S
S
S
S
S
S
S
S
S
S
S
S
S
S
IRQ2
IRQ2
IRQ2
IRQ2
IRQ2
TO 1
TO 2
TO 3
TO 4
TO 5
TO 6
TO 7
TO 8
TO 9
TO 10
TO 11
TO 12
TO 13
TO 14
TO 15
IRQ1
IRQ1
IRQ6
IRQ6
IRQ5
IRQ0
IRQ0
IRQ0
IRQ0
IRQ4
TO 16
TO 17
TO 18
TO 19
TO 20
IRQ4
DRQ0
IRQ3
IRQ3
3 2 1 0
0 1 2 3
3 2 1 0
3 2 1 0
PRS2
IRQ4
IRQ4
0 1 2 3
TIN1S
TIN2S
TIN3S
TIN4S
TIN5S
TIN6S
TCLK1S
TCLK2S
TIN7S
TIN8S
TIN9S
TIN10S
TIN11S
DRQ7
DRQ8
DRQ9
DRQ10
DRQ11
Mitsubishi Microcomputers
33
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 22 Block Diagram of Multijunction Timers (MJT) (2/4)
Clock bus
Input event bus
3 2 1 0
3 2 1 0
clk
TMS 0
S
ovf
cap3
cap2
cap1
cap0
S
S
S
S
TCLK3
TCLK3S
DRQ3
IRQ10
TIN12
TIN13
TIN14
TIN15
clk
TMS 1
ovf
cap3
cap2
cap1
cap0
S
S
S
S
S
DRQ5
TIN16
TIN17
TIN18
TIN19
DRQ6
IRQ10
IRQ10
IRQ10
IRQ10
IRQ10
IRQ10
IRQ10
clk
TML0
cap3
cap2
cap1
cap0
S
S
S
S
TIN20
TIN21
TIN22
TIN23
IRQ11
IRQ11
IRQ11
IRQ11
1/2 internal
peripheral clock
Output event bus
0 1 2 3
IRQ7
IRQ7
3 2 1 0
3 2 1 0
0 1 2 3
TIN12S
TIN13S
TIN14S
TIN15S
TIN16S
TIN17S
TIN18S
TIN19S
TIN20S
TIN21S
TIN22S
TIN23S
S
DRQ12
clk
TML1
cap3
cap2
cap1
cap0
S
S
S
S
TIN30
TIN31
TIN32
TIN33
TIN30S
TIN31S
TIN32S
TIN33S
S
IRQ18
IRQ18
IRQ18
IRQ18
1/2 internal
peripheral clock
S
: Serector
AD0TRG
(To A-D converter)
DRQ2
DRQ4
Mitsubishi Microcomputers
34
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Clock bus
Input event bus
3 2 1 0
3 2 1 0
Output event bus
0 1 2 3
3 2 1 0
3 2 1 0
0 1 2 3
clk
TID0
ovf
udf
TIN24
TIN25
1/2 internal
peripheral
clock
IRQ14
clk
TOD0_0
udf
F/F21
clk
TOD0_1
udf
F/F22
TO21
TO22
clk
TOD0_2
udf
F/F23
clk
TOD0_3
udf
F/F24
TO23
TO24
clk
TOD0_4
udf
F/F25
clk
TOD0_5
udf
F/F26
TO25
TO26
clk
TOD0_6
udf
F/F27
clk
TOD0_7
udf
F/F28
TO27
TO28
IRQ13
IRQ13
IRQ13
IRQ13
IRQ13
IRQ13
IRQ13
IRQ13
CLK1 CLK2
PRS3
clk
TID1
TIN26
TIN27
1/2 internal
peripheral
clock
IRQ15
clk
TOD1_0
udf
F/F29
clk
TOD1_1
udf
F/F30
TO29
TO30
clk
TOD1_2
udf
F/F31
clk
TOD1_3
udf
F/F32
TO31
TO32
clk
TOD1_4
udf
F/F33
clk
TOD1_5
udf
F/F34
TO33
TO34
clk
TOD1_6
udf
F/F35
clk
TOD1_7
udf
F/F36
TO35
TO36
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
CLK1 CLK2
PRS4
EN
EN
EN
EN
EN
EN
clk
TID2
TIN28
TIN29
1/2 internal
peripheral
clock
clk
TOM0_0
udf
F/F37
clk
TOM0_1
udf
F/F38
TO37
TO38
clk
TOM0_2
udf
F/F39
clk
TOM0_3
udf
F/F40
TO39
TO40
clk
TOM0_4
udf
F/F41
clk
TOM0_5
udf
F/F42
TO41
TO42
clk
TOM0_6
udf
F/F43
clk
TOM0_7
udf
F/F44
TO43
TO44
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
IRQ16
CLK1 CLK2
PRS5
EN
EN
EN
EN
EN
EN
EN
EN
AD1TRG
(To A-D converter)
ovf
udf
ovf
udf
IRQ17
EN
EN
Figure 23 Block Diagram of Multijunction Timers (MJT) (3/4)
Mitsubishi Microcomputers
35
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 24 Block Diagram of Multijunction Timers (MJT) (4/4)
udf
end
Clock bus
Input event bus
3 2 1 0
3 2 1 0
Output event bus
0 1 2 3
3 2 1 0
3 2 1 0
0 1 2 3
AD0
completed
TIO8-udf
S
DMA0
udf
end
DMAIRQ0
S
DMA1
udf
end
DMAIRQ0
TIN13
udf
TIN18
S
DMA3
udf
end
DMAIRQ0
S
DMA4
udf
DMAIRQ0
TIN19
SIO0-TXD
SIO1-RXD
SIO0-RXD
S
DMA5
udf
end
DMAIRQ1
DMAIRQ1
SIO2-RXD
SIO1-TXD
DMAIRQ1
DMAIRQ1
SIO2-TXD
SIO3-RXD
DMAIRQ1
SIO3-TXD
TIN2
TIN7
TIN8
TIN20
TIN1
TIN0
udf
end
S
DMA2
udf
DMAIRQ0
S
DMA6
udf
end
DMA7
udf
end
S
DMA8
udf
end
S
S
DMA9
udf
S
: Selector
Mitsubishi Microcomputers
36
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Built-in Two Independent A-D Converters
The microcomputer contains two 16-channel converters with
10-bit resolution (A-D0 converter and A-D1 converter). In
addition to single conversion on each channel, continuous
A-D conversion on a combined group of 4, 8, and 16 chan-
nels is possible. The A-D converted value can be read out in
either 10 bits or 8 bits.
Table 19 Outline of the A-D Converters
Item
Content
Analog input
16 channels
2
A-D conversion method
Successive approximation method.
Resolution
10 bits (Conversion results can be read out in either 10 or 8 bits.)
Absolute accuracy (Note 1)
Normal rate mode
+2 LSB
(Conditions: Ta = -40 ~ +125
C,
Double rate mode
+2 LSB
AVCC0,1 = VREF0,1 = 5.12V)
Conversion mode
A-D conversion mode,comparator mode
Operation mode
Single mode, scan mode
Scan mode
Single -shot scan mode, continuous scan mode.
Conversion start trigger
Software start
Started by setting A-D conversion start bit to 1.
Hardware start
A-D0 converter started by MJT output event bus 3,
A-D1 converter started by TID1 overflow or underflow.
_____
Started by external ADTRG pin input.
Conversion rate
During single mode
Normal
299
1/ f (BCLK) (Note 2)
f(BCLK) : Internal peripheral clock
(Shortest time )
Double speed
173
1/ f (BCLK)
operating frequency
During comparator mode
Normal
47
1/ f (BCLK)
(Shortest time )
Double speed
29
1/ f (BCLK)
Interrupt request generation
When A-D conversion is finished, when comparate operation is finished, when single-shot
scan is finished, or when one cycle of continuous scan is finished.
DMA transfer request generation
When A-D conversion is finished, when comparate operation is finished, when single-shot
(Note 3)
scan is finished, or when one cycle of continuous scan is finished.
Note 1: The rated value of conversion accuracy here is that of the microcomputer's own as a single unit which can be exhibited when the
microcomputer is used in an environment where it may not be affected by the power supply wiring or noise on the board.
Note 2: When BCLK = 20 MHz, this is1/f (BCLK) = 50ns.
Note 3: The DMA transfer request generation function is available for only the A-D0 converter. The A-D1 converter does not have this function.
In addition to ordinary A-D conversion, the converters sup-
port comparator mode in which the set value and A-D con-
verted value are compared to determine which is larger or
smaller than the other.
When A-D conversion is finished, the converters can generated
a DMA transfer request (A-D0 converter only), as well as an
interrupt.
The A-D converters are interfaced using a dedicated power
supply to allow for connections to the peripheral circuits op-
erating with 5 V or 3.3V.
Mitsubishi Microcomputers
37
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Figure 25 Block Diagram of the A-D0 Converter
AD0IN0
AD0IN1
AD0IN2
AD0IN3
AD0IN4
AD0IN5
AD0IN6
AD0IN7
Selector
Interrupt request
AVSS0
VREF0
10-bit A-D Successive
Approximation Register
(AD0SAR)
10-bit A-D0 Data Register 0
10-bit A-D0 Data Register 1
Single Mode Register
A-D comparate
Data Register
A-D Control Circuit
Mode selection
Channel selection
Conversion time
selection
Flag control
Interrupt control
10-bit D-A Converter
Comparator
AD0IN8
AD0IN9
AD0N10
AD0IN11
AD0IN12
AD0IN13
AD0IN14
AD0IN15
AD0CMP
AD0DT0
AD0DT1
AD0DT2
AD0DT3
AD0DT4
AD0DT5
AD0DT6
AD0DT7
AD0DT8
AD0DT9
AD0DT10
AD0DT11
AD0DT12
AD0DT13
AD0DT14
AD0DT15
DMA transfer request
Successive Approximation
-type A-D Converter Unit
Internal data bus
Scan Mode Register
P67/ADTRG
AD0SCM0,1
AD0SIM0,1
AVCC0
Output event bus 3
(Multijunction timer)
10-bit readout
8-bit readout
Shifter
10-bit A-D0 Data Register 2
10-bit A-D0 Data Register 3
10-bit A-D0 Data Register 4
10-bit A-D0 Data Register 5
10-bit A-D0 Data Register 6
10-bit A-D0 Data Register 7
10-bit A-D0 Data Register 8
10-bit A-D0 Data Register 9
10-bit A-D0 Data Register 10
10-bit A-D0 Data Register 11
10-bit A-D0 Data Register 12
10-bit A-D0 Data Register 13
10-bit A-D0 Data Register 14
10-bit A-D0 Data Register 15
Mitsubishi Microcomputers
38
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 26 Block Diagram of the A-D1 Converter
AD1IN0
AD1IN1
AD1IN2
AD1IN3
AD1IN4
AD1IN5
AD1IN6
AD1IN7
Selector
Interrupt request
AVSS1
VREF1
10-bit A-D Successive
Approximation Register
(AD1SAR)
10-bit A-D1 Data Register 0
10-bit A-D1 Data Register 1
Single Mode Register
A-D Comparate
Data Register
A-D Control Circuit
Mode selection
Channel selection
Conversion time
selection
Flag control
Interrupt control
10-bit D-A Converter
Comparator
AD1IN8
AD1IN9
AD1N10
AD1IN11
AD1IN12
AD1IN13
AD1IN14
AD1IN15
AD1CMP
AD1DT0
AD1DT1
AD1DT2
AD1DT3
AD1DT4
AD1DT5
AD1DT6
AD1DT7
AD1DT8
AD1DT9
AD1DT10
AD1DT11
AD1DT12
AD1DT13
AD1DT14
AD1DT15
Successive Approximation
-type A-D Converter Unit
Internal data bus
Scan Mode Register
P67/ADTRG
AD1SCM0,1
AD1SIM0,1
AVCC1
TID1 underflow
/overflow
10-bit readout
8-bit readout
Shifter
10-bit A-D1 Data Register 2
10-bit A-D1 Data Register 3
10-bit A-D1 Data Register 4
10-bit A-D1 Data Register 5
10-bit A-D1 Data Register 6
10-bit A-D1 Data Register 7
10-bit A-D1 Data Register 8
10-bit A-D1 Data Register 9
10-bit A-D1 Data Register 10
10-bit A-D1 Data Register 11
10-bit A-D1 Data Register 12
10-bit A-D1 Data Register 13
10-bit A-D1 Data Register 14
10-bit A-D1 Data Register 15
Note: The A-D converter does not have DMA transfer request generation function.
Mitsubishi Microcomputers
39
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
6-channel High-speed Serial I/Os
The microcomputer contains six channels of serial I/Os con-
sisting of four channels that can be set for CSIO mode
(clock-synchronized serial I/O) or UART mode (asynchro-
nous serial I/O) and two other channels that can only be set
for UART mode.
The SIO has the function to generate a DMA transfer re-
quest when data reception is completed or the transmit reg-
ister becomes empty, and is capable of high-speed serial
communication without causing any additional CPU load.
Table 20 Outline of Serial I/O
Item
Content
Number of channels
CSIO/UART: 4 channels (SIO0,SIO1,SIO4,SIO5)
UART only : 2 channels (SIO2,SIO3)
Clock
During CSIO mode : Internal clock / external clock, selectable (Note1)
During UART mode : Internal clock only
Transfer mode
Transmit half-duplex, receive half-duplex, transmit/receive full-duplex
BRG count sourcef
(BCLK), f(BCLK)/8, f(BCLK)/32, f(BCLK)/256 (When internal clock is selected) (Note2)
Data format
CSIO mode :
Data length = Fixed to 8 bits
Order of transfer = Fixed to LSB first
UARTmode :
Start bit = 1 bit
Character length = 7, 8, or 9 bits
Parity bit = Added or not added (When added, selectable between
odd and even parity)
Stop bit = 1 or 2 bits
Order of transfer = Fixed to LSB first
Baud rate
CSIO mode :
152 bits per second to 2 Mbits per second (when operating with f(BCLK) = 20 MHz)
UARTmode :
19 bits per second to 156 Kbits per second (when operating with f(BCLK) = 20 MHz)
Error detection
CSIO mode :
Overrun error only
UARTmode :
Overrun, parity, and framing errors
(The error-sum bit indicates which error has occurred)
Fixed cycle clock
When SIO0, SIO1, SIO4, or SIO5 is in UART mode, this function outputs a 1/2 BRG clock from the SCLK pin.
output function
Note 1: During CSIO mode, the maximum input frequency of an external clock is f(BCLK) divided by 16.
Note 2: When f(BCLK) is selected for the BRG count source, the BRG set value is subject to limitations.
Mitsubishi Microcomputers
40
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 27 Block Diagram of Serial I/O
SCLKI0/ SCLKO0
BCLK,
BCLK/8,
BCLK/32,
BCLK/256
Baud rate
generator
(BRG)
BCLK
(Set value + 1)
1
Inter
nal data b
u
s
CSIO Mode
When internal clock selected
CSIO
Mode
UART
Mode
When internal clock selected
1/16
1/2
Clock
divider
RXD0
TXD0
Receive interrupt
Transmit/
receive
control
circuit
SIO0 Transmit Buffer Register
SIO0 Transmit Shift Register
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
To DMAC3
SIO0 Receive Shift Register
SIO0 Receive Buffer Register
When extended clock selected
When UART mode selected
Note 2: SIO2 and SIO3 do not have the SCLKI/SCLKO function.
Note 1: When BCLK is selected, the BRG set value is subject to limitations.
SCLKI1/ SCLKO1
To DMAC6
To interrupt
controller
SIO0
SIO1
SIO2
SIO3
RXD1
TXD1
Transmit/
receive
control
circuit
SIO1 Transmit Shift Register
SIO1 Receive Shift Register
To DMAC7
RXD2
TXD2
Transmit/
receive
control
circuit
SIO2 Transmit Shift Register
SIO2 Receive Shift Register
To DMAC9
RXD3
TXD3
Transmit/
receive
control
circuit
SIO3 Transmit Shift Register
SIO3 Receive Shift Register
Receive interrupt
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
Receive interrupt
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
Receive interrupt
Receive DMA transfer request
Transmit interrupt
Transmit DMA transfer request
To interrupt
controller
To DMAC8
To DMAC5
To DMAC3
To DMAC4
SIO4
RXD4
TXD4
Transmit/
receive
control
circuit
SIO4 Transmit Shift Register
SIO4 Receive Shift Register
Receive interrupt
Transmit interrupt
SIO5
RXD5
TXD5
Transmit/
receive
control
circuit
SIO5 Transmit Shift Register
SIO5 Receive Shift Register
Receive interrupt
Transmit interrupt
SCLKI4 / SCLKO4
SCLKI5 / SCLKO5
To interrupt
controller
To interrupt
controller
Mitsubishi Microcomputers
41
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
CAN Module
The M32170 and M32174 Group contains two Full CAN
modules compliant with CAN Specification V2.0B (CAN0
and CAN1), each of which has 16-channel message slots
and three mask registers.
Figure 28 Block Diagram of the CAN Module
CTX
CRX
CAN0 Protocol
Controller
2.0B active
CAN0 Message
Slot 0-15
Control Register
CAN0 Global
Mask Register
CAN0 Local
Mask Register A
CAN0 Local
Mask Register B
CAN0 Extended
Register
Message Memory
Acceptance
Filtering
16-bit Timer
CAN0 Time Stamp
Register
CAN0 Configuration
Register
CAN0 Slot
Status Register
CAN0 Slot
Interrupt Control
Register
CAN0 REC
Register
CAN0 TEC
Register
CAN0 Error
Interrupt Control
Register
Interrupt Control
Circuit
CAN0 Transmit/Receive
& Error Interrupt
Data bus
(1) Message ID
(2) Data length code
(3) Message data
(4) Time stamp
CAN0 Status
Register
CAN0 Control
Register
Mitsubishi Microcomputers
42
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
8-level Interrupt Controller
The Interrupt Controller controls interrupt requests from
each internal peripheral I/O (31 sources) by using eight pri-
ority levels assigned to each interrupt source, including in-
terrupts disabled. In addition to these interrupts, it handles
System Break Interrupt (SBI), Reserved Instruction Excep-
tion (RIE), and Address Exception (AE) as nonmaskable in-
terrupts.
Wait Controller
The Wait Controller supports access to external devices.
For access to an external extended area of up to 1 Mbytes
(during external extended or processor mode), the Wait
Controller controls bus cycle extension by inserting one to
____
four wait cycles or using external WAIT signal input.
Real-Time Debugger
(RTD)
RTDCLK
RTDRXD
RTDTXD
RTDACK
Command
address
Data
Internal RAM
M32R
CPU
32170, 32174 Group
Data
Data
Data Bus(CPU)
Data Bus(RTD)
R/W without CPU intervention
Virtual-DPRAM
structure
Figure 29 Conceptual Diagram of the Realtime Debugger (RTD)
Realtime Debugger (RTD)
The Realtime Debugger (RTD) provides a function for ac-
cessing directly from the outside to the internal RAM. It uses
a dedicated clock-synchronized serial I/O to communicate
with the outside.
Use of the RTD communicating via dedicated serial lines al-
lows the internal RAM to be read out and rewritten without
having to halt the CPU.
Mitsubishi Microcomputers
43
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
CPU Instruction Set
The M32R employs a RISC architecture, supporting a total
of 83 discrete instructions.
(1) Load/store instructions
Perform data transfer between memory and registers.
LD
Load
LDB
Load byte
LDUB
Load unsigned byte
LDH
Load halfword
LDUH
Load unsigned halfword
LOCK
Load locked
ST
Store
STB
Store byte
STH
Store halfword
UNLOCK
Store unlocked
(2) Transfer instructions
Perform register to register transfer or register to immediate
transfer
.
LD24
Load 24-bit immediate
LDI
Load immediate
MV
Move register
MVFC
Move from control register
MVTC
Move to control register
SETH
Set high-order 16-bit
(3) Branch instructions
Used to change the program flow.
BC
Branch on C-bit
BEQ
Branch on equal
BEQZ
Branch on equal zero
BGEZ
Branch on greater than or equal zero
BGTZ
Branch on greater than zero
BL
Branch and link
BLEZ
Branch on less than or equal zero
BLTZ
Branch on less than zero
BNC
Branch on not C-bit
BNE
Branch on not equal
BNEZ
Branch on not equal zero
BRA
Branch
JL
Jump and link
JMP
Jump
NOP
No operation
(4) Arithmetic/logic instructions
Perform comparison, arithmetic/logic operation, multiplica-
tion/division, or shift between registers.
Comparison
CMP
Compare
CMPI
Compare immediate
CMPU
Compare unsigned
CMPUI
Compare unsigned immediate
Logical operation
AND
AND
AND3
AND 3-operand
NOT
Logical NOT
OR
OR
OR3
OR 3-operand
XOR
Exclusive OR
XOR3
Exclusive OR 3-operand
Arithmetic operation
ADD
Add
ADD3
Add 3-operand
ADDI
Add immediate
ADDV
Add (with overflow checking)
ADDV3
Add 3-operand
ADDX
Add with carry
NEG
Negate
SUB
Subtract
SUBV
Subtract (with overflow checking)
SUBX
Subtract with borrow
Multiplication/division
DIV
Divide
DIVU
Divide unsigned
MUL
Multiply
REM
Remainder
REMU
Remainder unsigned
Shift
SLL
Shift left logical
SLL3
Shift left logical 3-operand
SLLI
Shift left logical immediate
SRA
Shift right arithmetic
SRA3
Shift right arithmetic 3-operand
SRAI
Shift right arithmetic immediate
SRL
Shift right logical
SRL3
Shift right logical 3-operand
SRLI
Shift right logical immediate
(5) Instructions for the DSP function
Perform 32 bit
16 bit or 16 bit
16 bit multiplication or sum-
of-products calculation. These instructions also perform
rounding of the accumulator data or transfer between accu-
mulator and general-purpose register.
MACHI
Multiply-accumulate high-order
halfwords
MACLO
Multiply-accumulate low-order
halfwords
MACWHI
Multiply-accumulate word and
high-order halfword
MACWLO
Multiply-accumulate word and
low-order halfword
MULHI
Multiply high-order halfwords
MULLO
Multiply low-order halfwords
MULWHI
Multiply word and high-order
halfword
MULWLO
Multiply word and low-order
halfword
MVFACHI
Move from accumulator high-order word
MVFACLO
Move from accumulator low-order word
MVFACMI
Move from accumulator middle-order
word
MVTACHI
Move to accumulator high-order word
MVTACLO
Move to accumulator low-order word
RAC
Round accumulator
RACH
Round accumulator halfword
(6) EIT related instructions
Start trap or return from EIT processing.
RTE
Return from EIT
TRAP
Trap
Mitsubishi Microcomputers
44
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
Figure 30 Instructions for the DSP Function
Rsrc1
0
15 16
31
H
L
0
15 16
31
H
L
MACLO instruction
MACHI instruction
Rsrc2
ACC
63
+
63
ACC
Rsrc1
0
31
32 bit
0
15 16
31
H
L
MACWLO instruction
MACWHI instruction
Rsrc2
ACC
63
63
ACC
Rsrc1
0
15 16
31
H
ACC
63
L
0
15 16
31
H
L
MULLO instruction
MULHI instruction
Rsrc2
Rsrc1
0
31
ACC
63
0
15 16
31
H
L
MULWLO instruction
MULWHI instruction
Rsrc2
32 bit
63
ACC
RAC
instruction
63
ACC
RACH
instruction
< Ropund off instruction >
sign
0
data
sign
0
data
63
63
Rdest
1
63
15 16
31
47 48
MVFACHI
instruction
ACC
MVFACLO
instruction
MVFACMI
instruction
Rsrc
0
31
63
31 32
ACC
MVTACLO
instruction
MVTACHI
instruction
< Multiply instruction >
< Multiply-accumulate instruction >
< Accumulator - register transfer instruction >
+
+
+
0
0
0
0
0
0
0
32
0
0
0
0
0
0
Mitsubishi Microcomputers
45
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
Package Dimensions Diagram
QFP240-P-3232-0.50
Weight(g)
JEDEC Code
EIAJ Package Code
Lead Material
Cu Alloy
240P6Y-A
Plastic 240pin 32
32mm body QFP
0.35
0.45
Symbol
Min
NomMax
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225
I
2
1.2
M
D
32.6
M
E
32.6
10
0
0.1
1.3
0.7
0.5
0.3
34.8
34.6
34.4
34.8
34.6
34.4
0.5
32.1
32.0
31.9
32.1
32.0
31.9
0.2
0.15
0.13
0.3
0.2
0.15
3.6
0.25
4.1
e
e
e
E
c
H
E
1
60
61
H
D
D
M
D
M
E
A
F
b
A
1
A
2
L
1
L
y
b
2
I
2
Recommended Mount Pad
Detail F
240
120
121
180
181
Mitsubishi Microcomputers
46
2001-5-14 Rev.1.0
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
32170 Group, 32174 Group
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Weight(g)
JEDEC Code
EIAJ Package Code
255F7F
255pin 17
17mm body FBGA
0.8
19=15.2
A
0.8TYP
17TYP
0.8
19=15.2
0.8TYP
B
1.2MAX
C
0.1
C
0.35
0.05
(16.6)
17TYP
(16.6)
0.20
C
B
0.2
4
255-
0.45
0.05
0.08
C
M
AB
Under Development
0.20 C A
Y
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
Note: 255FBGA is currently under development.
Mitsubishi Microcomputers
47
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
2001-5-14 Rev.1.0
32170 Group, 32174 Group
MEMO
SINGLE-CHIP 32-BIT CMOS MICROCOMPUTER
Mitsubishi Microcomputers
2001-5-14 Rev.1.0
32170Group, 32174Group
HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN
2001 MITSUBISHI ELECTRIC CORP.
New publication, effective May 2001.
Specifications subject to change without notice.
Keep safety first in your circuit designs!
Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to
personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable
material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property
rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party.
Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples
contained in these materials.
All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Mitsubishi
Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for
the latest product information before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Mitsubishi Electric Corporation by various means, including the Mitsubishi Semiconductor home page (http://www.mitsubishichips.com).
When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on
the applicability of the information and products. Mitsubishi Electric Corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein.
Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric
Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical,
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The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials.
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Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Rev.
Revision Description
Rev.
No. Page
Point
date
1.0
First Edition
010514
Revision Description List
32170 Group, 32174 Group Data Sheet
(1/1)
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