MOSEL VITELIC
1
V53C16256H
256K x 16 FAST PAGE MODE
CMOS DYNAMIC RAM
PRELIMINARY
V53C16256H Rev. 2.3 June 1998
HIGH PERFORMANCE
30
35
40
45
50
60
Max. RAS Access Time, (t
RAC
)
30 ns
35 ns
40 ns
45 ns
50 ns
60 ns
Max. Column Address Access Time, (t
CAA
)
16 ns
18 ns
20 ns
22 ns
24 ns
30 ns
Min. Fast Page Mode Cycle Time, (t
PC
)
19 ns
21 ns
23 ns
25 ns
28 ns
35 ns
Min. Read/Write Cycle Time, (t
RC
)
65 ns
70 ns
75 ns
80 ns
90 ns
110 ns
Features
s
256K x 16-bit organization
s
Fast Page Mode for a sustained data rate
of 53 MHz.
s
RAS access time: 30, 35, 40, 45, 50, 60 ns
s
Dual CAS Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
s
Refresh Interval: 512 cycles/8 ms
s
Available in 40-pin 400 mil SOJ and
40/44L-pin 400 mil TSOP-II packages
s
Single +5V
10% Power Supply
s
TTL Interface
Description
The V53C16256H is a 262,144 x 16 bit high-
performance CMOS dynamic random access mem-
ory. The V53C16256H offers Fast Page mode with
dual CAS inputs. An address, CAS and RAS input
capacitances are reduced to one quarter when the
x4 DRAM is used to construct the same memory
density. The V53C16256H has symmetric address
and accepts 512 cycle 8ms interval.
All inputs are TTL compatible. Fast Page Mode
operation allows random access up to 512 x 16 bits,
within a page, with cycle times as short as 19ns.
The V53C16256H is best suited for graphics, and
DSP applications.
Device Usage Chart
Operating
Temperature
Range
Package Outline
Access Time (ns)
Power
Temperature
Mark
K
T
30
35
40
45
50
60
Std.
0
C to 70
C
Blank
-40
C to +85
C
I
2
V53C16256H Rev. 2.3 June 1998
MOSEL VITELIC
V53C16256H
FAMILY
DEVICE
PKG
( t
RAC
)
SPEED
PWR.
V
5
3
C
2
5
6
30 (30 ns)
35 (35 ns)
40 (40 ns)
45 (45 ns)
50 (50 ns)
60 (60 ns)
TEMP.
BLANK (0
C to 70
C)
I (-40
C to +85
C)
BLANK (NORMAL)
16256H-01
K (SOJ)
T (TSOP-II)
H
16
Description
Pkg.
Pin Count
SOJ
K
40
TSOP-II
T
40/44L
40-Pin Plastic SOJ
PIN CONFIGURATION
Top View
40/44 Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
5
6
7
8
9
10
11
12
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16256H-02
39
40
38
37
36
35
34
33
32
31
30
29
13
14
15
16
17
18
19
20
28
27
26
25
24
23
22
21
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
5
6
7
8
9
10
Vcc
I/O1
I/O2
I/O3
I/O4
Vcc
I/O5
I/O6
I/O7
I/O8
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
1
2
3
4
16256H-03
43
44
42
41
40
39
38
37
36
35
13
14
15
16
17
18
19
20
21
22
32
31
30
29
28
27
26
25
24
23
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Pin Names
A
0
A
8
Address Inputs
RAS
Row Address Strobe
UCAS
Column Address Strobe Upper Byte Control
LCAS
Column Address Strobe Lower Byte Control
WE
Write Enable
OE
Output Enable
I/O
1
I/O
16
Data Input, Output
V
CC
+5V Supply
V
SS
0V Supply
NC
No Connect
3
MOSEL VITELIC
V53C16256H
V53C16256H Rev. 2.3 June 1998
Absolute Maximum Ratings*
Ambient Temperature
Under Bias ................................ 10
C to +80
C
Storage Temperature (plastic) ..... 55
C to +125
C
Voltage Relative to V
SS
..................1.0 V to +7.0V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
*Note:
Operation above Absolute Maximum Ratings can
adversely affect device reliability.
Capacitance*
T
A
= 25
C, V
CC
= 5V
10%, V
SS
= 0 V
* Note:
Capacitance is sampled and not 100% tested
Symbol
Parameter Typ.
Max.
Unit
C
IN1
Address Input
3
4
pF
C
IN2
RAS, UCAS, LCAS,
WE, OE
4
5
pF
C
OUT
Data Input/Output
5
7
pF
Block Diagram
A 0
A 1
A7
A8
SENSE AMPLIFIERS
REFRESH
COUNTER
VCC
VSS
9
I/O 1
ADDRESS BUFFERS
AND PREDECODERS
X0 -X
ROW
DECODERS
512
MEMORY
ARRAY
COLUMN DECODERS
DATA I/O BUS
Y0 -Y 8
512 x 16
I/O
BUFFER
I/O2
I/O3
I/O4
OE CLOCK
GENERATOR
WE CLOCK
GENERATOR
CAS CLOCK
GENERATOR
RAS CLOCK
GENERATOR
OE
WE
LCAS
RAS
8
I/O 5
I/O6
I/O7
I/O8
I/O 9
I/O10
I/O11
I/O12
I/O 13
I/O14
I/O15
I/O16
UCAS
256K x 16
16256H-04
4
V53C16256H Rev. 2.3 June 1998
MOSEL VITELIC
V53C16256H
DC and Operating Characteristics
(1-2)
T
A
= 0
C to 70
C, V
CC
= 5V
5%, V
SS
= 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C16256H
Unit
Test Conditions
Notes
Min.
Typ.
Max.
I
LI
Input Leakage Current
(any input pin)
10
10
m
A
V
SS
V
IN
V
CC
I
LO
Output Leakage Current
(for High-Z State)
10
10
m
A
V
SS
V
OUT
V
CC
RAS, CAS at V
IH
I
CC1
V
CC
Supply Current,
Operating
30
200
mA
t
RC
= t
RC
(min.)
1, 2
35
190
40
180
45
170
50
160
60
150
I
CC2
V
CC
Supply Current,
TTL Standby
2
mA
RAS, CAS at V
IH
other inputs
V
SS
I
CC3
V
CC
Supply Current,
RAS-Only Refresh
30
200
mA
t
RC
= t
RC
(min.)
2
35
190
40
180
45
170
50
160
60
150
I
CC4
V
CC
Supply Current,
Fast Page Mode Operation
30
190
mA
Minimum Cycle
1, 2
35
180
40
170
45
160
50
150
60
140
I
CC5
V
CC
Supply Current,
Standby, Output Enabled
other inputs
V
SS
2
mA
RAS = V
IH
, CAS = V
IL
1
I
CC6
V
CC
Supply Current,
CMOS Standby
1
mA
RAS
V
CC
0.2 V,
CAS
V
CC
0.2 V,
All other inputs
V
SS
V
IL
Input Low Voltage
1
0.8
V
3
V
IH
Input High Voltage
2.0
V
CC
+ 1
V
3
V
OL
Output Low Voltage
0.4
V
I
OL
= 2.0 mA
V
OH
Output High Voltage
2.4
V
I
OH
= 2.0 mA
5
MOSEL VITELIC
V53C16256H
V53C16256H Rev. 2.3 June 1998
AC Characteristics
Over all temperature range, V
CC
= 5 V
10%, V
SS
= 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V
#
JEDEC
Symbol
Symbol Parameter
30
35
40
45
50
60
Unit Notes
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1
t
RL1RH1
t
RAS
RAS Pulse Width
30
75K
35
75K
40
75
45
75K
50
75K
60
75K
ns
2
t
RL2RL2
t
RC
Read or Write Cycle
Time
65
70
75
80
90
110
ns
3
t
RH2RL2
t
RP
RAS Precharge
Time
25
25
25
25
30
40
ns
4
t
RL1CH1
t
CSH
CAS Hold Time
30
35
40
45
50
60
ns
5
t
CL1CH1
t
CAS
CAS Pulse Width
5
6
12
13
14
15
ns
6
t
RL1CL1
t
RCD
RAS to CAS Delay
15
20
16
24
17
28
18
32
19
36
20
45
ns
7
t
WH2CL2
t
RCS
Read Command
Setup Time
0
0
0
0
0
0
ns
4
8
t
AVRL2
t
ASR
Row Address
Setup Time
0
0
0
0
0
0
ns
9
t
RL1AX
t
RAH
Row Address Hold
Time
5
6
7
8
9
10
ns
10
t
AVCL2
t
ASC
Column Address
Setup Time
0
0
0
0
0
0
ns
11
t
CL1AX
t
CAH
Column Address
Hold Time
5
5
5
6
7
10
ns
12
t
CL1RH1(R)
t
RSH (R)
RAS Hold Time
(Read Cycle)
10
10
12
13
14
15
ns
13
t
CH2RL2
t
CRP
CAS to RAS
Precharge Time
5
5
5
5
5
5
ns
14
t
CH2WX
t
RCH
Read Command
Hold Time
Referenced to CAS
0 0 0 0
0
0
ns
5
15
t
RH2WX
t
RRH
Read Command
Hold Time
Referenced to RAS
0 0 0 0
0
0
ns
5
16
t
OEL1RH2
t
ROH
RAS Hold Time
Referenced to OE
6
7
8
9
10
10
ns
17
t
GL1QV
t
OAC
Access Time from
OE
10
11
12
13
14
15
ns
18
t
CL1QV
t
CAC
Access Time from
CAS
10
11
12
13
14
15
ns
6, 7
19
t
RL1QV
t
RAC
Access Time from
RAS
30
35
45
50
55
60
ns
6, 8, 9
20
t
AVQV
t
CAA
Access Time from
Column Address
16
18
20
22
24
30
ns
6, 7,
10
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