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Data Sheet

C-3e NETWORK PROCESSOR

SILICON REVISION A1

C3ENPA1-DS/D
Rev 03 PRELIMINARY

Data Sheet

C-3e Network Processor
Silicon Revision A1

C3ENPA1-DS/D

Rev 03

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Copyright � 2002 Motorola, Inc. All rights reserved. No part of this documentation may
be reproduced in any form or by any means or used to make any derivative work (such as
translation, transformation, or adaptation) without written permission from Motorola.

Motorola reserves the right to revise this documentation and to make changes in content
from time to time without obligation on the part of Motorola to provide notification of
such revision or change.

Motorola provides this documentation without warranty, term, or condition of any kind,
either implied or expressed, including, but not limited to, the implied warranties, terms or
conditions of merchantability, satisfactory quality, and fitness for a particular purpose.
Motorola may make improvements or changes in the product(s) and/or the program(s)
described in this documentation at any time.

C-5e, C-3e, C-5, Q-5, Q-3, C-Port, and C-Ware are all trademarks of C-Port, a Motorola
Company. Motorola and the stylized Motorola logo are registered in the US Patent &
Trademark Office. All other product or service names are the property of their respective
owners.

MOTOROLA GENERAL BUSINESS INFORMATION

C3ENPA1-DS/D REV 03

C3ENPA1-DS/D

Rev 03

CONTENTS

About This Guide

Guide Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

13

Data Sheet Classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

Using PDF Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

14

Guide Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

16

Related Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17

C

HAPTER

1

Functional Description

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

Massive Processing Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

High Functional Integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

19

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

20

Channel Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

22

Executive Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

System Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

23

Fabric Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

Buffer Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

24

Table Lookup Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

25

Queue Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

26

C

HAPTER

2

Signal Descriptions

Signal Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

27

Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

28

Pin Descriptions Grouped by Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30

LVTTL and LVPECL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

30

Clock Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

CP Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

31

DS1/T1 Framer Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

34

10/100 Ethernet (RMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

35

Gigabit Ethernet (GMII) Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

36

Document Outline

• Data Sheet
• NOTE: This is a Preliminary version and is subject to change.
• Data Sheet
• Contents
• NOTE: All Contents listings are hyperlinks.
• List of Figures
• List of Tables
• About This Guide
  • Guide Overview
  • Data Sheet Classifications
  • Using PDF Documents
  • Guide Conventions
  • Revision History
  • Related Product Documentation
• NOTE: Throughout this book, all blue text is a hyperlink.
• Functional Description
  • Features
    • Massive Processing Power
    • High Functional Integration
  • Block Diagram
  • Channel Processors
  • Executive Processor
    • System Interfaces
  • Fabric Processor
  • Buffer Management Unit
  • Table Lookup Unit
  • Queue Management Unit
• Signal Descriptions
  • Signal Summary
  • Pinout Diagram
  • NOTE: To view individual pin names in Figure2 or Figure3, increase the zoom size to 200% or higher.
  • Pin Descriptions Grouped by Function
    • LVTTL and LVPECL Specifications
    • Clock Signals
    • CP Interface Signals
      • DS1/T1 Framer Interface Configuration
      • 10/100 Ethernet (RMII) Configuration
      • Gigabit Ethernet (GMII) Configuration
      • Gigabit Ethernet and Fibre Channel TBI Configuration
      • SONET OC-3 Transceiver Interface Configuration
      • SONET OC-12 Transceiver Interface Configuration
    • Executive Processor System Interface Signals
      • PCI Signals
      • Serial Interface Signals
      • PROM Interface Signals
      • General System Interface Signal
    • Fabric Processor Interface Signals
    • BMU SDRAM Interface Signals
    • TLU SRAM Interface Signals
    • QMU SRAM (Internal Mode) Interface Signals
    • QMU to Q-5/Q-3 (External Mode) Interface Signals
    • Power Supply Signals
    • Test Signals
  • Signals Grouped by Pin Number
  • JTAG Support
    • Pinout
    • JTAG Data Registers
    • Boundary Scan Restriction
    • Boundary Scan Cell Types
    • IDcode Register
    • JTAG Instruction Register
    • Boundary Scan Description Language
• Electrical Specifications
  • Absolute Maximum Ratings
  • Recommended Operating Conditions
  • DC Characteristics
  • Power Sequencing
  • Power and Thermal Characteristics
    • Thermal Management Information
      • Internal Package Conduction Resistance
      • Heat Sink Selection Example
  • AC Timing Specifications
    • Clock Timing Specifications
    • CP Timing Specifications
      • DS1/DS3 Timing Specifications
      • 10/100 Ethernet Timing Specifications
      • Gigabit GMII Ethernet, TBI and MII Interface Timing Specifications
      • OC-3 Timing Specifications
      • OC-12 Timing Specifications
    • Executive Processor Timing Specifications
      • PCI Timing Specifications
      • MDIO Serial Interface Timing Specifications
      • Low Speed Serial Interface Timing Specifications
      • PROM Interface Timing Specifications
    • Fabric Processor Timing Specifications
    • BMU Timing Specifications
    • TLU Timing Specifications
    • QMU SRAM (Internal Mode) Timing Specifications
    • QMU to Q-5/Q-3 (External Mode) Timing Specifications
• Mechanical Specifications
  • Package Views
  • Package Measurements
  • Marking Codes
  • Reflow
• Index
• NOTE: All page numbers are hyperlinks.