DSP56F807/D

Rev. 12.0, 02/2004

56F807

Technical Data

56F807 16-bit Hybrid Processor

Up to 40 MIPS at 80MHz core frequency

DSP and MCU functionality in a unified,
C-efficient architecture

Hardware DO and REP loops

MCU-friendly instruction set supports both
DSP and controller functions: MAC, bit
manipulation unit, 14 addressing modes

60K

16-bit words Program Flash

16-bit words Program RAM

16-bit words Data Flash

16-bit words Data RAM

16-bit words Boot Flash

Up to 64K

16- bit words each of external

Program and Data memory

Two 6 channel PWM Modules

Four 4 channel, 12-bit ADCs

Two Quadrature Decoders

CAN 2.0 B Module

Two Serial Communication Interfaces (SCIs)

Serial Peripheral Interface (SPI)

Up to four General Purpose Quad Timers

JTAG/OnCE

port for debugging

14 Dedicated and 18 Shared GPIO lines

160-pin LQFP or 160 MAPBGA Packages

Figure 1. 56F807 Block Diagram

JTAG/
OnCE

Port

Digital Reg

Analog Reg

Low Voltage

Supervisor

Program Controller

and

Hardware Looping Unit

Data ALU

16 x 16 + 36

36-Bit MAC

Three 16-bit Input Registers

Two 36-bit Accumulators

Address

Generation

Unit

Bit

Manipulation

Unit

PLL

Clock Gen

16-Bit
56800

Core

PAB

PDB

XDB2

CGDB

XAB1

XAB2

XTAL

EXTAL

INTERRUPT

CONTROLS

IPBB

CONTROLS

IPBus Bridge

(IPBB)

MODULE CONTROLS

ADDRESS BUS [8:0]

DATA BUS [15:0]

COP RESET

RESET

IRQA

IRQB

Applica-

tion-Specific

Memory &

Peripherals

Interrupt

Controller

Program Memory
61440 x 16 Flash

2048 x 16 SRAM

Boot Flash

2048 x 16 Flash

Data Memory

8192 x 16 Flash

4096 x 16 SRAM

COP/

Watchdog

SPI

GPIO

SCI0

GPIO

Quad Timer D

/ Alt Func

Quad Timer C

A/D1
A/D2

ADCA

PWM Outputs

Fault Inputs

PWMA

VCAPC

DDA

SSA

10*

· ·

EXTBOOT

Current Sense Inputs

Quadrature

Decoder 0

/Quad Timer

CAN 2.0A/B

CLKO

External

Address Bus

Switch

Bus

Control

External

Data Bus

Switch

External

Bus

Interface

Unit

RD Enable

WR Enable

DS Select

PS Select

A[00:05]

D[00:15]

A[06:15] or
GPIO-E2:E3 &
GPIO-A0:A7

PWM Outputs

Fault Inputs

PWMB

Current Sense Inputs

Quadrature

Decoder 1

/Quad Timer B

SCI1

GPIO

Dedicated

GPIO

VPP

RSTO

A/D1
A/D2

ADCB

VREF2

VREF

includes TCS pin which is reserved for factory use and is tied to

VSS

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56F807 Technical Data

Part 1 Overview

1.1 56F807 Features

1.1.1

Digital Signal Processing Core

Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture

As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency

Single-cycle 16

16-bit parallel Multiplier-Accumulator (MAC)

Two 36-bit accumulators including extension bits

16-bit bidirectional barrel shifter

Parallel instruction set with unique DSP addressing modes

Hardware DO and REP loops

Three internal address buses and one external address bus

Four internal data buses and one external data bus

Instruction set supports both DSP and controller functions

Controller style addressing modes and instructions for compact code

Efficient C compiler and local variable support

Software subroutine and interrupt stack with depth limited only by memory

JTAG/OnCE debug programming interface

1.1.2

Memory

Harvard architecture permits as many as three simultaneous accesses to Program and Data memory

On-chip memory including a low-cost, high-volume Flash solution

-- 60K

16-bit words of Program Flash

-- 2K

16-bit words of Program RAM

-- 8K

16-bit words of Data Flash

-- 4K

16-bit words of Data RAM

-- 2K

16-bit words of Boot Flash

Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states

-- As much as 64K

16 bits of Data memory

-- As much as 64K

16 bits of Program memory

1.1.3

Peripheral Circuits for 56F807

Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
four Fault inputs, fault tolerant design with dead time insertion, supports both center- and
edge-aligned modes

Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized

Two Quadrature Decoders each with four inputs or two additional Quad Timers

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56F807 Description

56F807 Technical Data

Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D
with four pins

CAN 2.0 B Module with 2-pin port for transmit and receive

Two Serial Communication Interfaces each with two pins (or four additional GPIO lines)

Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines)

Computer-Operating Properly (COP) Watchdog timer

Two dedicated external interrupt pins

14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins

External reset input pin for hardware reset

External reset output pin for system reset

JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging

Software-programmable, Phase Locked Loop-based frequency synthesizer for the hybrid controller
core clock

1.1.4

Energy Information

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

Uses a single 3.3V power supply

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

1.2 56F807 Description

The 56F807 is a member of the 56800 core-based family of hybrid controllers. It combines, on a single chip,
the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals
to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact
program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals that
are especially useful for applications such as motion control, smart appliances, steppers, encoders,
tachometers, limit switches, power supply and control, automotive control, engine management, noise
suppression, remote utility metering, industrial control for power, lighting, and automation.

The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in
parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and
optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The
instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized
control applications.

The 56F807 supports program execution from either internal or external memories. Two data operands can
be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external
dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral
configuration.

The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each
programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It
also supports program execution from external memory.

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56F807 Technical Data

A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable
software routines that can be used to program the main Program and Data Flash memory areas. Both
Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words.
The Boot Flash memory can also be either bulk or page erased.

A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM)
modules. These modules each incorporate three complementary, individually programmable PWM signal
outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM
outputs) to enhance motor control functionality. Complementary operation permits programmable dead
time insertion, distortion correction via current sensing by software, and separate top and bottom output
polarity control. The up-counter value is programmable to support a continuously variable PWM frequency.
Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The
device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC
(Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper
motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output
drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature
for key parameters is also included. A patented PWM waveform distortion correction circuit is also
provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be
programmable from 1 to 16. The PWM modules provide a reference output to synchronize the
analog-to-digital converters.

The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the
two-phase inputs, permitting generation of a number proportional to actual position. Speed computation
capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the
Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected.
Each input is filtered to ensure only true transitions are recorded.

This controller also provides a full set of standard programmable peripherals that include two Serial
Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of
these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A
Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and
14 dedicated GPIO lines are also included on the 56F807.

1.3 State of the Art Development Environment

Processor Expert

(PE) provides a Rapid Application Design (RAD) tool that combines

easy-to-use component-based software application creation with an expert knowledge system.

The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation,
compiling, and debugging. A complete set of evaluation modules (EVMs) and development system
cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a
complete, scalable tools solution for easy, fast, and efficient development.

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Product Documentation

56F807 Technical Data

1.4 Product Documentation

The four documents listed in

Table 1

are required for a complete description and proper design with the 56F807.

Documentation is available from local Motorola distributors, Motorola semiconductor sales offices, Motorola
Literature Distribution Centers, or online at http://www.motorola.com/semiconductors.

Table 1. 56F807 Chip Documentation

1.5 Data Sheet Conventions

This data sheet uses the following conventions:

Topic

Description

Order Number

DSP56800
Family Manual

Detailed description of the 56800 family architecture,
and 16-bit core processor and the instruction set

DSP56800FM/D

DSP56F801/803/805/807
User's Manual

Detailed description of memory, peripherals, and
interfaces of the 56F801, 56F803, 56F805, and
56F807

DSP56F801-7UM/D

56F807
Technical Data Sheet

Electrical and timing specifications, pin descriptions,
and package descriptions (this document)

DSP56F807/D

56F807
Product Brief

Summary description and block diagram of the 56F807
core, memory, peripherals and interfaces

DSP56F807PB/D

DSP56F807
Errata

Details any chip issues that might be present

DSP56F807E/D

OVERBAR

This is used to indicate a signal that is active when pulled low. For example, the RESET pin is
active when low.

"asserted"

A high true (active high) signal is high or a low true (active low) signal is low.

"deasserted"

A high true (active high) signal is low or a low true (active low) signal is high.

Examples:

Signal/Symbol

Logic State

Signal State

Voltage

Values for V

, V

, and V

are defined by individual product specifications.

True

Asserted

False

Deasserted

True

Asserted

False

Deasserted

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56F807 Technical Data

Part 2 Signal/Connection Descriptions

2.1 Introduction

The input and output signals of the 56F807 are organized into functional groups, as shown in

Table 2

and

as illustrated in

Figure 2

. In

Table 3

through

Table 19

, each table row describes the signal or signals

present on a pin.

Table 2. Functional Group Pin Allocations

Functional Group

Number of

Pins

Detailed

Description

Power (V

or V

DDA

)

Table 3

Ground (V

or V

SSA

)

Table 4

Supply Capacitors & V

Table 5

PLL and Clock

Table 6

Address Bus

Table 7

Data Bus

Table 8

Bus Control

Table 9

Interrupt and Program Control

Table 10

Dedicated General Purpose Input/Output

Table 11

Pulse Width Modulator (PWM) Ports

Table 12

Serial Peripheral Interface (SPI) Port

Alternately, GPIO pins

Table 13

Quadrature Decoder Ports

Alternately, Quad Timer pins

Table 14

Serial Communications Interface (SCI) Ports

Table 15

CAN Port

Table 16

Analog to Digital Converter (ADC) Ports

Table 17

Quad Timer Module Ports

Table 18

JTAG/On-Chip Emulation (OnCE)

Table 19

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Introduction

56F807 Technical Data

Figure 2. 56F807 Signals Identified by Functional Group

1. Alternate pin functionality is shown in parenthesis.

56F807

Power Port

Ground Port

Power Port

Ground Port

PLL

and

Clock

External

Address Bus or

GPIO

External

Data Bus

External

Bus Control

Dedicated
GPIO

SCI0 Port
or GPIO

SCI1 Port
or GPI0

DDA

SSA

VCAPC

EXTAL

XTAL

CLKO

A0-A5

A6-7 (GPIOE2-E3)

A8-15 (GPIOA0-A7)

D0D15

PHASEA0 (TA0)

PHASEB0 (TA1)

INDEX0 (TA2)

HOME0 (TA3)

PHASEA1 (TB0)

PHASEB1 (TB1)

INDEX1 (TB2)

HOME1 (TB3)

TCK

TMS

TDI

TDO

TRST

Quadrature

Decoder or

Quad Timer A

JTAG/OnCE

Port

GPIOB07

GPIOD05

PWMA0-5

ISA0-2

FAULTA0-3

PWMB0-5

ISB0-2

FAULTB0-3

SCLK (GPIOE4)

MOSI (GPIOE5)

MISO (GPIOE6)

SS (GPIOE7)

TXD0 (GPIOE0)

RXD0 (GPIOE1)

TXD1 (GPIOD6)

RXD1 (GPIOD7)

ANA0-7

VREF

ANB0-7

MSCAN_RX

MSCAN_TX

TC0-1

TD0-3

IRQA

IRQB

RESET

RSTO

EXTBOOT

PWMB
Port

Quad
Timers
C & D

ADCA
Port

ADCB
Port

Other

Supply

Ports

10*

Interrupt/
Program
Control

Quadrature

Decoder1 or

Quad Timer B

PWMA
Port

SPI Port
or GPIO

CAN

includes TCS pin which is reserved for factory use and is tied to

VSS

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56F807 Technical Data

2.2 Power and Ground Signals

2.3 Clock and Phase Locked Loop Signals

Table 3. Power Inputs

No. of Pins

Signal Name

Signal Description

Power--These pins provide power to the internal structures of the chip, and
should all be attached to V

DD.

DDA

Analog Power--These pins is a dedicated power pin for the analog portion
of the chip and should be connected to a low noise 3.3V supply.

Table 4. Grounds

No. of Pins

Signal Name

Signal Description

GND--These pins provide grounding for the internal structures of the chip and
should all be attached to V

SS.

SSA

Analog Ground--This pin supplies an analog ground.

TCS

TCS--This Schmitt pin is reserved for factory use and must be tied to V

for

normal use. In block diagrams, this pin is considered an additional V

SS.

Table 5. Supply Capacitors and VPP

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

VCAPC Supply

Supply

VCAPC--Connect each pin to a 2.2uF or greater bypass
capacitor in order to bypass the core logic voltage regulator
(required for proper chip operation). For more information, please
refer to

Section 5.2

VPP

Input

VPP--This pin should be left unconnected as an open circuit for
normal functionality.

Table 6. PLL and Clock

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

EXTAL

Input

External Crystal Oscillator Input--This input should be
connected to an 8MHz external crystal or ceramic resonator.
For more information, please refer to

Section 3.5

XTAL

Input/

Output

Chip-driven

Crystal Oscillator Output--This output should be connected
to an 8MHz external crystal or ceramic resonator. For more
information, please refer to

Section 3.5

This pin can also be connected to an external clock source. For
more information, please refer to

Section 3.5.2

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Address, Data, and Bus Control Signals

56F807 Technical Data

2.4 Address, Data, and Bus Control Signals

CLKO

Output

Chip-driven

Clock Output--This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device's master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.

Table 7. Address Bus Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

A0A5

Output

Tri-stated

Address Bus--A0A5 specify the address for external
Program or Data memory accesses.

A6A7

GPIOE2-

GPIOE3

Output

Input/O

utput

Tri-stated

Input

Address Bus--A6A7 specify the address for external
Program or Data memory accesses.

Port E GPIO--These two General Purpose I/O (GPIO) pins
can individually be programmed as input or output pins.

After reset, the default state is Address Bus.

A8A15

GPIOA0-

GPIOA7

Output

Input/O

utput

Tri-stated

Input

Address Bus--A8A15 specify the address for external
Program or Data memory accesses.

Port A GPIO--These eight General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.

After reset, the default state is Address Bus.

Table 8. Data Bus Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

D0D15

Input/O

utput

Tri-stated

Data Bus-- D0D15 specify the data for external program or
data memory accesses. D0D15 are tri-stated when the external
bus is inactive. Internal pullups may be active.

Table 6. PLL and Clock (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

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56F807 Technical Data

2.5 Interrupt and Program Control Signals

Table 9. Bus Control Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

Output

Tri-stated

Program Memory Select--PS is asserted low for external program
memory access.

Output

Tri-stated

Data Memory Select--DS is asserted low for external data
memory access.

Output

Tri-stated

Write Enable--WR is asserted during external memory write
cycles. When WR is asserted low, pins D0D15 become outputs
and the device puts data on the bus. When WR is deasserted high,
the external data is latched inside the external device. When WR is
asserted, it qualifies the A0A15, PS, and DS pins. WR can be
connected directly to the WE pin of a Static RAM.

Output

Tri-stated

Read Enable--RD is asserted during external memory read cycles.
When RD is asserted low, pins D0D15 become inputs and an
external device is enabled onto the device's data bus. When RD is
deasserted high, the external data is latched inside the device.
When RD is asserted, it qualifies the A0A15, PS, and DS pins. RD
can be connected directly to the OE pin of a Static RAM or ROM.

Table 10. Interrupt and Program Control Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

IRQA

Input

(Schmitt)

Input

External Interrupt Request A--The IRQA input is a
synchronized external interrupt request that indicates that an
external device is requesting service. It can be programmed to
be level-sensitive or negative-edge-triggered.

IRQB

Input

(Schmitt)

Input

External Interrupt Request B--The IRQB input is an external
interrupt request that indicates that an external device is
requesting service. It can be programmed to be level-sensitive
or negative-edge-triggered.

RSTO

Output

Reset Output--This output reflects the internal reset state of
the chip.

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GPIO Signals

56F807 Technical Data

2.6 GPIO Signals

2.7 Pulse Width Modulator (PWM) Signals

RESET

Input

(Schmitt)

Input

Reset--This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and
placed in the Reset state. A Schmitt trigger input is used for
noise immunity. When the RESET pin is deasserted, the initial
chip operating mode is latched from the EXTBOOT pin. The
internal reset signal will be deasserted synchronous with the
internal clocks, after a fixed number of internal clocks.

To ensure complete hardware reset, RESET and TRST should
be asserted together. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG
module. In this case, assert RESET, but do not assert TRST.

EXTBOOT

Input

(Schmitt)

Input

External Boot--This input is tied to V

to force device to boot

from off-chip memory. Otherwise, it is tied to VSS.

Table 11. Dedicated General Purpose Input/Output (GPIO) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

GPIOB0-G

PIOB7

Input

Output

Input

Port B GPIO--These eight pins are dedicated General
Purpose I/O (GPIO) pins that can individually be programmed
as input or output pins.

After reset, the default state is GPIO input.

GPIOD0-G

PIOD5

Input

Output

Input

Port D GPIO--These six pins are dedicated GPIO pins that
can individually be programmed as an input or output pins.

After reset, the default state is GPIO input.

Table 12. Pulse Width Modulator (PWMA and PWMB) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

PWMA0-5

Output

Tri- stated

PWMA0-5-- Six PWMA output pins.

ISA0-2

Input

(Schmitt)

Input

ISA0-2-- These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.

FAULTA0-3

Input

(Schmitt)

Input

FAULTA0-3-- These Fault input pins are used for disabling
selected PWMA outputs in cases where fault conditions
originate off-chip.

PWMB0-5

Output

Tri- stated

PWMB0-5-- Six PWMB output pins.

Table 10. Interrupt and Program Control Signals (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

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56F807 Technical Data

2.8 Serial Peripheral Interface (SPI) Signals

ISB0-2

Input

(Schmitt)

Input

ISB0-2-- These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMB.

FAULTB0-3

Input

(Schmitt)

Input

FAULTB0-3-- These four Fault input pins are used for
disabling selected PWMB outputs in cases where fault
conditions originate off-chip.

Table 13. Serial Peripheral Interface (SPI) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

MISO

GPIOE6

Input/

Output

Input/Outp

Input

SPI Master In/Slave Out (MISO)--This serial data pin is an
input to a master device and an output from a slave device. The
MISO line of a slave device is placed in the high-impedance
state if the slave device is not selected.

Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

After reset, the default state is MISO.

MOSI

GPIOE5

Input/

Output

Input/Outp

Input

SPI Master Out/Slave In (MOSI)--This serial data pin is an
output from a master device and an input to a slave device. The
master device places data on the MOSI line a half-cycle before
the clock edge that the slave device uses to latch the data.

Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

After reset, the default state is MOSI.

SCLK

GPIOE4

Input/Outp

Input

SPI Serial Clock--In master mode, this pin serves as an
output, clocking slaved listeners. In slave mode, this pin serves
as the data clock input.

Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

After reset, the default state is SCLK.

GPIOE7

Input

Input/Outp

Input

SPI Slave Select--In master mode, this pin is used to arbitrate
multiple masters. In slave mode, this pin is used to select the
slave.

Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.

After reset, the default state is SS.

Table 12. Pulse Width Modulator (PWMA and PWMB) Signals (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

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Quadrature Decoder Signals

56F807 Technical Data

2.9 Quadrature Decoder Signals

2.10 Serial Communications Interface (SCI) Signals

Table 14. Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

PHASEA0

TA0

Input

Input/Output

Input

Phase A--Quadrature Decoder #0 PHASEA input

TA0--Timer A Channel 0

PHASEB0

TA1

Input

Input/Output

Input

Phase B--Quadrature Decoder #0 PHASEB input

TA1--Timer A Channel 1

INDEX0

TA2

Input

Input/Output

Input

Index--Quadrature Decoder #0 INDEX input

TA2--Timer A Channel 2

HOME0

TA3

Input

Input/Output

Input

Home--Quadrature Decoder #0 HOME input

TA3--Timer A Channel 3

PHASEA1

TB0

Input

Input/Output

Input

Phase A--Quadrature Decoder #1 PHASEA input

TB0--Timer B Channel 0

PHASEB1

TB1

Input

Input/Output

Input

Phase B--Quadrature Decoder #1 PHASEB input

TB1--Timer B Channel 1

INDEX1

TB2

Input

Input/Output

Input

Index--Quadrature Decoder #1 INDEX input

TB2--Timer B Channel 2

HOME1

TB3

Input

Input/Output

Input

Home--Quadrature Decoder #1 HOME input

TB3--Timer B Channel 3

Table 15. Serial Communications Interface (SCI0 and SCI1) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TXD0

GPIOE0

Output

Input/Outp

Input

Transmit Data (TXD0)--transmit data output

Port E GPIO--This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.

After reset, the default state is SCI output.

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56F807 Technical Data

2.11 CAN Signals

2.12 Analog-to-Digital Converter (ADC) Signals

RXD0

GPIOE1

Input

Input/Outp

Input

Receive Data (RXD0)-- receive data input

Port E GPIO--This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.

After reset, the default state is SCI input.

TXD1

GPIOD6

Output

Input/Outp

Input

Transmit Data (TXD1)--transmit data output

Port D GPIO--This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.

After reset, the default state is SCI output.

RXD1

GPIOD7

Input

Input/Outp

Input

Receive Data (RXD1)-- receive data input

Port D GPIO--This pin is a General Purpose I/O (GPIO) pin
that can individually be programmed as input or output pin.

After reset, the default state is SCI input.

Table 16. CAN Module Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

MSCAN_ RX

Input

(Schmitt)

Input

MSCAN Receive Data--MSCAN input. This pin has
an internal pull-up resistor.

MSCAN_ TX

Output

MSCAN Transmit Data--MSCAN output. CAN output
is open-drain output and pull-up resistor is needed.

Table 17. Analog to Digital Converter Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

ANA0-3

Input

ANA0-3--Analog inputs to ADCA channel 1

ANA4-7

Input

ANA4-7--Analog inputs to ADCA channel 2

VREF

Input

VREF--Analog reference voltage for ADC. Must be set to
V

DDA

-0.3V for optimal performance.

ANB0-3

Input

ANB0-3--Analog inputs to ADCB, channel 1

ANB4-7

Input

ANB4-7--Analog inputs to ADCB, channel 2

Table 15. Serial Communications Interface (SCI0 and SCI1) Signals (Continued)

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

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Quad Timer Module Signals

56F807 Technical Data

2.13 Quad Timer Module Signals

2.14 JTAG/OnCE

Part 3 Specifications

3.1 General Characteristics

The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term
"5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to
withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices
designed for 3.3V and 5V power supplies. In such sytems, a bus may carry both 3.3V and 5V-compatible
I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V

10% during

normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings
of 3.3V I/O levels while being able to receive 5V levels without being damaged.

Table 18. Quad Timer Module Signals

No. of

Pins

Signal

Name

Signal Type

State During

Reset

Signal Description

TC0-1

Input/Output

Input

TC0-1--Timer C Channels 0 and 1

TD0-3

Input/Output

Input

TD0-3--Timer D Channels 0, 1, 2, and 3

Table 19. JTAG/On-Chip Emulation (OnCE) Signals

No. of

Pins

Signal

Name

Signal

Type

State During

Reset

Signal Description

TCK

Input

(Schmitt)

Input, pulled

low internally

Test Clock Input--This input pin provides a gated clock to
synchronize the test logic and shift serial data to the JTAG/OnCE
port. The pin is connected internally to a pull-down resistor.

TMS

Input

(Schmitt)

Input, pulled

high internally

Test Mode Select Input--This input pin is used to sequence the
JTAG TAP controller's state machine. It is sampled on the rising
edge of TCK and has an on-chip pull-up resistor.

TDI

Input

(Schmitt)

Input, pulled

high internally

Test Data Input--This input pin provides a serial input data
stream to the JTAG/OnCE port. It is sampled on the rising edge
of TCK and has an on-chip pull-up resistor.

TDO

Output

Tri-stated

Test Data Output--This tri-statable output pin provides a serial
output data stream from the JTAG/OnCE port. It is driven in the
Shift-IR and Shift-DR controller states, and changes on the falling
edge of TCK.

TRST

Input

(Schmitt)

Input, pulled

high internally

Test Reset--As an input, a low signal on this pin provides a
reset signal to the JTAG TAP controller. To ensure complete
hardware reset, TRST should be asserted at power-up and
whenever RESET is asserted. The only exception occurs in a
debugging environment when a hardware device reset is
required and it is necessary not to reset the OnCE/JTAG module.
In this case, assert RESET, but do not assert TRST.

Output

Debug Event--DE provides a low pulse on recognized debug
events.

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56F807 Technical Data

Absolute maximum ratings given in

Table 20

are stress ratings only, and functional operation at the

maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.

The 56F807 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after complete characterization and device qualifications have been
completed.

CAUTION

This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields. However,
normal precautions are advised to avoid application of any
voltages higher than maximum rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if
unused inputs are tied to an appropriate voltage level.

Table 20. Absolute Maximum Ratings

Characteristic

Symbol

Min

Max

Unit

Supply voltage

0.3

+ 4.0

All other input voltages, excluding Analog inputs

0.3

+ 5.5V

Analog inputs, ANA0-7 and VREF

SSA

0.3

DDA

+ 0.3

Analog inputs EXTAL and XTAL

SSA

0.3

SSA

+ 3.0

Current drain per pin excluding V

, V

, PWM

outputs, TCS, VPP, V

DDA

, V

SSA

Table 21. Recommended Operating Conditions

Characteristic

Symbol

Min

Typ

Max

Unit

Supply voltage, digital

3.0

3.3

3.6

Supply Voltage, analog

DDA

3.0

3.3

3.6

ADC reference voltage

VREF

2.7

DDA

Ambient operating temperature

°C

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General Characteristics

56F807 Technical Data

Notes:

Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application.
Determined on 2s2p thermal test board.

Junction to ambient thermal resistance, Theta-JA (

) was simulated to be equivalent to the

JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was
also simulated on a thermal test board with two internal planes (2s2p where "s" is the number of
signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for
Theta-JA for forced convection or with the non-single layer boards is Theta-JMA.

Junction to case thermal resistance, Theta-JC (R

), was simulated to be equivalent to the measured

values using the cold plate technique with the cold plate temperature used as the "case" temperature.
The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This
is the correct thermal metric to use to calculate thermal performance when the package is being used
with a heat sink.

Thermal Characterization Parameter, Psi-JT (

), is the "resistance" from junction to reference

point thermocouple on top center of case as defined in JESD51-2.

is a useful value to use to

estimate junction temperature in steady state customer environments.

Junction temperature is a function of on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, ambient temperature, air flow, power dissipation of other
components on the board, and board thermal resistance.

See Section 5.1 from more details on thermal design considerations.

Table 22. Thermal Characteristics

Characteristic

Comments

Symbol

Value

Unit

Notes

160-pin

LQFP

160

MBGA

Junction to ambient
Natural convection

38.5

63.4

°C/W

Junction to ambient (@1m/sec)

JMA

35.4

60.3

°C/W

Junction to ambient
Natural convection

Four layer
board (2s2p)

JMA

(2s2p)

49.9

°C/W

1,2

Junction to ambient (@1m/sec)

Four layer
board (2s2p)

JMA

31.5

46.8

°C/W

1,2

Junction to case

8.6

8.1

°C/W

Junction to center of case

0.8

0.6

°C/W

4, 5

I/O pin power dissipation

I/O

User Determined

Power dissipation

= (I

x V

+ P

I/O

)

Junction to center of case

DMAX

(TJ - TA) /

°C

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56F807 Technical Data

3.2 DC Electrical Characteristics

Table 23. DC Electrical Characteristics

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

Input high voltage (XTAL/EXTAL)

IHC

2.25

2.75

Input low voltage (XTAL/EXTAL)

ILC

0.5

Input high voltage (Schmitt trigger inputs)

IHS

2.2

5.5

Input low voltage (Schmitt trigger inputs)

ILS

-0.3

0.8

Input high voltage (all other digital inputs)

2.0

5.5

Input low voltage (all other digital inputs)

-0.3

0.8

Input current high (pullup/pulldown resistors disabled,
V

)

-1

Input current low (pullup/pulldown resistors disabled,
V

)

-1

Input current high (with pullup resistor, V

)

IHPU

-1

Input current low (with pullup resistor, V

)

ILPU

-210

-50

Input current high (with pulldown resistor, V

)

IHPD

180

Input current low (with pulldown resistor, V

)

ILPD

-1

Nominal pullup or pulldown resistor value

, R

Output tri-state current low

OZL

-10

Output tri-state current high

OZH

-10

Input current high (analog inputs, V

DDA

)

IHA

-15

Input current low (analog inputs, V

SSA

)

ILA

-15

Output High Voltage (at IOH)

0.7

Output Low Voltage (at IOL)

0.4

Output source current

PWM pin output source current

OHP

PWM pin output sink current

OLP

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DC Electrical Characteristics

56F807 Technical Data

Input capacitance

Output capacitance

OUT

supply current

DDT

Run

195

220

Wait

170

200

Stop

115

145

Low Voltage Interrupt, external power supply

EIO

2.4

2.7

3.0

Low Voltage Interrupt, internal power supply

EIC

2.0

2.2

2.4

Power on Reset

POR

1.7

2.0

Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3,

TCK, TRST, TMS, TDI, and MSCAN_RX

Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling.

PWM pin output source current measured with 50% duty cycle.

PWM pin output sink current measured with 50% duty cycle.

DDT

= I

+ I

DDA

(Total supply current for V

+ V

DDA

)

Run (operating) I

measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports

configured as inputs; measured with all modules enabled.

Wait I

measured using external square wave clock source (f

osc

= 8MHz) into XTAL; all inputs 0.2V from rail; no

DC loads; less than 50pF on all outputs. C

= 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly

affects wait I

; measured with PLL enabled.

This low voltage interrupt monitors the V

DDA

external power supply. V

DDA

is generally connected to the same

potential as V

via separate traces. If V

DDA

drops below V

EIO

, an interrupt is generated. Functionality of the device is

guaranteed under transient conditions when V

DDA

EIO

(between the minimum specified V

and the point when the

EIO

interrupt is generated).

This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage

is regulator drops below V

EIC

, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt

will not be generated unless the external power supply drops below the minimum specified value (3.0V).

10. Power

on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power

is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up
rate is. The internally regulated voltage is typically 100mV less than V

during ramp-up until 2.5V is reached, at which

time it self-regulates.

Table 23. DC Electrical Characteristics (Continued)

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

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56F807 Technical Data

Figure 3. Maximum Run IDD vs. Frequency (see Note

Table 16

)

3.3 AC Electrical Characteristics

Timing waveforms in

Section 3.3

are tested using the V

and V

levels specified in the DC Characteristics

table. In

Figure 4

the levels of V

and V

for an input signal are shown.

Figure 4. Input Signal Measurement References

Figure 5

shows the definitions of the following signal states:

Active state, when a bus or signal is driven, and enters a low impedance state.

Tri-stated, when a bus or signal is placed in a high impedance state.

Data Valid state, when a signal level has reached V

or V

OH.

Data Invalid state, when a signal level is in transition between V

and V

OH.

100

200

250

Freq. (MHz)

IDD (mA)

150

IDD Digital

IDD Analog

IDD Total

Fall Time

Input Signal

Note: The midpoint is V

+ (V

)/2.

Midpoint1

Low

High

90%

50%

10%

Rise Time

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Flash Memory Characteristics

56F807 Technical Data

3.4 Flash Memory Characteristics

Figure 5. Signal States

Table 24. Flash Memory Truth Table

Mode

X address enable, all rows are disabled when XE=0

Y address enable, YMUX is disabled when YE=0

Sense amplifier enable

Output enable, tri-state Flash data out bus when OE=0

PROG

Defines program cycle

ERASE

Defines erase cycle

MAS1

Defines mass erase cycle, erase whole block

NVSTR

Defines non-volatile store cycle

Standby

Read

Word Program

Page Erase

Mass Erase

Table 25. IFREN Truth Table

Mode

IFREN=1

IFREN=0

Read

Read information block

Read main memory block

Word program

Program information block

Program main memory block

Page erase

Erase information block

Erase main memory block

Mass erase

Erase both block

Erase main memory block

Data Invalid State

Data1

Data2 Valid

Data

Tri-stated

Data3 Valid

Data2

Data3

Data1 Valid

Data Active

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56F807 Technical Data

Table 26. Flash Timing Parameters

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6V, T

= 40

to +85

C, C

50pF

Characteristic

Symbol

Min Typ

Max

Unit

Figure

Program time

prog*

Figure 6

Erase time

erase*

Figure 7

Mass erase time

me*

100

Figure 8

Endurance

One cycle is equal to an erase program and read.

CYC

10,000

20,000

cycles

Data Retention

@ 5000 cycles

RET

years

The following parameters should only be used in the Manual Word Programming Mode

PROG/ERASE to NVSTR set
up time

nvs*

Figure 6

Figure 7

Figure 8

NVSTR hold time

nvh*

Figure 6

Figure 7

NVSTR hold time (mass erase)

nvh1*

100

Figure 8

NVSTR to program set up time

pgs*

Figure 6

Recovery time

rcv*

Figure 6

Figure 7

Figure 8

Cumulative program

HV period

Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot

be programmed twice before next erase.

Figure 6

Program hold time

Parameters are guaranteed by design in smart programming mode and must be one cycle or greater.

*The Flash interface unit provides registers for the control of these parameters.

pgh

Figure 6

Address/data set up time

ads

Figure 6

Address/data hold time

adh

Figure 6

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External Clock Operation

56F807 Technical Data

3.5 External Clock Operation

The 56F807 system clock can be derived from an external crystal or an external system clock signal. To
generate a reference frequency using the internal oscillator, a reference crystal must be connected between
the EXTAL and XTAL pins.

3.5.1

Crystal Oscillator

The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the
frequency range specified for the external crystal in

Table 28

. In

Figure 9

a recommended crystal

oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, since
crystal parameters determine the component values required to provide maximum stability and reliable
start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and
XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator
circuitry is designed to have no external load capacitors present. As shown in

Figure 10

no external load

capacitors should be used.

The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a
capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and
process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF as
a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as
determined by the following equation:

This is the value load capacitance that should be used when selecting a crystal and determining the actual
frequency of operation of the crystal oscillator circuit.

Figure 9. Connecting to a Crystal Oscillator

3.5.2

Ceramic Resonator

It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system
design can tolerate the reduced signal integrity. In

Figure 10

, a typical ceramic resonator circuit is shown.

Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The
resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The
internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in

Figure 9

no external load capacitors should be used.

CL =

CL1 * CL2

CL1 + CL2

+ Cs =

+ 3 = 6 + 3 = 9pF

12 * 12

12 + 12

Recommended External Crystal
Parameters:
R

= 1 to 3 M

= 8MHz (optimized for 8MHz)

EXTAL XTAL

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56F807 Technical Data

Figure 10. Connecting a Ceramic Resonator

Note: Motorola recommends only two terminal ceramic resonators vs. three terminal
resonators (which contain an internal bypass capacitor to ground).

3.5.3

External Clock Source

The recommended method of connecting an external clock is given in

Figure 11

. The external clock

source is connected to XTAL and the EXTAL pin is grounded.

Figure 11. Connecting an External Clock Signal

Figure 12. External Clock Timing

Table 27. External Clock Operation Timing Requirements

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

Characteristic

Symbol

Min

Typ

Max

Unit

Frequency of operation (external clock driver)

See

Figure 11

for details on using the recommended connection of an external clock driver.

osc

MHz

Clock Pulse Width

The high or low pulse width must be no smaller than 6.25ns or the chip will not function.

Parameters listed are guaranteed by design.

6.25

Recommended Ceramic Resonator
Parameters:
R

= 1 to 3 M

= 8MHz (optimized for 8MHz)

EXTAL XTAL

56F807

XTAL

EXTAL

External

Clock

External

Clock

Note: The midpoint is V

+ (V

)/2.

90%

50%

10%

90%

50%

10%

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External Bus Asynchronous Timing

56F807 Technical Data

3.5.4

Phase Locked Loop Timing

3.6 External Bus Asynchronous Timing

Table 28. PLL Timing

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

Characteristic

Symbol

Min

Typ

Max

Unit

External reference crystal frequency for the PLL

An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work

correctly. The PLL is optimized for 8MHz input crystal.2.

osc

MHz

PLL output frequency

ZCLK may not exceed 80MHz. For additional information on ZCLK and

out

/2,

please refer to the OCCS chapter

in the User Manual. ZCLK = f

out

110

MHz

PLL stabilization time

to +85

This is the minimum time required after the PLL set-up is changed to ensure reliable operation.

plls

PLL stabilization time

-40

to 0

plls

100

200

Table 29. External Bus Asynchronous Timing

1,2

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

Address Valid to WR Asserted

AWR

6.5

WR Width Asserted
Wait states = 0
Wait states > 0

7.5

(T*WS)+7.5

--
--

ns
ns

WR Asserted to D0D15 Out Valid

WRD

T + 4.2

Data Out Hold Time from WR Deasserted

DOH

4.8

Data Out Set Up Time to WR Deasserted
Wait states = 0
Wait states > 0

DOS

2.2

(T*WS)+6.4

--
--

ns
ns

RD Deasserted to Address Not Valid

RDA

Address Valid to RD Deasserted
Wait states = 0
Wait states > 0

ARDD

18.7

(T*WS) + 18.7

ns
ns

Input Data Hold to RD Deasserted

DRD

RD Assertion Width
Wait states = 0
Wait states > 0

(T*WS)+19

--
--

ns
ns

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56F807 Technical Data

Address Valid to Input Data Valid
Wait states = 0
Wait states > 0

--
--

(T*WS)+1

ns
ns

Address Valid to RD Asserted

ARDA

-4.4

RD Asserted to Input Data Valid
Wait states = 0
Wait states > 0

RDD

--
--

2.4

(T*WS) + 2.4

ns
ns

WR Deasserted to RD Asserted

WRRD

6.8

RD Deasserted to RD Asserted

RDRD

WR Deasserted to WR Asserted

WRWR

14.1

RD Deasserted to WR Asserted

RDWR

12.8

Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and

T = Clock Period. For 80MHz operation, T = 12.5ns.

Parameters listed are guaranteed by design.

To calculate the required access time for an external memory for any frequency < 80MHz, use this formula:

Top = Clock period @ desired operating frequency

WS = Number of wait states

Memory Access Time = (Top*WS) + (Top- 11.5)

Figure 13. External Bus Asynchronous Timing

Table 29. External Bus Asynchronous Timing

1,2

(Continued)

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

A0A15,

PS, DS

(See Note)

D0D15

Note: During read-modify-write instructions and internal instructions, the address lines do not change state.

Data In

Data Out

AWR

ARDA

ARDD

RDA

RDRD

RDWR

WRWR

DOS

WRD

WRRD

DOH

DRD

RDD

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Reset, Stop, Wait, Mode Select, and Interrupt Timing

56F807 Technical Data

3.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing

Table 30. Reset, Stop, Wait, Mode Select, and Interrupt Timing

1,5

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF

In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

See

Figure

RESET Assertion to Address, Data and Control Signals
High Impedance

RAZ

Figure 14

Minimum RESET Assertion Duration

OMR Bit 6 = 0
OMR Bit 6 = 1

Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
· After power-on reset
· When recovering from Stop state

275,000T

128T

--
--

ns
ns

Figure 14

RESET Deassertion to First External Address Output

RDA

33T

34T

Figure 14

Edge-sensitive Interrupt Request Width

IRW

1.5T

Figure 15

IRQA, IRQB Assertion to External Data Memory Access
Out Valid, caused by first instruction execution in the
interrupt service routine

IDM

15T

Figure 16

IRQA, IRQB Assertion to General Purpose Output Valid,
caused by first instruction execution in the interrupt
service routine

16T

Figure 16

IRQA Low to First Valid Interrupt Vector Address Out

recovery from Wait State

The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state.

This is not the minimum required so that the IRQA interrupt is accepted.

IRI

13T

Figure 17

IRQA Width Assertion to Recover from Stop State

The interrupt instruction fetch is visible on the pins only in Mode 3.

Parameters listed are guaranteed by design.

Figure 18

Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

--
--

275,000T

12T

ns
ns

Figure 18

Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

IRQ

--
--

275,000T

12T

ns
ns

Figure 19

Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1

--
--

275,000T

12T

ns
ns

Figure 19

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56F807 Technical Data

Figure 14. Asynchronous Reset Timing

Figure 15. External Interrupt Timing (Negative-Edge-Sensitive)

Figure 16. External Level-Sensitive Interrupt Timing

Figure 17. Interrupt from Wait State Timing

First Fetch

RAZ

RDA

A0A15,

D0D15

PS, DS,

RD, WR

RESET

First Fetch

IRQA,
IRQB

IRW

IDM

A0A15,

IRQA

IRQB

First Interrupt Instruction Execution

a) First Interrupt Instruction Execution

General

Purpose

I/O Pin

IRQA

IRQB

b) General Purpose I/O

Instruction Fetch

IRI

IRQA,

IRQB

First Interrupt Vector

A0A15,

PS, DS,

RD, WR

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Serial Peripheral Interface (SPI) Timing

56F807 Technical Data

Figure 18. Recovery from Stop State Using Asynchronous Interrupt Timing

Figure 19. Recovery from Stop State Using IRQA Interrupt Service

Figure 20. Reset Output Timing

3.8 Serial Peripheral Interface (SPI) Timing

Table 31. SPI Timing

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Max

Unit

See Figure

Cycle time
Master
Slave

50
25

--
--

ns
ns

Figures

Enable lead time
Master
Slave

ELD

--
--

ns
ns

Figure

Enable lag time
Master
Slave

ELG

100

--
--

ns
ns

Figure

Not IRQA Interrupt Vector

IRQA

A0A15,

PS, DS,

RD, WR

First Instruction Fetch

Instruction Fetch

IRQ

IRQA

A0A15
PS, DS,

RD, WR

First IRQA Interrupt

RSTO

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56F807 Technical Data

Parameters listed are guaranteed by design.

Clock (SCK) high time
Master
Slave

17.6
12.5

--
--

ns
ns

Figures

Clock (SCK) low time
Master
Slave

24.1

--
--

ns
ns

Figure

Data set-up time required for inputs
Master
Slave

--
--

ns
ns

Figures

Data hold time required for inputs
Master
Slave

0
2

--
--

ns
ns

Figures

Access time (time to data active from
high-impedance state)
Slave

4.8

Figure

Disable time (hold time to high-impedance state)
Slave

3.7

15.2

Figure

Data Valid for outputs
Master
Slave (after enable edge)

--
--

4.5

20.4

ns
ns

Figures

Data invalid
Master
Slave

0
0

--
--

ns
ns

Figures

Rise time
Master
Slave

--
--

11.5
10.0

ns
ns

Figures

Fall time
Master
Slave

--
--

9.7
9.0

ns
ns

Figures

Table 31. SPI Timing

(Continued)

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

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Serial Peripheral Interface (SPI) Timing

56F807 Technical Data

Figure 21. SPI Master Timing (CPHA = 0)

Figure 22. SPI Master Timing (CPHA = 1)

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 141

LSB in

(ref)

Master MSB out

Bits 141

Master LSB out

(Input)

SS is held High on master

SCLK (CPOL = 0)

(Output)

SCLK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

MSB in

Bits 141

LSB in

(ref)

Master MSB out

Bits 14 1

Master LSB out

(Input)

SS is held High on master

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56F807 Technical Data

Figure 23. SPI Slave Timing (CPHA = 0)

Figure 24. SPI Slave Timing (CPHA = 1)

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 141

MSB in

Bits 141

LSB in

(Input)

ELG

ELD

Slave LSB out

SCLK (CPOL = 0)

(Input)

SCLK (CPOL = 1)

(Input)

MISO

(Output)

MOSI

(Input)

Slave MSB out

Bits 141

MSB in

Bits 141

LSB in

(Input)

Slave LSB out

ELD

ELG

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Quad Timer Timing

56F807 Technical Data

3.9 Quad Timer Timing

3.10 Quadrature Decoder Timing

Table 32. Timer Timing

1, 2

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Timer input period

4T + 6

Timer input high/low period

INHL

2T + 3

Timer output period

OUT

Timer output high/low period

OUTHL

Figure 25. Timer Timing

Table 33. Quadrature Decoder Timing

1, 2

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. V

= 0V, V

3.03.6V,
T

= 40

to +85

C, C

50pF.

Parameters listed are guaranteed by design.

Characteristic

Symbol

Min

Max

Unit

Quadrature input period

8T + 12

Quadrature input high/low period

4T + 6

Quadrature phase period

2T + 3

OUT

OUTHL

INHL

Timer Inputs

Timer Outputs

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56F807 Technical Data

3.11 Serial Communication Interface (SCI) Timing

Table 34. SCI Timing

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Figure 27. RXD Pulse Width

Figure 28. TXD Pulse Width

Figure 26. Quadrature Decoder Timing

Characteristic

Symbol

Min

Max

Unit

Baud Rate

MAX

is the frequency of operation of the system clock in MHz.

MAX

*2.5)/(80)

Mbps

RXD

Pulse Width

The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1.

RXD

0.965/BR

1.04/BR

TXD

Pulse Width

The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1.

Parameters listed are guaranteed by design.

TXD

0.965/BR

1.04/BR

Phase B

(Input)

Phase A

(Input)

RXD

SCI receive

data pin

(Input)

TXD

SCI receive

data pin

(Input)

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Analog-to-Digital Converter (ADC) Characteristics

56F807 Technical Data

3.12 Analog-to-Digital Converter (ADC) Characteristics

Table 35. ADC Characteristics

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, V

REF

= V

-0.3V, ADCDIV = 4, 9, or 14, (for optimal

performance), ADC clock = 4MHz, 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Characteristic

Symbol

Min

Typ

Max

Unit

ADC input voltages

ADCIN

For optimum ADC performance, keep the minimum V

ADCIN

value > 25mV. Inputs less than 25mV may convert

to a digital output code of 0.

REF

must be equal to or less than V

DDA

and must be greater than 2.7V. For optimal ADC performance, set V

REF

to V

DDA

-0.3V.

Resolution

Bits

Integral Non-Linearity

Measured in 10-90% range.

INL

+/- 2.5

+/- 4

LSB

LSB = Least Significant Bit.

Differential Non-Linearity

DNL

+/- 0.9

+/- 1

LSB

Monotonicity

GUARANTEED

ADC internal clock

Guaranteed by characterization.

ADIC

0.5

MHz

Conversion range

SSA

DDA

Conversion time

ADC

AIC

cycles

AIC

= 1/

ADIC

Sample time

ADS

AIC

cycles

Input capacitance

ADI

Gain Error (transfer gain)

GAIN

0.93

1.00

1.08

Total Harmonic Distortion

THD

Offset Voltage

OFFSET

-90

-25

+10

Signal-to-Noise plus Distortion

SINAD

Effective Number of Bits

ENOB

bit

Spurious Free Dynamic Range

SFDR

Bandwidth

100

KHz

ADC Quiescent Current (each dual ADC)

ADC

REF

Quiescent Current (each dual ADC)

VREF

16.5

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56F807 Technical Data

Figure 29. Equivalent Analog Input Circuit

Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf)

Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf)

Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms)

Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is
only connected to it at sampling time. (1pf)

3.13 Controller Area Network (CAN) Timing

Table 36. CAN Timing

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, MSCAN Clock = 30MHz

Figure 30. Bus Wakeup Detection

Characteristic

Symbol

Min

Max

Unit

Baud Rate

CAN

Mbps

Bus Wakeup detection

If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any

bus event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus
wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds
originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of
1Mbps.

Parameters listed are guaranteed by design

WAKEUP

ADC analog input

WAKEUP

MSCAN_RX

CAN receive

data pin

(Input)

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JTAG Timing

56F807 Technical Data

3.14 JTAG Timing

Table 37. JTAG Timing

1, 3

Operating Conditions:

= V

SSA

= 0 V, V

= V

DDA

= 3.03.6 V, T

= 40

to +85

C, C

50pF, f

= 80MHz

Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation,

T = 12.5ns.

Characteristic

Symbol

Min

Max

Unit

TCK frequency of operation

TCK frequency of operation must be less than 1/8 the processor rate.

Parameters listed are guaranteed by design.

MHz

TCK cycle time

100

TCK clock pulse width

TMS, TDI data set-up time

0.4

TMS, TDI data hold time

1.2

TCK low to TDO data valid

26.6

TCK low to TDO tri-state

23.5

TRST assertion time

TRST

DE assertion time

Figure 31. Test Clock Input Timing Diagram

TCK

(Input)

= V

+ (V

)/2

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Package and Pin-Out Information 56F807

56F807 Technical Data

Part 4 Packaging

4.1 Package and Pin-Out Information 56F807

This section contains package and pin-out information for the 56F807. This device comes in two case types:
low-profile quad flat pack (LQFP) or mold array process ball grid assembly (MAPBGA).

Figure 35

shows

the package outline for the LQFP case,

Figure 36

shows the mechanical parameters for the LQFP case, and

Table 38

lists the pinout for the LQFP case.

Figure 37

shows the mechanical parameters for the MAPBGA

case, and

Table 39

lists the pinout for the MAPBGA package.

Figure 35. Top View, 56F807 160-pin LQFP Package

A0
A1
A2
A3
A4
A5
A6
A7

A8
A9

A10
A11
A12
A13
A14
A15
V

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

D10
V

D11
D12
D13
D14
D15

GPIOB0

I
O

ISB

VPP

PIN 1

ORIENTATION

MARK

PIN 41

PIN 121

PIN 81

ANB7
ANB6
ANB5
ANB4
ANB3
ANB2
ANB1
ANB0
V

SSA

DDA

VREF2
ANA7
ANA6
ANA5
ANA4
ANA3
ANA2
ANA1
ANA0
V

SSA

DDA

VREF
RESET
RSTO
V

EXTAL
XTAL
V

DDA

SSA

EXTBOOT
FAULTA3
FAULTA2
FAULTA1
FAULTA0
PWMA5

HOM

MOS

Motorola

56F807

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56F807 Technical Data

Figure 36. 160-pin LQFP Mechanical Information

CASE 1259-01

ISSUE O

DIM

MIN

MAX

MILLIMETERS

---

1.60

0.05

0.15

1.35

1.45

0.17

0.27

0.17

0.23

0.09

0.20

0.09

0.16

26.00 BSC

24.00 BSC

0.50 BSC

26.00 BSC

24.00 BSC

0.45

0.75

1.00 REF

0.08

---

0.08

0.20

---

0.25

NOTES:
1.

DIMENSIONS ARE IN MILLIMETERS.

INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.

DATUMS A, B, AND D TO BE DETERMINED
WHERE THE LEADS EXIT THE PLASTIC BODY
AT DATUM PLANE H.

DIMENSIONS D1 AND E1 DO NOT INCLUDE
MOLD PROTRUSION. ALLOWABLE
PROTRUSION IS 0.25mm PER SIDE.
DIMENSIONS D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS
INCLUDING MOLD MISMATCH.

DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL NOT CAUSE THE LEAD
WIDTH TO EXCEED THE MAXIMUM b
DIMENSION BY MORE THAN 0.08mm.
DAMBAR CAN NOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN A PROTRUSION AND AN
ADJACENT LEAD IS 0.07mm.

EXACT SHAPE OF CORNERS MAY VARY.

G G

A-B

0.20

A-B

0.08

A-B

0.20

160X

0.08 C

SEATING
PLANE

156X

e/2

160X

DETAIL F

(L1)

GAGE
PLANE

DETAIL F

(b)

SECTION G-G

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Package and Pin-Out Information 56F807

56F807 Technical Data

Table 38. 56F807 LQFP Package Pin Identification by Pin Number

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

GPIOB1

PWMA5

121

GPIOB2

FAULTA0

122

GPIOB3

FAULTA1

123

ISA0

GPIOB4

FAULTA2

124

ISA1

GPIOB5

FAULTA3

125

ISA2

GPIOB6

EXTBOOT

126

TD0

GPIOB7

SSA

127

TD1

DDA

128

TD2

GPIOD0

129

TD3

GPIOD1

130

TC0

GPIOD2

131

TC1

A10

GPIOD3

XTAL

132

TRST

A11

GPIOD4

EXTAL

133

TCS

A12

GPIOD5

134

TCK

A13

TXD1

135

TMS

A14

RXD1

136

TDI

A15

PWMB0

RSTO

137

TDO

PWMB1

RESET

138

VCAPC2

PWMB2

VREF

139

MSCAN_TX

PWMB3

100

DDA

140

PWMB4

101

SSA

141

PWMB5

102

ANA0

142

MSCAN_RX

103

ANA1

143

ISB0

104

ANA2

144

SCLK

VCAPC1

105

ANA3

145

MISO

ISB1

106

ANA4

146

MOSI

ISB2

107

ANA5

147

PHA0

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56F807 Technical Data

VPP2

108

ANA6

148

PHB0

IRQA

109

ANA7

149

INDX0

IRQB

110

VREF2

150

HOME0

FAULTB0

111

DDA

151

PHA1

FAULTB1

112

SSA

152

PHB1

D10

FAULTB2

113

ANB0

153

FAULTB3

114

ANB1

154

INDX1

D11

PWMA0

115

ANB2

155

HOME1

D12

116

ANB3

156

VPP

D13

PWMA1

117

ANB4

157

D14

PWMA2

118

ANB5

158

CLKO

D15

PWMA3

119

ANB6

159

TXD0

GPIOB0

PWMA4

120

ANB7

160

RXD0

Table 38. 56F807 LQFP Package Pin Identification by Pin Number (Continued)

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

Pin No.

Signal Name

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Package and Pin-Out Information 56F807

56F807 Technical Data

Figure 37. 160 MAPBGA Mechanical Information

NOTES:
1.

DIMENSIONS ARE IN MILLIMETERS.

INTERPRET DIMENSIONS AND
TOLERANCES PER ASME Y14.5M, 1994.

DIMENSION b IS MEASURED AT THE
MAXIMUM SOLDER BALL DIAMETER,
PARALLEL TO DATUM PLANE Z.

DATUM Z (SEATING PLANE) IS DEFINED BY
THE SPHERICAL CROWNS OF THE SOLDER
BALLS.

PARALLELISM MEASUREMENT SHALL
EXCLUDE ANY EFFECT OF MARK ON TOP
SURFACE OF PACKAGE.

CASE 1268-01

ISSUE O

DATE 04/06/98

0.20

LASER MARK FOR PIN 1
IDENTIFICATION IN
THIS AREA

13X

0.15 Z

0.30 Z

ROTATED 90 CLOCKWISE

DETAIL K

VIEW M-M

13X

0.30

0.10 Z

160X

METALIZED MARK FOR
PIN 1 IDENTIFICATION
IN THIS AREA

12 11 10

160X

DIM MIN

MAX

MILLIMETERS

1.32

1.75

0.27

0.47

1.18 REF

0.35

0.65

15.00 BSC

1.00 BSC

0.50 BSC

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56F807 Technical Data

Table 39. 160 MAPBGA Package Pin Identification by Pin Number

Solder

Ball

Signal Name

Solder

Ball

Signal Name

Solder

Ball

Signal Name

Solder

Ball

Signal Name

GPIOB5

K12

SSA

E10

TC1

GPIOB6

K13

DDA

TRST

GPIOB7

L14

TCS

K11

TCK

GPIOD0

K14

TMS

GPIOD1

J13

XTAL

TDI

GPIOD2

J12

EXTAL

TDO

GPIOD3

J14

VCAPC2

GPIOD4

J11

MSCAN_TX

GPIOD5

H13

TXD1

H12

RSTO

A10

RXD1

H14

RESET

MSCAN_RX

A11

PWMB0

H11

VREF

A12

PWMB1

G12

DDA

A13

PWMB2

G11

SSA

A14

PWMB3

G14

ANA0

A15

PWMB4

B13

PWMB5

A14

B12

ISA0

ISB0

A13

ISA1

P14

PWMA5

A12

ISA2

M13

FAULTA0

B11

TD0

D10

GPIOB1

L12

FAULTA1

A11

TD1

GPIOB2

N14

FAULTA2

D10

TD2

D11

GPIOB3

L13

FAULTA3

B10

TD3

D12

GPIOB4

M14

EXTBOOT

A10

TC0

D13

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Package and Pin-Out Information 56F807

56F807 Technical Data

D14

N11

D14

SSA

PHB0

D15

P13

PWMA1

D11

ANA8

INDX0

GPIOB0

N12

PWMA2

D12

ANA9

HOME0

K10

VCAPC1

N13

PWMA3

D13

ANA10

PHA1

ISB1

M12

PWMA4

C14

ANA11

PHB1

ISB2

F11

ANA1

C13

ANA12

L10

VPP2

G13

ANA2

C11

ANA13

INDX1

IRQA

F12

ANA3

B14

ANA14

HOME1

P10

IRQB

F14

ANA4

C12

ANA15

VPP

P11

FAULTB0

E11

ANA5

CLKO

N10

FAULTB1

F13

ANA6

SCLK

TXD0

L11

FAULTB2

E12

ANA7

MISO

RXD0

M11

FAULTB3

E14

VREF2

MOSI

P12

PWMA0

E13

DDA

PHA0

Table 39. 160 MAPBGA Package Pin Identification by Pin Number (Continued)

Solder

Ball

Signal Name

Solder

Ball

Signal Name

Solder

Ball

Signal Name

Solder

Ball

Signal Name

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56F807 Technical Data

Part 5 Design Considerations

5.1 Thermal Design Considerations

An estimation of the chip junction temperature, T

, in

C can be obtained from the equation:

Equation 1:

Where:

= ambient temperature °C

= package junction-to-ambient thermal resistance °C/W

= power dissipation in package

Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and
a case-to-ambient thermal resistance:

Equation 2:

Where:

= package junction-to-ambient thermal resistance °C/W

= package junction-to-case thermal resistance °C/W

= package case-to-ambient thermal resistance °C/W

is device-related and cannot be influenced by the user. The user controls the thermal environment to

change the case-to-ambient thermal resistance, R

. For example, the user can change the air flow around

the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or
otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This
model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through
the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device
thermal performance may need the additional modeling capability of a system level thermal simulation tool.

The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the
package is mounted. Again, if the estimations obtained from R

do not satisfactorily answer whether the

thermal performance is adequate, a system level model may be appropriate.

Definitions:

A complicating factor is the existence of three common definitions for determining the junction-to-case
thermal resistance in plastic packages:

Measure the thermal resistance from the junction to the outside surface of the package (case) closest
to the chip mounting area when that surface has a proper heat sink. This is done to minimize
temperature variation across the surface.

Measure the thermal resistance from the junction to where the leads are attached to the case. This
definition is approximately equal to a junction to board thermal resistance.

Use the value obtained by the equation (T

)/P

where T

is the temperature of the package

case determined by a thermocouple.

(

)

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56F807 Technical Data

The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T
thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that
the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple
junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire.

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface
between the case of the package and the interface material. A clearance slot or hole is normally required in
the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this case
temperature, the junction temperature is determined from the junction-to-case thermal resistance.

5.2 Electrical Design Considerations

Use the following list of considerations to assure correct operation:

Provide a low-impedance path from the board power supply to each V

pin on the hybrid

controller, and from the board ground to each V

pin.

The minimum bypass requirement is to place 0.1

F capacitors positioned as close as possible to

the package supply pins. The recommended bypass configuration is to place one bypass capacitor
on each of the V

pairs, including V

DDA

SSA.

Ceramic and tantalum capacitors tend to

provide better performance tolerances.

Ensure that capacitor leads and associated printed circuit traces that connect to the chip V

and

pins are less than 0.5 inch per capacitor lead.

Bypass the V

and V

layers of the PCB with approximately 100

F, preferably with a

high-grade capacitor such as a tantalum capacitor.

Because the controller's output signals have fast rise and fall times, PCB trace lengths should be
minimal.

Consider all device loads as well as parasitic capacitance due to PCB traces when calculating
capacitance. This is especially critical in systems with higher capacitive loads that could create
higher transient currents in the V

and V

circuits.

CAUTION

This device contains protective circuitry to guard
against damage due to high static voltage or electrical
fields. However, normal precautions are advised to
avoid application of any voltages higher than maximum
rated voltages to this high-impedance circuit. Reliability
of operation is enhanced if unused inputs are tied to an
appropriate voltage level.

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56F807 Technical Data

Take special care to minimize noise levels on the VREF, V

DDA

and V

SSA

pins.

Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as
development or debugging systems) should allow a means to assert TRST whenever RESET is
asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at
power up for proper operation. Designs that do not require debugging functionality, such as
consumer products, TRST should be tied low.

Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide
an interface to this port to allow in-circuit Flash programming.

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Electrical Design Considerations

56F807 Technical Data

Part 6 Ordering Information

Table 40

lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales

office or authorized distributor to determine availability and to order parts.

Table 40. 56F807 Ordering Information

Part

Supply

Voltage

Package Type

Pin

Count

Frequency

(MHz)

Order Number

56F807

3.03.6 V

Low-Profile Quad Flat Pack (LQFP)

160

DSP56F807PY80

56F807

3.03.6 V

Mold Array Process Ball Grid Array
(MAPBGA)

160

DSP56F807VF80

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HOW TO REACH US:

USA/EUROPE/LOCATIONS NOT LISTED:
Motorola Literature Distribution
P.O. Box 5405, Denver, Colorado 80217
1-800-521-6274 or 480-768-2130

JAPAN:
Motorola Japan Ltd.
SPS, Technical Information Center
3-20-1, Minami-Azabu
Minato-ku
Tokyo 106-8573, Japan
81-3-3440-3569

ASIA/PACIFIC:
Motorola Semiconductors H.K. Ltd.
Silicon Harbour Centre
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T. Hong Kong
852-26668334

HOME PAGE:
http://motorola.com/semiconductors

Information in this document is provided solely to enable system and software

implementers to use Motorola products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits or

integrated circuits based on the information in this document.

Motorola reserves the right to make changes without further notice to any products

herein. Motorola makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Motorola assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

damages. "Typical" parameters which may be provided in Motorola data sheets

and/or specifications can and do vary in different applications and actual

performance may vary over time. All operating parameters, including "Typicals"

must be validated for each customer application by customer's technical experts.

Motorola does not convey any license under its patent rights nor the rights of

others. Motorola products are not designed, intended, or authorized for use as

components in systems intended for surgical implant into the body, or other

applications intended to support or sustain life, or for any other application in which

the failure of the Motorola product could create a situation where personal injury or

death may occur. Should Buyer purchase or use Motorola products for any such

unintended or unauthorized application, Buyer shall indemnify and hold Motorola

and its officers, employees, subsidiaries, affiliates, and distributors harmless

against all claims, costs, damages, and expenses, and reasonable attorney fees

arising out of, directly or indirectly, any claim of personal injury or death associated

with such unintended or unauthorized use, even if such claim alleges that Motorola

was negligent regarding the design or manufacture of the part.

Motorola and the Stylized M Logo are registered in the U.S. Patent and Trademark
Office. digital dna is a trademark of Motorola, Inc. All other product or service
names are the property of their respective owners. Motorola, Inc. is an Equal
Opportunity/Affirmative Action Employer.

DSP56F807/D

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Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56F807VF80

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: DSP56F807VF80