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Электронный компонент: MC33151P

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MC34151
MC33151
SEMICONDUCTOR
TECHNICAL DATA
HIGH SPEED
DUAL MOSFET DRIVERS
PIN CONNECTIONS
Order this document by MC34151/D
D SUFFIX
PLASTIC PACKAGE
CASE 751
(SO8)
P SUFFIX
PLASTIC PACKAGE
CASE 626
8
1
1
8
1
2
3
4
5
6
7
8
N.C.
Logic Input A
Gnd
Logic Input B
N.C.
Drive Output A
VCC
Drive Output B
(Top View)
Device
Operating
Temperature Range
Package
ORDERING INFORMATION
MC34151D
MC34151P
TA = 0
to +70
C
SO8
Plastic DIP
MC33151D
MC33151P
SO8
Plastic DIP
TA = 40
to +85
C
1
MOTOROLA ANALOG IC DEVICE DATA
High Speed Dual
MOSFET Drivers
The MC34151/MC33151 are dual inverting high speed drivers specifically
designed for applications that require low current digital circuitry to drive
large capacitive loads with high slew rates. These devices feature low input
current making them CMOS and LSTTL logic compatible, input hysteresis for
fast output switching that is independent of input transition time, and two high
current totem pole outputs ideally suited for driving power MOSFETs. Also
included is an undervoltage lockout with hysteresis to prevent erratic system
operation at low supply voltages.
Typical applications include switching power supplies, dc to dc
converters, capacitor charge pump voltage doublers/inverters, and motor
controllers.
These devices are available in dualinline and surface mount packages.
Two Independent Channels with 1.5 A Totem Pole Output
Output Rise and Fall Times of 15 ns with 1000 pF Load
CMOS/LSTTL Compatible Inputs with Hysteresis
Undervoltage Lockout with Hysteresis
Low Standby Current
Efficient High Frequency Operation
Enhanced System Performance with Common Switching Regulator
Control ICs
Pin Out Equivalent to DS0026 and MMH0026
Representative Block Diagram
+
+
+
VCC
6
5.7V
Logic Input A
2
Logic Input B
4
Gnd
3
100k
Drive Output A
7
Drive Output B
5
+
+
+
+
100k
Motorola, Inc. 1996
Rev 0
MC34151 MC33151
2
MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Power Supply Voltage
VCC
20
V
Logic Inputs (Note 1)
Vin
0.3 to VCC
V
Drive Outputs (Note 2)
Totem Pole Sink or Source Current
Diode Clamp Current (Drive Output to VCC)
IO
IO(clamp)
1.5
1.0
A
Power Dissipation and Thermal Characteristics
D Suffix SO8 Package Case 751
Maximum Power Dissipation @ TA = 50
C
Thermal Resistance, JunctiontoAir
P Suffix 8Pin Package Case 626
Maximum Power Dissipation @ TA = 50
C
Thermal Resistance, JunctiontoAir
PD
R
JA
PD
R
JA
0.56
180
1.0
100
W
C/W
W
C/W
Operating Junction Temperature
TJ
+150
C
Operating Ambient Temperature
MC34151
MC33151
TA
0 to +70
40 to +85
C
Storage Temperature Range
Tstg
65 to +150
C
ELECTRICAL CHARACTERISTICS
(VCC = 12 V, for typical values TA = 25
C, for min/max values TA is the only operating ambient
temperature range that applies [Note 3], unless otherwise noted.)
Characteristics
Symbol
Min
Typ
Max
Unit
LOGIC INPUTS
Input Threshold Voltage High State Logic 1
Input Threshold Voltage
Low State Logic 0
VIH
VIL
2.6
1.75
1.58
0.8
V
Input Current High State (VIH = 2.6 V)
Input Current
Low State (VIL = 0.8 V)
IIH
IIL

200
20
500
100
A
DRIVE OUTPUT
Output Voltage Low State (ISink = 10 mA)
Output Voltage Low State
(ISink = 50 mA)
Output Voltage Low State
(ISink = 400 mA)
Output Voltage
High State (ISource = 10 mA)
Output Voltage High State
(ISource = 50 mA)
Output Voltage High State
(ISource = 400 mA)
VOL
VOH


10.5
10.4
9.5
0.8
1.1
1.7
11.2
11.1
10.9
1.2
1.5
2.5


V
Output PullDown Resistor
RPD
100
k
SWITCHING CHARACTERISTICS (TA = 25
C)
Propagation Delay (10% Input to 10% Output, CL = 1.0 nF)
Logic Input to Drive Output Rise
Logic Input to Drive Output Fall
tPLH(in/out)
tPHL(in/out)

35
36
100
100
ns
Drive Output Rise Time (10% to 90%) CL = 1.0 nF
Drive Output Rise Time (10% to 90%)
CL = 2.5 nF
tr

14
31
30
ns
Drive Output Fall Time (90% to 10%) CL = 1.0 nF
Drive Output Fall Time (90% to 10%)
CL = 2.5 nF
tf

16
32
30
ns
TOTAL DEVICE
Power Supply Current
Standby (Logic Inputs Grounded)
Operating (CL = 1.0 nF Drive Outputs 1 and 2, f = 100 kHz)
ICC

6.0
10.5
10
15
mA
Operating Voltage
VCC
6.5
18
V
NOTES: 1. For optimum switching speed, the maximum input voltage should be limited to 10 V or VCC, whichever is less.
2. Maximum package power dissipation limits must be observed.
3. Tlow =
0
C for MC34151
Thigh = +70
C for MC34151
40
C for MC33151
+85
C for MC33151
MC34151 MC33151
3
MOTOROLA ANALOG IC DEVICE DATA
Figure 1. Switching Characteristics Test Circuit
Figure 2. Switching Waveform Definitions
Figure 3. Logic Input Current versus
Input Voltage
Figure 4. Logic Input Threshold Voltage
versus Temperature
Figure 5. Drive Output LowtoHigh Propagation
Delay versus Logic Overdrive Voltage
Figure 6. Drive Output HightoLow Propagation
Delay versus Logic Input Overdrive Voltage
Vin, INPUT VOLTAGE (V)
, INPUT

CURRENT
(mA)
inI
VCC = 12 V
TA = 25
C
TA, AMBIENT TEMPERATURE (
C)
V
th
, INPUT

THRESHOLD
VOL
T
AGE (V)
VCC = 12 V
Upper Threshold
Low State Output
Lower Threshold
High State Output
Vin, INPUT OVERDRIVE VOLTAGE BELOW LOWER THRESHOLD (V)
t PLH(IN/OUT)
, DRIVE OUTPUT
PROP
AGA
TION DELA
Y
(ns)
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
Vth(lower)
VCC = 12 V
CL = 1.0 nF
TA = 25
C
Vin, INPUT OVERDRIVE VOLTAGE ABOVE UPPER THRESHOLD (V)
t PHL(IN/OUT)
, DRIVE OUTPUT
PROP
AGA
TION DELA
Y
(ns)
VCC = 12 V
CL = 1.0 nF
TA = 25
C
Vth(upper)
Overdrive Voltage is with Respect
to the Logic Input Lower Threshold
+
+
+
6
5.7V
Logic Input
2
4
3
100k
Drive Output
7
5
+
+
+
+
100k
12V
4.7
0.1
50
CL
+
5.0 V
0 V
10%
90%
tPHL
tPLH
90%
10%
tf
tr
Logic Input
tr, tf
10 ns
Drive Output
2.4
2.0
1.6
1.2
0.8
0.4
0
2.2
2.0
1.8
1.6
1.4
1.2
1.0
200
160
120
80
40
0
200
160
120
80
40
0
0
2.0
4.0
6.0
8.0
10
12
55
25
0
25
50
75
100
125
1.6
1.2
0.8
0.4
0
0
1.0
2.0
3.0
4.0
MC34151 MC33151
4
MOTOROLA ANALOG IC DEVICE DATA
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25
C
Figure 7. Propagation Delay
Figure 8. Drive Output Clamp Voltage
versus Clamp Current
Figure 9. Drive Output Saturation Voltage
versus Load Current
Figure 10. Drive Output Saturation Voltage
versus Temperature
Figure 11. Drive Output Rise Time
Figure 12. Drive Output Fall Time
90%
10%
50 ns/DIV
90%
10%
10 ns/DIV
90%
10%
10 ns/DIV
IO, OUTPUT LOAD CURRENT (A)
V
clamp
,
OUTPUT
CLAMP

VOL
T
AGE (V)
High State Clamp
(Drive Output Driven Above VCC)
VCC
Gnd
Low State Clamp
(Drive Output Driven Below Ground)
VCC = 12 V
80
s Pulsed Load
120 Hz Rate
TA = 25
C
IO, OUTPUT LOAD CURRENT (A)
V
sat
, OUTPUT
SA
TURA
TION VOL
T
AGE(V)
Source Saturation
(Load to Ground)
VCC = 12 V
80
s Pulsed Load
120 Hz Rate
TA = 25
C
VCC
Sink Saturation
(Load to VCC)
Gnd
TA, AMBIENT TEMPERATURE (
C)
V
sat
, OUTPUT
SA
TURA
TION VOL
T
AGE(V)
Source Saturation
(Load to Ground)
Sink Saturation
(Load to VCC)
VCC = 12 V
Isource = 400 mA
Isink = 400 mA
VCC
Isource = 10 mA
Isink = 10 mA
Gnd
Drive Output
Logic Input
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25
C
VCC = 12 V
Vin = 5 V to 0 V
CL = 1.0 nF
TA = 25
C
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
55
25
0
25
50
75
100
125
3.0
2.0
1.0
0
0
1.0
0
1.0
2.0
3.0
3.0
2.0
1.0
0
0
0.5
0.7
0.9
1.1
1.9
1.7
1.5
1.0
0.8
0.6
0
MC34151 MC33151
5
MOTOROLA ANALOG IC DEVICE DATA
Figure 13. Drive Output Rise and Fall Time
versus Load Capacitance
Figure 14. Supply Current versus Drive Output
Load Capacitance
Figure 15. Supply Current versus Input Frequency
Figure 16. Supply Current versus Supply Voltage
CL, OUTPUT LOAD CAPACITANCE (nF)
t
, OUTPUT
RISE-F
ALL

TIME(ns)
tf
tr
t r
VCC = 12 V
VIN = 0 V to 5.0 V
TA = 25
C
CL, OUTPUT LOAD CAPACITANCE (nF)
I CC
, SUPPL
Y

CURRENT
(mA)
VCC = 12 V
Both Logic Inputs Driven
0 V to 5.0 V
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25
C
f = 500 kHz
f = 200 kHz
f = 50 kHz
I CC
, SUPPL
Y

CURRENT
(mA)
1
2
3
4
Both Logic Inputs Driven
0 V to 5.0 V,
50% Duty Cycle
Both Drive Outputs Loaded
TA = 25
C
1 VCC = 18 V, CL = 2.5 nF
2 VCC = 12 V, CL = 2.5 nF
3 VCC = 18 V, CL = 1.0 nF
4 VCC = 12 V, CL = 1.0 nF
f, INPUT FREQUENCY (Hz)
I CC
, SUPPL
Y

CURRENT
(mA)
VCC, SUPPLY VOLTAGE (V)
TA = 25
C
Logic Inputs at VCC
Low State Drive Outputs
Logic Inputs Grounded
High State Drive Outputs
f
80
60
40
20
0
80
60
40
20
0
80
60
40
20
0
8.0
6.0
4.0
2.0
0
0.1
1.0
10
0.1
1.0
10
100
1.0 M
0
4.0
8.0
12
16
10 k
APPLICATIONS INFORMATION
Description
The MC34151 is a dual inverting high speed driver
specifically designed to interface low current digital circuitry
with power MOSFETs. This device is constructed with
Schottky clamped Bipolar Analog technology which offers a
high degree of performance and ruggedness in hostile
industrial environments.
Input Stage
The Logic Inputs have 170 mV of hysteresis with the input
threshold centered at 1.67 V. The input thresholds are
insensitive to VCC making this device directly compatible with
CMOS and LSTTL logic families over its entire operating
voltage range. Input hysteresis provides fast output switching
that is independent of the input signal transition time,
preventing output oscillations as the input thresholds are
crossed. The inputs are designed to accept a signal
amplitude ranging from ground to VCC. This allows the output
of one channel to directly drive the input of a second channel
for masterslave operation. Each input has a 30 k
pulldown resistor so that an unconnected open input will
cause the associated Drive Output to be in a known high
state.
Output Stage
Each totem pole Drive Output is capable of sourcing and
sinking up to 1.5 A with a typical `on' resistance of 2.4
at
1.0 A. The low `on' resistance allows high output currents to
be attained at a lower VCC than with comparative CMOS
drivers. Each output has a 100 k
pulldown resistor to keep
the MOSFET gate low when VCC is less than 1.4 V. No over
current or thermal protection has been designed into the
device, so output shorting to VCC or ground must be avoided.
Parasitic inductance in series with the load will cause the
driver outputs to ring above VCC during the turnon transition,
and below ground during the turnoff transition. With CMOS
drivers, this mode of operation can cause a destructive
output latchup condition. The MC34151 is immune to output
latchup. The Drive Outputs contain an internal diode to VCC
for clamping positive voltage transients. When operating with
VCC at 18 V, proper power supply bypassing must be
observed to prevent the output ringing from exceeding the
maximum 20 V device rating. Negative output transients are
clamped by the internal NPN pullup transistor. Since full
supply voltage is applied across the NPN pullup during the
negative output transient, power dissipation at high
frequencies can become excessive. Figures 19, 20, and 21
show a method of using external Schottky diode clamps to
reduce driver power dissipation.
Undervoltage Lockout
An undervoltage lockout with hysteresis prevents erratic
system operation at low supply voltages. The UVLO forces
the Drive Outputs into a low state as VCC rises from 1.4 V to