MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

MC68HC908GR8
MC68HC908GR4

Technical Data -- Rev 4.0

Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer's technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

Motorola and

are registered trademarks of Motorola, Inc.

DigitalDNA is a trademark of Motorola, Inc.

� Motorola, Inc., 2002

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List of Paragraphs

Technical Data -- MC68HC908GR8

List of Paragraphs

List of Paragraphs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Section 1. General Description . . . . . . . . . . . . . . . . . . . . 25

Section 2. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Section 3. Low Power Modes . . . . . . . . . . . . . . . . . . . . . . 49

Section 4. Resets and Interrupts . . . . . . . . . . . . . . . . . . . 61

Section 5. Analog-to-Digital Converter (ADC) . . . . . . . . 79

Section 6. Break Module (BRK) . . . . . . . . . . . . . . . . . . . . 91

Section 7. Clock Generator Module (CGMC) . . . . . . . . . 99

Section 8. Configuration Register (CONFIG) . . . . . . . . 129

Section 9. Computer Operating Properly (COP) . . . . . 133

Section 10. Central Processing Unit (CPU) . . . . . . . . . 139

Section 11. Flash Memory . . . . . . . . . . . . . . . . . . . . . . . 157

Section 12. External Interrupt (IRQ) . . . . . . . . . . . . . . . 167

Section 13. Keyboard Interrupt (KBI) . . . . . . . . . . . . . . 175

Section 14. Low-Voltage Inhibit (LVI) . . . . . . . . . . . . . . 183

Section 15. Monitor ROM (MON) . . . . . . . . . . . . . . . . . . 189

Section 16. Input/Output Ports (I/O) . . . . . . . . . . . . . . . 205

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Table of Contents

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Table of Contents

List of Paragraphs

Table of Contents

List of Tables

List of Figures

Section 1. General Description

1.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.4

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.5

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.6

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Section 2. Memory Map

2.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 35

2.4

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.5

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

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Section 3. Low Power Modes

3.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3

Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 50

3.4

Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.5

Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.6

Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7

Computer Operating Properly Module (COP). . . . . . . . . . . . . . 52

3.8

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . 53

3.9

Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . 53

3.10

Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . 54

3.11

Serial Communications Interface Module (SCI) . . . . . . . . . . . . 54

3.12

Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . 55

3.13

Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . 55

3.14

Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.15

Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.16

Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Section 4. Resets and Interrupts

4.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

4.3

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

4.4

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Section 5. Analog-to-Digital Converter (ADC)

5.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

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5.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.5

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.6

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

5.7

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.8

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Section 6. Break Module (BRK)

6.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

6.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6.5

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

6.6

Break Module Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Section 7. Clock Generator Module (CGMC)

7.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.5

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.6

CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.7

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.8

Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.9

Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125

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Section 8. Configuration Register (CONFIG)

8.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

Section 9. Computer Operating Properly (COP)

9.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.4

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.5

COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.6

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.7

Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.8

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

9.9

COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .137

Section 10. Central Processing Unit (CPU)

10.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.4

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10.5

Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10.6

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

10.7

CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 146

10.8

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.9

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

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Section 11. Flash Memory

11.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.4

FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

11.5

FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 160

11.6

FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 161

11.7

FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . .162

11.8

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

11.9

Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Section 12. External Interrupt (IRQ)

12.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

12.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

12.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167

12.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

12.5

IRQ1 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170

12.6

IRQ Module During Break Interrupts . . . . . . . . . . . . . . . . . . .171

12.7

IRQ Status and Control Register . . . . . . . . . . . . . . . . . . . . . . 172

Section 13. Keyboard Interrupt (KBI)

13.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

13.5

Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

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13.6

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

13.7

Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180

13.8

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

Section 14. Low-Voltage Inhibit (LVI)

14.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

14.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

14.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183

14.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184

14.5

LVI Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

14.6

LVI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188

14.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .188

Section 15. Monitor ROM (MON)

15.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

15.5

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

Section 16. Input/Output Ports (I/O)

16.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

16.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

16.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

16.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

16.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

16.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

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16.7

Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

Section 17. RAM

17.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

17.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

17.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

Section 18. Serial Communications Interface (SCI)

18.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

18.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

18.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

18.4

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

18.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

18.6

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

18.7

SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 251

18.8

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

18.9

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Section 19. System Integration Module (SIM)

19.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

19.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

19.3

SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 275

19.4

Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 276

19.5

SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

19.6

Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

19.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

19.8

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

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Section 20. Serial Peripheral Interface (SPI)

20.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

20.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

20.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

20.4

Pin Name Conventions and I/O Register Addresses . . . . . . . 298

20.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

20.6

Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

20.7

Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 309

20.8

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

20.9

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318

20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

Section 21. Timebase Module (TBM)

21.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

21.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

21.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

21.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

21.5

Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . . 331

21.6

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

21.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

Section 22. Timer Interface Module (TIM)

22.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

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Table of Contents

22.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

22.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

22.4

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

22.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

22.6

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

22.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

22.8

TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 348

22.9

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

Section 23. Electrical Specifications

23.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361

23.2

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362

23.3

Functional Operating Range. . . . . . . . . . . . . . . . . . . . . . . . . . 363

23.4

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

23.5

5.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 364

23.6

3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 366

23.7

5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

23.8

3.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

23.9

Output High-Voltage Characteristics . . . . . . . . . . . . . . . . . . .370

23.10 Output Low-Voltage Characteristics . . . . . . . . . . . . . . . . . . . . 373

23.11 Typical Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376

23.12 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378

23.13 5.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379

23.14 3.0 V SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380

23.15 Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 383

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23.16 Clock Generation Module Characteristics . . . . . . . . . . . . . . . 383

23.17 Memory Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385

Section 24. Mechanical Specifications

24.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

24.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387

24.3

32-Pin LQFP (Case #873A) . . . . . . . . . . . . . . . . . . . . . . . . . .388

24.4

28-Pin PDIP (Case #710) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389

24.5

28-Pin SOIC (Case #751F). . . . . . . . . . . . . . . . . . . . . . . . . . . 390

Section 25. Ordering Information

25.1

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

25.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391

25.3

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

25.4

Development Tools. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

Glossary

Revision History

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Changes from Rev 3.0 published in February 2002 to Rev 4.0
published in June 2002. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405

Changes from Rev 2.0 published in January 2002 to Rev 3.0 pub-
lished in February 2002 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

Changes from Rev 1.0 published in April 2001 to Rev 2.0 pub-
lished in December 2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406

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MOTOROLA

List of Tables

Technical Data -- MC68HC908GR8

List of Tables

Table

Title

Page

2-1

Vector Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4-1

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4-2

Interrupt Source Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5-1

Mux Channel Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5-2

ADC Clock Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

7-1

Numeric Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7-2

PRE 1 and PRE0 Programming . . . . . . . . . . . . . . . . . . . . . . . 117

7-3

VPR1 and VPR0 Programming . . . . . . . . . . . . . . . . . . . . . . . 117

10-1

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10-2

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155

11-1

Examples of protect start address: . . . . . . . . . . . . . . . . . . . . . 166

14-1

LVIOUT Bit Indication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187

15-1

Monitor Mode Signal Requirements and Options . . . . . . . . . . 193

15-2

Mode Differences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

15-3

Monitor Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . 197

15-4

READ (Read Memory) Command . . . . . . . . . . . . . . . . . . . . . 199

15-5

WRITE (Write Memory) Command. . . . . . . . . . . . . . . . . . . . . 199

15-6

IREAD (Indexed Read) Command . . . . . . . . . . . . . . . . . . . . . 200

15-7

IWRITE (Indexed Write) Command . . . . . . . . . . . . . . . . . . . . 200

15-8

READSP (Read Stack Pointer) Command . . . . . . . . . . . . . . .201

15-9

RUN (Run User Program) Command . . . . . . . . . . . . . . . . . . . 201

16-1

Port Control Register Bits Summary. . . . . . . . . . . . . . . . . . . . 208

16-2

Port A Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

16-3

Port B Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

16-4

Port C Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

16-5

Port D Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223

16-6

Port E Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227

18-1

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

18-2

Start Bit Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

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List of Tables

MOTOROLA

18-3

Data Bit Recovery. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244

18-4

Stop Bit Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

18-5

Character Format Selection . . . . . . . . . . . . . . . . . . . . . . . . . .255

18-6

SCI Baud Rate Prescaling . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

18-7

SCI Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266

18-8

SCI Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . 268

19-1

Signal Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . 273

19-2

PIN Bit Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277

19-3

Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286

19-4

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

20-1

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

20-2

SPI Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

20-3

SPI Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

20-4

SPI Master Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . 327

21-1

Timebase Rate Selection for OSC1 = 32.768 kHz . . . . . . . . . 331

22-1

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

22-2

Prescaler Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

22-3

Mode, Edge, and Level Selection . . . . . . . . . . . . . . . . . . . . . .358

23-1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . .362

23-2

Functional Operation Range. . . . . . . . . . . . . . . . . . . . . . . . . . 363

23-3

Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

23-4

5.0V DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 364

23-5

3.0 V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . 366

23-6

5.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368

23-7

3.0 V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369

23-8

Timer Interface Module Characteristics . . . . . . . . . . . . . . . . . 383

23-9

CGM Component Specifications. . . . . . . . . . . . . . . . . . . . . . . 383

25-1

MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392

25-2

Development Tool Kits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393

25-3

Development Tool Components . . . . . . . . . . . . . . . . . . . . . . . 393

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

List of Figures

Technical Data -- MC68HC908GR8

List of Figures

Figure

Title

Page

1-1

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

1-2

QFP Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1-3

DIP And SOIC Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . 31

1-4

Power Supply Bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

2-1

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2-2

Control, Status, and Data Registers . . . . . . . . . . . . . . . . . . . . . 39

4-1

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

4-2

Power-On Reset Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

4-3

SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . . 65

4-4

Interrupt Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

4-5

Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . . 68

4-6

Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

4-7

Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . . .76

4-8

Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . . .76

4-9

Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . . .77

5-1

ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

5-2

ADC Status and Control Register (ADSCR) . . . . . . . . . . . . . . . 85

5-3

ADC Data Register (ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

5-4

ADC Clock Register (ADCLK) . . . . . . . . . . . . . . . . . . . . . . . . . 88

6-1

Break Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 92

6-2

I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

6-3

Break Status and Control Register (BRKSCR). . . . . . . . . . . . . 95

6-4

Break Address Register High (BRKH) . . . . . . . . . . . . . . . . . . . 96

6-5

Break Address Register Low (BRKL) . . . . . . . . . . . . . . . . . . . . 96

6-6

SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . . 96

6-7

SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . . 98

7-1

CGMC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

7-2

CGMC External Connections . . . . . . . . . . . . . . . . . . . . . . . . . 111

7-3

CGMC I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . 114

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List of Figures

MOTOROLA

7-4

PLL Control Register (PCTL) . . . . . . . . . . . . . . . . . . . . . . . . . 115

7-5

PLL Bandwidth Control Register (PBWC) . . . . . . . . . . . . . . . 118

7-6

PLL Multiplier Select Register High (PMSH) . . . . . . . . . . . . . 119

7-7

PLL Multiplier Select Register Low (PMSL) . . . . . . . . . . . . . . 120

7-8

PLL VCO Range Select Register (PMRS) . . . . . . . . . . . . . . . 121

7-9

PLL Reference Divider Select Register (PMDS) . . . . . . . . . . 122

7-10

PLL Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127

8-1

Configuration Register 2 (CONFIG2) . . . . . . . . . . . . . . . . . . .130

8-2

Configuration Register 1 (CONFIG1) . . . . . . . . . . . . . . . . . . .130

9-1

COP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

9-2

COP Control Register (COPCTL) . . . . . . . . . . . . . . . . . . . . . .136

10-1

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10-2

Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10-3

Index register (H:X). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

10-4

Stack pointer (SP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

10-5

Program counter (PC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

10-6

Condition code register (CCR) . . . . . . . . . . . . . . . . . . . . . . . . 143

11-1

FLASH Control Register (FLCR) . . . . . . . . . . . . . . . . . . . . . . 159

11-2

FLASH Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . 164

11-3

FLASH Block Protect Register (FLBPR). . . . . . . . . . . . . . . . . 165

11-4

FLASH Block Protect Start Address . . . . . . . . . . . . . . . . . . . . 165

12-1

IRQ Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .169

12-2

IRQ I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 169

12-3

IRQ Status and Control Register (INTSCR) . . . . . . . . . . . . . . 172

13-1

Keyboard Module Block Diagram . . . . . . . . . . . . . . . . . . . . . .177

13-2

I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177

13-3

Keyboard Status and Control Register (INTKBSCR) . . . . . . . 181

13-4

Keyboard Interrupt Enable Register (INTKBIER) . . . . . . . . . . 182

14-1

LVI Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 185

14-2

LVI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 186

14-3

LVI Status Register (LVISR) . . . . . . . . . . . . . . . . . . . . . . . . . . 187

15-1

Monitor Mode Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191

15-2

Low-Voltage Monitor Mode Entry Flowchart. . . . . . . . . . . . . . 195

15-3

Monitor Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

15-4

Break Transaction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196

15-5

Read Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

15-6

Write Transaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198

15-7

Stack Pointer at Monitor Mode Entry . . . . . . . . . . . . . . . . . . .202

List of Figures

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

List of Figures

15-8

Monitor Mode Entry Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 203

16-1

I/O Port Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 206

16-2

Port A Data Register (PTA) . . . . . . . . . . . . . . . . . . . . . . . . . .209

16-3

Data Direction Register A (DDRA) . . . . . . . . . . . . . . . . . . . . . 210

16-4

Port A I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211

16-5

Port A Input Pullup Enable Register (PTAPUE) . . . . . . . . . . . 212

16-6

Port B Data Register (PTB) . . . . . . . . . . . . . . . . . . . . . . . . . .213

16-7

Data Direction Register B (DDRB) . . . . . . . . . . . . . . . . . . . . . 214

16-8

Port B I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215

16-9

Port C Data Register (PTC) . . . . . . . . . . . . . . . . . . . . . . . . . .216

16-10 Data Direction Register C (DDRC) . . . . . . . . . . . . . . . . . . . . . 217
16-11 Port C I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
16-12 Port C Input Pullup Enable Register (PTCPUE) . . . . . . . . . . . 219
16-13 Port D Data Register (PTD) . . . . . . . . . . . . . . . . . . . . . . . . . .220
16-14 Data Direction Register D (DDRD) . . . . . . . . . . . . . . . . . . . . . 222
16-15 Port D I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
16-16 Port D Input Pullup Enable Register (PTDPUE) . . . . . . . . . . . 224
16-17 Port E Data Register (PTE) . . . . . . . . . . . . . . . . . . . . . . . . . .225
16-18 Data Direction Register E (DDRE) . . . . . . . . . . . . . . . . . . . . . 226
16-19 Port E I/O Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
18-1

SCI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 234

18-2

SCI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 235

18-3

SCI Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

18-4

SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237

18-5

SCI Receiver Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 242

18-6

Receiver Data Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243

18-7

Slow Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246

18-8

Fast Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247

18-9

SCI Control Register 1 (SCC1). . . . . . . . . . . . . . . . . . . . . . . . 253

18-10 SCI Control Register 2 (SCC2). . . . . . . . . . . . . . . . . . . . . . . . 256
18-11 SCI Control Register 3 (SCC3). . . . . . . . . . . . . . . . . . . . . . . . 258
18-12 SCI Status Register 1 (SCS1) . . . . . . . . . . . . . . . . . . . . . . . . 260
18-13 Flag Clearing Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263
18-14 SCI Status Register 2 (SCS2) . . . . . . . . . . . . . . . . . . . . . . . . 264
18-15 SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 265
18-16 SCI Baud Rate Register (SCBR) . . . . . . . . . . . . . . . . . . . . . . 265
19-1

SIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272

19-2

SIM I/O Register Summary. . . . . . . . . . . . . . . . . . . . . . . . . . . 274

List of Figures

Technical Data

MC68HC908GR8 -- Rev 4.0

List of Figures

MOTOROLA

19-3

CGM Clock Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275

19-4

External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277

19-5

Internal Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

19-6

Sources of Internal Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278

19-7

POR Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279

19-8

Interrupt Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

19-9

Interrupt Recovery Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 283

19-10 Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
19-11 Interrupt Recognition Example . . . . . . . . . . . . . . . . . . . . . . . . 285
19-12 Interrupt Status Register 1 (INT1). . . . . . . . . . . . . . . . . . . . . .288
19-13 Interrupt Status Register 2 (INT2). . . . . . . . . . . . . . . . . . . . . .288
19-14 Interrupt Status Register 3 (INT3). . . . . . . . . . . . . . . . . . . . . .289
19-15 Wait Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .291
19-16 Wait Recovery from Interrupt or Break . . . . . . . . . . . . . . . . . . 291
19-17 Wait Recovery from Internal Reset. . . . . . . . . . . . . . . . . . . . . 292
19-18 Stop Mode Entry Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
19-19 Stop Mode Recovery from Interrupt or Break . . . . . . . . . . . . . 293
19-20 SIM Break Status Register (SBSR) . . . . . . . . . . . . . . . . . . . . 294
19-21 SIM Reset Status Register (SRSR) . . . . . . . . . . . . . . . . . . . . 295
19-22 SIM Break Flag Control Register (SBFCR) . . . . . . . . . . . . . . 296
20-1

SPI I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

20-2

SPI Module Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . 300

20-3

Full-Duplex Master-Slave Connections . . . . . . . . . . . . . . . . . 301

20-4

Transmission Format (CPHA = 0) . . . . . . . . . . . . . . . . . . . . . 305

20-5

CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

20-6

Transmission Format (CPHA = 1) . . . . . . . . . . . . . . . . . . . . . 306

20-7

Transmission Start Delay (Master) . . . . . . . . . . . . . . . . . . . . . 308

20-8

.SPRF/SPTE CPU Interrupt Timing . . . . . . . . . . . . . . . . . . . . 309

20-9

Missed Read of Overflow Condition . . . . . . . . . . . . . . . . . . . . 311

20-10 Clearing SPRF When OVRF Interrupt Is Not Enabled . . . . . . 312
20-11 SPI Interrupt Request Generation . . . . . . . . . . . . . . . . . . . . . 315
20-12 CPHA/SS Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320
20-13 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . 322
20-14 SPI Status and Control Register (SPSCR) . . . . . . . . . . . . . . .325
20-15 SPI Data Register (SPDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
21-1

Timebase Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

21-2

Timebase Control Register (TBCR) . . . . . . . . . . . . . . . . . . . . 331

22-1

TIM Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338

List of Figures

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

List of Figures

22-2

TIM I/O Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . 339

22-3

PWM Period and Pulse Width . . . . . . . . . . . . . . . . . . . . . . . . 343

22-4

TIM Status and Control Register (TSC) . . . . . . . . . . . . . . . . . 349

22-5

TIM Counter Registers High (TCNTH) . . . . . . . . . . . . . . . . . . 352

22-6

TIM Counter Registers Low (TCNTL) . . . . . . . . . . . . . . . . . . . 352

22-7

TIM Counter Modulo Register High (TMODH) . . . . . . . . . . . .353

22-8

TIM Counter Modulo Register Low (TMODL) . . . . . . . . . . . . . 353

22-9

TIM Counter Register High (TCNTH) . . . . . . . . . . . . . . . . . . . 354

22-10 TIM Counter Register Low (TCNTL). . . . . . . . . . . . . . . . . . . . 354
22-11 TIM Channel 0 Status and Control Register (TSC0) . . . . . . . 355
22-12 TIM Channel 1 Status and Control Register (TSC1) . . . . . . . 355
22-13 CHxMAX Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
22-14 TIM Channel 0 Register High (TCH0H) . . . . . . . . . . . . . . . . . 360
22-15 TIM Channel 0 Register Low (TCH0L) . . . . . . . . . . . . . . . . . . 360
22-16 TIM Channel 1 Register High (TCH1H) . . . . . . . . . . . . . . . . . 360
22-17 TIM Channel 1 Register Low (TCH1L) . . . . . . . . . . . . . . . . . . 360
23-1

Typical High-Side Driver Characteristics �
Port PTA3�PTA0 (V

= 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 370

23-2

Typical High-Side Driver Characteristics �
Port PTA3�PTA0 (V

= 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 370

23-3

Typical High-Side Driver Characteristics �
Port PTC1�PTC0 (V

= 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 371

23-4

Typical High-Side Driver Characteristics �
Port PTC1�PTC0 (V

= 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 371

23-5

Typical High-Side Driver Characteristics � Ports PTB5�PTB0,
PTD6�PTD0, and PTE1�PTE0 (V

= 5.5 Vdc) . . . . . . . . . . 372

23-6

Typical High-Side Driver Characteristics � Ports PTB5�PTB0,
PTD6�PTD0, and PTE1�PTE0 (V

= 2.7 Vdc) . . . . . . . . . . 372

23-7

Typical Low-Side Driver Characteristics �
Port PTA3�PTA0 (V

= 5.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 373

23-8

Typical Low-Side Driver Characteristics �
Port PTA3�PTA0 (V

= 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 373

23-9

Typical Low-Side Driver Characteristics �
Port PTC1�PTC0 (V

= 4.5 Vdc) . . . . . . . . . . . . . . . . . . . . . 374

23-10 Typical Low-Side Driver Characteristics �

Port PTC1�PTC0 (V

= 2.7 Vdc) . . . . . . . . . . . . . . . . . . . . . 374

23-11 Typical Low-Side Driver Characteristics � Ports PTB5�PTB0,

PTD6�PTD0, and PTE1�PTE0 (V

= 5.5 Vdc) . . . . . . . . . . 375

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

General Description

Technical Data -- MC68HC908GR8

Section 1. General Description

1.1 Contents

1.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

1.4

MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

1.5

Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

1.6

Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

1.2 Introduction

The MC68HC908GR8 is a member of the low-cost, high-performance
M68HC08 Family of 8-bit microcontroller units (MCUs). All MCUs in the
family use the enhanced M68HC08 central processor unit (CPU08) and
are available with a variety of modules, memory sizes and types, and
package types.

This document also describes the MC68HC908GR4. The
MC68HC908GR4 is a device identical to the MC68HC908GR8 except
that it has less Flash memory. Only when there are differences from the
MC68HC908GR8 is the MC68HC908GR4 specifically mentioned in the
text.

General Description

Technical Data

MC68HC908GR8 -- Rev 4.0

General Description

MOTOROLA

1.3 Features

For convenience, features have been organized to reflect:

�

Standard features of the MC68HC908GR8

�

Features of the CPU08

1.3.1 Standard Features of the MC68HC908GR8

�

High-performance M68HC08 architecture optimized for C-
compilers

�

Fully upward-compatible object code with M6805, M146805, and
M68HC05 Families

�

8-MHz internal bus frequency

�

FLASH program memory security

(1)

�

On-chip programming firmware for use with host personal
computer which does not require high voltage for entry

�

In-system programming

�

System protection features:

�

Optional computer operating properly (COP) reset

�

Low-voltage detection with optional reset and selectable trip
points for 3.0 V and 5.0 V operation

�

Illegal opcode detection with reset

�

Illegal address detection with reset

�

Low-power design; fully static with stop and wait modes

�

Standard low-power modes of operation:

�

Wait mode

�

Stop mode

�

Master reset pin and power-on reset (POR)

1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or
copying the FLASH difficult for unauthorized users.

General Description

Features

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

General Description

�

7680 bytes of on-chip FLASH memory on the MC68HC908GR8
and 4096 bytes of on-chip FLASH memory on the
MC68HC908GR4 with in-circuit programming capabilities of
FLASH program memory

�

384 bytes of on-chip random-access memory (RAM)

�

Serial peripheral interface module (SPI)

�

Serial communications interface module (SCI)

�

One 16-bit, 2-channel timer (TIM1) and one 16-bit, 1-channel
timer (TIM2) interface modules with selectable input capture,
output compare, and PWM capability on each channel

�

6-channel, 8-bit successive approximation analog-to-digital
converter (ADC)

�

BREAK module (BRK) to allow single breakpoint setting during in-
circuit debugging

�

Internal pullups on IRQ and RST to reduce customer system cost

�

Clock generator module with on-chip 32-kHz crystal compatible
PLL (phase-lock loop)

�

Up to 21 general-purpose input/output (I/O) pins, including:

�

19 shared-function I/O pins

�

Up to two dedicated I/O pins, depending on package choice

�

Selectable pullups on inputs only on ports A, C, and D. Selection
is on an individual port bit basis. During output mode, pullups are
disengaged.

�

High current 10-mA sink/10-mA source capability on all port pins

�

Higher current 15-mA sink/source capability on PTC0�PTC1

�

Timebase module with clock prescaler circuitry for eight user
selectable periodic real-time interrupts with optional active clock
source during stop mode for periodic wakeup from stop using an
external 32-kHz crystal

�

Oscillator stop mode enable bit (OSCSTOPENB) in the CONFIG
register to allow user selection of having the oscillator enabled or
disabled during stop mode

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SINGLE BRKPT BREAK

MODULE

CLOCK GENERATOR MODULE

24 INTR SYSTEM INTEGRATION

MODULE

PROGR. TIMEBASE

MODULE

MONITOR MODULE

SERIAL PERIPHERAL

1-CHANNEL TIMER INTERFACE

MODULE 2

DUAL V. LOW-VOLTAGE INHIBIT

MODULE

4-BIT KEYBOARD

ARITHMETIC/LOGIC

UNIT (ALU)

CPU

REGISTERS

M68HC08 CPU

CONTROL AND STATUS REGISTERS -- 64 BYTES

MC68HC908GR8 USER FLASH -- 7680 BYTES

USER RAM -- 384 BYTES

MONITOR ROM -- 310 BYTES

USER FLASH VECTOR SPACE -- 36 BYTES

SINGLE EXTERNAL IRQ

MODULE

DRE

INTERNAL BUS

OSC1
OSC2

CGMXFC

* RST

* IRQ

INTERFACE MODULE

INTERRUPT MODULE

COMPUTER OPERATING

PROPERLY MODULE

PTA3/KBD3�PTA0/KBD0

DDAD /

REFH

8-BIT ANALOG-TO-DIGITAL

CONVERTER MODULE

PTD6/T2CH0

PTD5/T1CH1

PTD4/T1CH0

PTD3/SPSCK

PTD2/MOSI

PTD1/MISO

PTD0/SS

PTE1/RxD
PTE0/TxD

SSAD

/ V

REFL

2-CHANNEL TIMER INTERFACE

MODULE 1

32-kHz OSCILLATOR

PHASE-LOCKED LOOP

SERIAL COMMUNICATIONS

INTERFACE MODULE

DATA BUS SWITCH

MODULE

MEMORY MAP

MODULE

MASK OPTION REGISTER1

MODULE

SECURITY

MODULE

POWER

SSA

DDA

Ports are software configurable with pullup device if input port.
Higher current drive port pins
* Pin contains integrated pullup device

MONITOR MODE ENTRY

MODULE

DRB

PTB5/AD5�PTB0/AD0

PTC1�PTC0

POWER-ON RESET

MODULE

FLASH PROGRAMMING (BURN-IN) ROM -- 544 BYTES

MASK OPTION REGISTER2

MODULE

MC68HC908GR4 USER FLASH -- 4096BYTES

General Description

Pin Functions

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

General Description

Figure 1-3. DIP And SOIC Pin Assignments

1.6 Pin Functions

Descriptions of the pin functions are provided here.

1.6.1 Power Supply Pins (V

and V

)

and V

are the power supply and ground pins. The MCU operates

from a single power supply.

Fast signal transitions on MCU pins place high, short-duration current
demands on the power supply. To prevent noise problems, take special
care to provide power supply bypassing at the MCU as

Figure 1-4

shows. Place the C1 bypass capacitor as close to the MCU as possible.
Use a high-frequency-response ceramic capacitor for C1. C2 is an
optional bulk current bypass capacitor for use in applications that require
the port pins to source high current levels.

CGMXFC

OSC2

OSC1

RST

PTE0/TxD

PTE1/RxD

IRQ

PTD0/SS

PTD1/MISO

PTD2/MOSI

PTD3/SPSCK

PTD4/T1CH0

SSA

DDA

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

SSAD

REFL

DDAD

REFH

PTB3/AD3

PTB2/AD2

PTB1/AD1

PTB0/AD0

PTD6/T2CH0

PTD5/T1CH1

NOTE: Ports PTB4, PTB5, PTC0, and PTC1 are available only with the QFP.

General Description

Technical Data

MC68HC908GR8 -- Rev 4.0

General Description

MOTOROLA

Figure 1-4. Power Supply Bypassing

1.6.2 Oscillator Pins (OSC1 and OSC2)

The OSC1 and OSC2 pins are the connections for the on-chip oscillator
circuit. See

Clock Generator Module (CGMC)

1.6.3 External Reset Pin (RST)

A logic 0 on the RST pin forces the MCU to a known startup state. RST
is bidirectional, allowing a reset of the entire system. It is driven low when
any internal reset source is asserted. This pin contains an internal pullup
resistor that is always activated, even when the reset pin is pulled low.
See

Resets and Interrupts

1.6.4 External Interrupt Pin (IRQ)

IRQ is an asynchronous external interrupt pin. This pin contains an
internal pullup resistor that is always activated, even when the reset pin
is pulled low. See

External Interrupt (IRQ)

1.6.5 CGM Power Supply Pins (V

DDA

and V

SSA

)

DDA

and V

SSA

are the power supply pins for the analog portion of the

clock generator module (CGM). Decoupling of these pins should be as
per the digital supply. See

Clock Generator Module (CGMC)

MCU

0.1

�

NOTE: Component values shown represent typical applications.

General Description

Pin Functions

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

General Description

1.6.6 External Filter Capacitor Pin (CGMXFC)

CGMXFC is an external filter capacitor connection for the CGM. See

Clock Generator Module (CGMC)

1.6.7 Analog Power Supply/Reference Pins (V

DDAD

REFH

and V

SSAD

REFL

)

DDAD

and V

SSAD

are the power supply pins for the analog-to-digital

converter. Decoupling of these pins should be as per the digital supply.

NOTE:

REFH

is the high reference supply for the ADC. The V

REFH

signal is

internally connected with V

DDAD

and have the same potential as V

DDAD.

DDAD

should be tied to the same potential as V

via separate traces.

REFL

is the low reference supply for the ADC. The V

REFL

pin is

internally connected with V

SSAD

and has the same potential as V

SSAD.

SSAD

should be tied to the same potential as V

via separate traces.

See

Analog-to-Digital Converter (ADC)

1.6.8 Port A Input/Output (I/O) Pins (PTA3/KBD3�PTA0/KBD0)

PTA3�PTA0 are special-function, bidirectional I/O port pins. Any or all of
the port A pins can be programmed to serve as keyboard interrupt pins.
See

Input/Output Ports (I/O)

and

External Interrupt (IRQ)

These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.

When the port pins are configured for special-function mode (KBI),
pullups will be automatically engaged. As long as the port pins are in
special-function mode, the pullups will always be on.

1.6.9 Port B I/O Pins (PTB5/AD5�PTB0/AD0)

PTB5�PTB0 are special-function, bidirectional I/O port pins that can also
be used for analog-to-digital converter (ADC) inputs. See

Input/Output

Ports (I/O)

and

Analog-to-Digital Converter (ADC)

There are no pullups associated with this port.

General Description

Technical Data

MC68HC908GR8 -- Rev 4.0

General Description

MOTOROLA

1.6.10 Port C I/O Pins (PTC1�PTC0)

PTC1�PTC0 are general-purpose, bidirectional I/O port pins. See

Input/Output Ports (I/O)

. PTC0 and PTC1 are only available on 32-pin

QFP packages.

These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.

1.6.11 Port D I/O Pins (PTD6/T2CH0�PTD0/SS)

PTD6�PTD0 are special-function, bidirectional I/O port pins.
PTD3�PTD0 can be programmed to be serial peripheral interface (SPI)
pins, while PTD6�PTD4 can be individually programmed to be timer
interface module (TIM1 and TIM2) pins. See

Timer Interface Module

(TIM)

Serial Peripheral Interface (SPI)

, and

Input/Output Ports (I/O)

These port pins also have selectable pullups when configured for input
mode. The pullups are disengaged when configured for output mode.
The pullups are selectable on an individual port bit basis.

When the port pins are configured for special-function mode (SPI, TIM1,
TIM2), pullups can be selectable on an individual port pin basis.

1.6.12 Port E I/O Pins (PTE1/RxD�PTE0/TxD)

PTE1�PTE0 are special-function, bidirectional I/O port pins. These pins
can also be programmed to be serial communications interface (SCI)
pins. See

Serial Communications Interface (SCI)

and

Input/Output Ports

(I/O)

NOTE:

Any unused inputs and I/O ports should be tied to an appropriate logic
level (either V

or V

). Although the I/O ports of the MC68HC908GR8

do not require termination, termination is recommended to reduce the
possibility of electro-static discharge damage.

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Memory Map

Technical Data -- MC68HC908GR8

Section 2. Memory Map

2.1 Contents

2.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

2.3

Unimplemented Memory Locations . . . . . . . . . . . . . . . . . . . . . . 35

2.4

Reserved Memory Locations . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.5

Input/Output (I/O) Section. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2.2 Introduction

The CPU08 can address 64K bytes of memory space. The memory
map, shown in

Figure 2-1

, includes:

�

8K bytes of FLASH memory, 7680 bytes of user space on the
MC68HC908GR8 or
4K bytes of FLASH memory, 4096 bytes of user space on the
MC68HC908GR4

�

384 bytes of random-access memory (RAM)

�

36 bytes of user-defined vectors

�

310 bytes of monitor routines in read-only memory (ROM)

�

544 bytes of integrated FLASH burn-in routines in ROM

2.3 Unimplemented Memory Locations

Accessing an unimplemented location can cause an illegal address
reset if illegal address resets are enabled. In the memory map (

Figure 2-

) and in register figures in this document, unimplemented locations are

shaded.

Memory Map

Technical Data

MC68HC908GR8 -- Rev 4.0

Memory Map

MOTOROLA

2.4 Reserved Memory Locations

Accessing a reserved location can have unpredictable effects on MCU
operation. In the

Figure 2-1

and in register figures in this document,

reserved locations are marked with the word Reserved or with the letter
R.

2.5 Input/Output (I/O) Section

Most of the control, status, and data registers are in the zero page area
of $0000�$003F. Additional I/O registers have these addresses:

�

$FE00; SIM break status register, SBSR

�

$FE01; SIM reset status register, SRSR

�

$FE03; SIM break flag control register, SBFCR

�

$FE09; interrupt status register 1, INT1

�

$FE0A; interrupt status register 2, INT2

�

$FE0B; interrupt status register 3, INT3

�

$FE07; reserved FLASH test control register, FLTCR

�

$FE08; FLASH control register, FLCR

�

$FE09; break address register high, BRKH

�

$FE0A; break address register low, BRKL

�

$FE0B; break status and control register, BRKSCR

�

$FE0C; LVI status register, LVISR

�

$FF7E; FLASH block protect register, FLBPR

Data registers are shown in

Figure 2-2

, and

Table 2-1

is a list of vector

locations.

Memory Map

Input/Output (I/O) Section

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Memory Map

Addr.

Register Name

Bit 7

Bit 0

$0000

Port A Data Register

(PTA)

Read:

PTA3

PTA2

PTA1

PTA0

Write:

Reset:

Unaffected by reset

$0001

Port B Data Register

(PTB)

Read:

PTB5

PTB4

PTB3

PTB2

PTB1

PTB0

Write:

Reset:

Unaffected by reset

$0002

Port C Data Register

(PTC)

Read:

PTC1

PTC0

Write:

Reset:

Unaffected by reset

$0003

Port D Data Register

(PTD)

Read:

PTD6

PTD5

PTD4

PTD3

PTD2

PTD1

PTD0

Write:

Reset:

Unaffected by reset

$0004

Data Direction Register A

(DDRA)

Read:

DDRA3

DDRA2

DDRA1

DDRA0

Write:

Reset:

$0005

Data Direction Register B

(DDRB)

Read:

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Write:

Reset:

$0006

Data Direction Register C

(DDRC)

Read:

DDRC1

DDRC0

Write:

Reset:

$0007

Data Direction Register D

(DDRD)

Read:

DDRD6

DDRD5

DDRD4

DDRD3

DDRD2

DDRD1

DDRD0

Write:

Reset:

$0008

Port E Data Register

(PTE)

Read:

PTE1

PTE0

Write:

Reset:

Unaffected by reset

$0009

Unimplemented

Read:

Write:

Reset:

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)

Memory Map

Technical Data

MC68HC908GR8 -- Rev 4.0

Memory Map

MOTOROLA

$000A

Unimplemented

Read:

Write:

Reset:

$000B

Unimplemented

Read:

Write:

Reset:

$000C

Data Direction Register E

(DDRE)

Read:

DDRE1

DDRE0

Write:

Reset:

$000D

Port A Input Pullup Enable

Read:

PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0

Write:

Reset:

$000E

Port C Input Pullup Enable

Read:

PTCPUE1 PTCPUE0

Write:

Reset:

$000F

Port D Input Pullup Enable

Read:

PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0

Write:

Reset:

$0010

SPI Control Register

(SPCR)

Read:

SPRIE

DMAS

SPMSTR

CPOL

CPHA

SPWOM

SPE

SPTIE

Write:

Reset:

$0011

SPI Status and Control

Read:

SPRF

ERRIE

OVRF

MODF

SPTE

MODFEN

SPR1

SPR0

Write:

Reset:

$0012

SPI Data Register

(SPDR)

Read:

Write:

Reset:

Unaffected by reset

$0013

SCI Control Register 1

(SCC1)

Read:

LOOPS

ENSCI

TXINV

WAKE

ILTY

PEN

PTY

Write:

Reset:

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)

Memory Map

Input/Output (I/O) Section

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Memory Map

$0014

SCI Control Register 2

(SCC2)

Read:

SCTIE

TCIE

SCRIE

ILIE

RWU

SBK

Write:

Reset:

$0015

SCI Control Register 3

(SCC3)

Read:

DMARE

DMATE

ORIE

NEIE

FEIE

PEIE

Write:

Reset:

$0016

SCI Status Register 1

(SCS1)

Read:

SCTE

SCRF

IDLE

Write:

Reset:

$0017

SCI Status Register 2

(SCS2)

Read:

BKF

RPF

Write:

Reset:

$0018

SCI Data Register

(SCDR)

Read:

Write:

Reset:

Unaffected by reset

$0019

SCI Baud Rate Register

(SCBR)

Read:

SCP1

SCP0

SCR2

SCR1

SCR0

Write:

Reset:

$001A

Keyboard Status

and Control Register

(INTKBSCR)

Read:

KEYF

IMASKK

MODEK

Write:

ACKK

Reset:

$001B

Keyboard Interrupt Enable

Read:

KBIE3

KBIE2

KBIE1

KBIE0

Write:

Reset:

$001C

Time Base Module Control

Read:

TBIF

TBR2

TBR1

TBR0

TBIE

TBON

Write:

TACK

Reset:

$001D

IRQ Status and Control

Read:

IRQF1

IMASK1

MODE1

Write:

ACK1

Reset:

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 3 of 8)

Memory Map

Technical Data

MC68HC908GR8 -- Rev 4.0

Memory Map

MOTOROLA

$001E

Configuration Register 2

(CONFIG2)

Read:

OSC-

STOPENB

SCIBD-

SRC

Write:

Reset:

$001F

Configuration Register 1

(CONFIG1)

Read:

COPRS

LVISTOP LVIRSTD LVIPWRD LVI5OR3

SSREC

STOP

COPD

Write:

Reset:

$0020

Timer 1 Status and Control

Read:

TOF

TOIE

TSTOP

PS2

PS1

PS0

Write:

TRST

Reset:

$0021

Timer 1 Counter Register

High (T1CNTH)

Read:

Bit 15

Bit 8

Write:

Reset:

$0022

Timer 1 Counter Register

Low (T1CNTL)

Read:

Bit 7

Bit 0

Write:

Reset:

$0023

Timer 1 Counter Modulo

Read:

Bit 15

Bit 8

Write:

Reset:

$0024

Timer 1 Counter Modulo

Read:

Bit 7

Bit 0

Write:

Reset:

$0025

Timer 1 Channel 0 Status

and Control Register

(T1SC0)

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

$0026

Timer 1 Channel 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

$0027

Timer 1 Channel 0

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

One-time writeable register after each reset, except LVI5OR3 bit. LVI5OR3 bit is only reset via POR (power-on reset).

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 4 of 8)

Memory Map

Input/Output (I/O) Section

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Memory Map

$0028

Timer 1 Channel 1 Status

and Control Register

(T1SC1)

Read:

CH1F

CH1IE

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

Write:

Reset:

$0029

Timer 1 Channel 1

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

$002A

Timer 1 Channel 1

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

$002B

Timer 2 Status and Control

Read:

TOF

TOIE

TSTOP

PS2

PS1

PS0

Write:

TRST

Reset:

$002C

Timer 2 Counter Register

High (T2CNTH)

Read:

Bit 15

Bit 8

Write:

Reset:

$002D

Timer 2 Counter Register

Low (T2CNTL)

Read:

Bit 7

Bit 0

Write:

Reset:

$002E

Timer 2 Counter Modulo

Read:

Bit 15

Bit 8

Write:

Reset:

$002F

Timer 2 Counter Modulo

Read:

Bit 7

Bit 0

Write:

Reset:

$0030

Timer 2 Channel 0 Status

and Control Register

(T2SC0)

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

$0031

Timer 2 Channel 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 5 of 8)

Memory Map

Technical Data

MC68HC908GR8 -- Rev 4.0

Memory Map

MOTOROLA

$0032

Timer 2 Channel 0

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

$0033

Unimplemented

Read:

Write:

Reset:

$0034

Unimplemented

Read:

Write:

Reset:

Indeterminate after reset

$0035

Unimplemented

Read:

Write:

Reset:

Indeterminate after reset

$0036

PLL Control Register

(PCTL)

Read:

PLLIE

PLLF

PLLON

BCS

PRE1

PRE0

VPR1

VPR0

Write:

Reset:

$0037

PLL Bandwidth Control

Read:

AUTO

LOCK

ACQ

Write:

Reset:

$0038

PLL Multiplier Select High

Read:

MUL11

MUL10

MUL9

MUL8

Write:

Reset:

$0039

PLL Multiplier Select Low

Read:

MUL7

MUL6

MUL5

MUL4

MUL3

MUL2

MUL1

MUL0

Write:

Reset:

$003A

PLL VCO Select Range

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

$003B

PLL Reference Divider

Select Register (PMDS)

Read:

RDS3

RDS2

RDS1

RDS0

Write:

Reset:

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 6 of 8)

Memory Map

Input/Output (I/O) Section

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Memory Map

$003C

Analog-to-Digital Status

and Control Register

(ADSCR)

Read:

COCO

AIEN

ADCO

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

Write:

Reset:

$003D

Analog-to-Digital Data

Read:

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

Write:

Reset:

Indeterminate after reset

$003E

Analog-to-Digital Input

Clock Register (ADCLK)

Read:

ADIV2

ADIV1

ADIV0

ADICLK

Write:

Reset:

$003F

Unimplemented

Read:

Write:

Reset:

$FE00

SIM Break Status Register

(SBSR)

Read:

SBSW

Write:

NOTE

Reset:

Note: Writing a logic 0 clears SBSW.

$FE01

SIM Reset Status Register

(SRSR)

Read:

POR

COP

ILOP

ILAD

MODRST

LVI

Write:

POR:

$FE02

Unimplemented

Read:

Write:

Reset:

$FE03

SIM Break Flag Control

Read:

BCFE

Write:

Reset:

$FE09

Interrupt Status Register 1

(INT1)

Read:

IF6

IF5

IF4

IF3

IF2

IF1

Write:

Reset:

$FE0A

Interrupt Status Register 2

(INT2)

Read:

IF14

IF13

IF12

IF11

IF10

IF9

IF8

IF7

Write:

Reset:

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 7 of 8)

Memory Map

Technical Data

MC68HC908GR8 -- Rev 4.0

Memory Map

MOTOROLA

$FE0B

Interrupt Status Register 3

(INT3)

Read:

IF16

IF15

Write:

Reset:

$FE07

FLASH Test Control

Read:

Write:

Reset:

$FE08

FLASH Control Register

(FLCR)

Read:

HVEN

MASS

ERASE

PGM

Write:

Reset:

$FE09

Break Address Register

High (BRKH)

Read:

Bit 15

Bit 8

Write:

Reset:

$FE0A

Break Address Register

Low (BRKL)

Read:

Bit 7

Bit 0

Write:

Reset:

$FE0B

Break Status and Control

Read:

BRKE

BRKA

Write:

Reset:

$FE0C

LVI Status Register

(LVISR)

Read: LVIOUT

Write:

Reset:

$FF7E

FLASH Block Protect

Read:

BPR7

BPR6

BPR5

BPR4

BPR3

BPR2

BPR1

BPR0

Write:

Reset:

$FFFF

COP Control Register

(COPCTL)

Read:

Low byte of reset vector

Write:

Writing clears COP counter (any value)

Reset:

Unaffected by reset

Non-volatile FLASH register

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

R = Reserved

U = Unaffected

Figure 2-2. Control, Status, and Data Registers (Sheet 8 of 8)

Memory Map

Input/Output (I/O) Section

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Memory Map

Table 2-1. Vector Addresses

Vector Priority

Vector

Address

Vector

Lowest

IF16

$FFDC

Timebase Vector (High)

$FFDD

Timebase Vector (Low)

IF15

$FFDE

ADC Conversion Complete Vector (High)

$FFDF

ADC Conversion Complete Vector (Low)

IF14

$FFE0

Keyboard Vector (High)

$FFE1

Keyboard Vector (Low)

IF13

$FFE2

SCI Transmit Vector (High)

$FFE3

SCI Transmit Vector (Low)

IF12

$FFE4

SCI Receive Vector (High)

$FFE5

SCI Receive Vector (Low)

IF11

$FFE6

SCI Error Vector (High)

$FFE7

SCI Error Vector (Low)

IF10

$FFE8

SPI Transmit Vector (High)

$FFE9

SPI Transmit Vector (Low)

IF9

$FFEA

SPI Receive Vector (High)

$FFEB

SPI Receive Vector (Low)

IF8

$FFEC

TIM2 Overflow Vector (High)

$FFED

TIM2 Overflow Vector (Low)

IF7

$FFEE

Reserved

$FFEF

Reserved

IF6

$FFF0

TIM2 Channel 0 Vector (High)

$FFF1

TIM2 Channel 0 Vector (Low)

IF5

$FFF2

TIM1 Overflow Vector (High)

$FFF3

TIM1 Overflow Vector (Low)

IF4

$FFF4

TIM1 Channel 1 Vector (High)

$FFF5

TIM1 Channel 1 Vector (Low)

IF3

$FFF6

TIM1 Channel 0 Vector (High)

$FFF7

TIM1 Channel 0 Vector (Low)

IF2

$FFF8

PLL Vector (High)

$FFF9

PLL Vector (Low)

IF1

$FFFA

IRQ Vector (High)

$FFFB

IRQ Vector (Low)

$FFFC

SWI Vector (High)

$FFFD

SWI Vector (Low)

$FFFE

Reset Vector (High)

Highest

$FFFF

Reset Vector (Low)

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

Technical Data -- MC68HC908GR8

Section 3. Low Power Modes

3.1 Contents

3.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

3.3

Analog-to-Digital Converter (ADC) . . . . . . . . . . . . . . . . . . . . . . 50

3.4

Break Module (BRK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.5

Central Processor Unit (CPU). . . . . . . . . . . . . . . . . . . . . . . . . . 51

3.6

Clock Generator Module (CGM) . . . . . . . . . . . . . . . . . . . . . . . . 52

3.7

Computer Operating Properly Module (COP). . . . . . . . . . . . . . 52

3.8

External Interrupt Module (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . 53

3.9

Keyboard Interrupt Module (KBI) . . . . . . . . . . . . . . . . . . . . . . . 53

3.10

Low-Voltage Inhibit Module (LVI) . . . . . . . . . . . . . . . . . . . . . . . 54

3.11

Serial Communications Interface Module (SCI) . . . . . . . . . . . . 54

3.12

Serial Peripheral Interface Module (SPI) . . . . . . . . . . . . . . . . . 55

3.13

Timer Interface Module (TIM1 and TIM2) . . . . . . . . . . . . . . . . . 55

3.14

Timebase Module (TBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3.15

Exiting Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

3.16

Exiting Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.2 Introduction

The MCU may enter two low-power modes: wait mode and stop mode.
They are common to all HC08 MCUs and are entered through instruction
execution. This section describes how each module acts in the low-
power modes.

Low Power Modes

Technical Data

MC68HC908GR8 -- Rev 4.0

Low Power Modes

MOTOROLA

3.2.1 Wait Mode

The WAIT instruction puts the MCU in a low-power standby mode in
which the CPU clock is disabled but the bus clock continues to run.
Power consumption can be further reduced by disabling the LVI module
and/or the timebase module through bits in the CONFIG register. (See

Configuration Register (CONFIG)

3.2.2 Stop Mode

Stop mode is entered when a STOP instruction is executed. The CPU
clock is disabled and the bus clock is disabled if the OSCSTOPENB bit
in the CONFIG register is at a logic 0. (See

Configuration Register

(CONFIG)

3.3 Analog-to-Digital Converter (ADC)

3.3.1 Wait Mode

The ADC continues normal operation during wait mode. Any enabled
CPU interrupt request from the ADC can bring the MCU out of wait
mode. If the ADC is not required to bring the MCU out of wait mode,
power down the ADC by setting ADCH4�ADCH0 bits in the ADC status
and control register before executing the WAIT instruction.

3.3.2 Stop Mode

The ADC module is inactive after the execution of a STOP instruction.
Any pending conversion is aborted. ADC conversions resume when the
MCU exits stop mode after an external interrupt. Allow one conversion
cycle to stabilize the analog circuitry.

Low Power Modes

Break Module (BRK)

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

3.4 Break Module (BRK)

3.4.1 Wait Mode

If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if the BW
bit in the break status register is set.

3.4.2 Stop Mode

The break module is inactive in stop mode. A break interrupt causes exit
from stop mode and sets the BW bit in the break status register. The
STOP instruction does not affect break module register states.

3.5 Central Processor Unit (CPU)

3.5.1 Wait Mode

The WAIT instruction:

�

Clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from wait mode by interrupt, the I bit
remains clear. After exit by reset, the I bit is set.

�

Disables the CPU clock

3.5.2 Stop Mode

The STOP instruction:

�

Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.

�

Disables the CPU clock

After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.

Low Power Modes

Technical Data

MC68HC908GR8 -- Rev 4.0

Low Power Modes

MOTOROLA

3.6 Clock Generator Module (CGM)

3.6.1 Wait Mode

The CGM remains active in wait mode. Before entering wait mode,
software can disengage and turn off the PLL by clearing the BCS and
PLLON bits in the PLL control register (PCTL). Less power-sensitive
applications can disengage the PLL without turning it off. Applications
that require the PLL to wake the MCU from wait mode also can deselect
the PLL output without turning off the PLL.

3.6.2 Stop Mode

If the OSCSTOPEN bit in the CONFIG register is cleared (default), then
the STOP instruction disables the CGM (oscillator and phase-locked
loop) and holds low all CGM outputs (CGMXCLK, CGMOUT, and
CGMINT).

If the STOP instruction is executed with the VCO clock, CGMVCLK,
divided by two driving CGMOUT, the PLL automatically clears the BCS
bit in the PLL control register (PCTL), thereby selecting the crystal clock,
CGMXCLK, divided by two as the source of CGMOUT. When the MCU
recovers from STOP, the crystal clock divided by two drives CGMOUT
and BCS remains clear.

If the OSCSTOPEN bit in the CONFIG register is set, then the phase
locked loop is shut off, but the oscillator will continue to operate in stop
mode.

3.7 Computer Operating Properly Module (COP)

3.7.1 Wait Mode

The COP remains active in wait mode. To prevent a COP reset during
wait mode, periodically clear the COP counter in a CPU interrupt routine
or a DMA service routine.

Low Power Modes

External Interrupt Module (IRQ)

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

3.7.2 Stop Mode

Stop mode turns off the CGMXCLK input to the COP and clears the COP
prescaler. Service the COP immediately before entering or after exiting
stop mode to ensure a full COP timeout period after entering or exiting
stop mode.

The STOP bit in the configuration register (CONFIG) enables the STOP
instruction. To prevent inadvertently turning off the COP with a STOP
instruction, disable the STOP instruction by clearing the STOP bit.

3.8 External Interrupt Module (IRQ)

3.8.1 Wait Mode

The IRQ module remains active in wait mode. Clearing the IMASK1 bit
in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of wait mode.

3.8.2 Stop Mode

The IRQ module remains active in stop mode. Clearing the IMASK1 bit
in the IRQ status and control register enables IRQ CPU interrupt
requests to bring the MCU out of stop mode.

3.9 Keyboard Interrupt Module (KBI)

3.9.1 Wait Mode

The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.

Low Power Modes

Serial Peripheral Interface Module (SPI)

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

3.11.2 Stop Mode

The SCI module is inactive in stop mode. The STOP instruction does not
affect SCI register states. SCI module operation resumes after the MCU
exits stop mode.

Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.

3.12 Serial Peripheral Interface Module (SPI)

3.12.1 Wait Mode

The SPI module remains active in wait mode. Any enabled CPU interrupt
request from the SPI module can bring the MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.

3.12.2 Stop Mode

The SPI module is inactive in stop mode. The STOP instruction does not
affect SPI register states. SPI operation resumes after an external
interrupt. If stop mode is exited by reset, any transfer in progress is
aborted, and the SPI is reset.

3.13 Timer Interface Module (TIM1 and TIM2)

3.13.1 Wait Mode

The TIM remains active in wait mode. Any enabled CPU interrupt
request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.

Low Power Modes

Technical Data

MC68HC908GR8 -- Rev 4.0

Low Power Modes

MOTOROLA

3.13.2 Stop Mode

The TIM is inactive in stop mode. The STOP instruction does not affect
register states or the state of the TIM counter. TIM operation resumes
when the MCU exits stop mode after an external interrupt.

3.14 Timebase Module (TBM)

3.14.1 Wait Mode

The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.

If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.

3.14.2 Stop Mode

The timebase module may remain active after execution of the STOP
instruction if the oscillator has been enabled to operate during stop mode
through the OSCSTOPEN bit in the CONFIG register. The timebase
module can be used in this mode to generate a periodic wakeup from
stop mode.

If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during stop mode. In stop mode, the
timebase register is not accessible by the CPU.

If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.

Low Power Modes

Exiting Wait Mode

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Low Power Modes

3.15 Exiting Wait Mode

These events restart the CPU clock and load the program counter with
the reset vector or with an interrupt vector:

�

External reset -- A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.

�

External interrupt -- A high-to-low transition on an external
interrupt pin (IRQ pin) loads the program counter with the contents
of locations: $FFFA and $FFFB; IRQ pin.

�

Break interrupt -- A break interrupt loads the program counter
with the contents of $FFFC and $FFFD.

�

Computer operating properly module (COP) reset -- A timeout of
the COP counter resets the MCU and loads the program counter
with the contents of $FFFE and $FFFF.

�

Low-voltage inhibit module (LVI) reset -- A power supply voltage
below the V

tripf

voltage resets the MCU and loads the program

counter with the contents of locations $FFFE and $FFFF.

�

Clock generator module (CGM) interrupt -- A CPU interrupt
request from the phase-locked loop (PLL) loads the program
counter with the contents of $FFF8 and $FFF9.

�

Keyboard module (KBI) interrupt -- A CPU interrupt request from
the KBI module loads the program counter with the contents of
$FFDE and $FFDF.

�

Timer 1 interface module (TIM1) interrupt -- A CPU interrupt
request from the TIM1 loads the program counter with the
contents of:

�

$FFF2 and $FFF3; TIM1 overflow

�

$FFF4 and $FFF5; TIM1 channel 1

�

$FFF6 and $FFF7; TIM1 channel 0

�

Timer 2 interface module (TIM2) interrupt -- A CPU interrupt
request from the TIM2 loads the program counter with the
contents of:

Low Power Modes

Technical Data

MC68HC908GR8 -- Rev 4.0

Low Power Modes

MOTOROLA

�

$FFEC and $FFED; TIM2 overflow

�

$FFF0 and $FFF1; TIM2 channel 0

�

Serial peripheral interface module (SPI) interrupt -- A CPU
interrupt request from the SPI loads the program counter with the
contents of:

�

$FFE8 and $FFE9; SPI transmitter

�

$FFEA and $FFEB; SPI receiver

�

Serial communications interface module (SCI) interrupt -- A CPU
interrupt request from the SCI loads the program counter with the
contents of:

�

$FFE2 and $FFE3; SCI transmitter

�

$FFE4 and $FFE5; SCI receiver

�

$FFE6 and $FFE7; SCI receiver error

�

Analog-to-digital converter module (ADC) interrupt -- A CPU
interrupt request from the ADC loads the program counter with the
contents of: $FFDE and $FFDF; ADC conversion complete.

�

Timebase module (TBM) interrupt -- A CPU interrupt request from
the TBM loads the program counter with the contents of: $FFDC
and $FFDD; TBM interrupt.

3.16 Exiting Stop Mode

These events restart the system clocks and load the program counter
with the reset vector or with an interrupt vector:

�

External reset -- A logic 0 on the RST pin resets the MCU and
loads the program counter with the contents of locations $FFFE
and $FFFF.

�

External interrupt -- A high-to-low transition on an external
interrupt pin loads the program counter with the contents of
locations:

�

$FFFA and $FFFB; IRQ pin

�

$FFDE and $FFDF; keyboard interrupt pins

Resets and Interrupts

Technical Data

MC68HC908GR8 -- Rev 4.0

Resets and Interrupts

MOTOROLA

4.3.3.3 Low-Voltage Inhibit Reset

A low-voltage inhibit (LVI) reset is an internal reset caused by a drop in
the power supply voltage to the LVI trip voltage, V

TRIPF

An LVI reset:

�

Holds the clocks to the CPU and modules inactive for an oscillator
stabilization delay of 4096 CGMXCLK cycles after the power
supply voltage rises to V

TRIPF

�

Drives the RST pin low for as long as V

is below V

TRIPF

and

during the oscillator stabilization delay

�

Releases the RST pin 32 CGMXCLK cycles after the oscillator
stabilization delay

�

Releases the CPU to begin the reset vector sequence
64 CGMXCLK cycles after the oscillator stabilization delay

�

Sets the LVI bit in the SIM reset status register

4.3.3.4 Illegal Opcode Reset

An illegal opcode reset is an internal reset caused by an opcode that is
not in the instruction set. An illegal opcode reset sets the ILOP bit in the
SIM reset status register.

If the stop enable bit, STOP, in the mask option register is a logic 0, the
STOP instruction causes an illegal opcode reset.

4.3.3.5 Illegal Address Reset

An illegal address reset is an internal reset caused by opcode fetch from
an unmapped address. An illegal address reset sets the ILAD bit in the
SIM reset status register.

A data fetch from an unmapped address does not generate a reset.

Resets and Interrupts

Resets

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Resets and Interrupts

4.3.4 SIM Reset Status Register

This read-only register contains flags to show reset sources. All flag bits
are automatically cleared following a read of the register. Reset service
can read the SIM reset status register to clear the register after power-
on reset and to determine the source of any subsequent reset.

The register is initialized on powerup as shown with the POR bit set and
all other bits cleared. During a POR or any other internal reset, the RST
pin is pulled low. After the pin is released, it will be sampled 32 XCLK
cycles later. If the pin is not above a V

at that time, then the PIN bit in

the SRSR may be set in addition to whatever other bits are set.

NOTE:

Only a read of the SIM reset status register clears all reset flags. After
multiple resets from different sources without reading the register,
multiple flags remain set.

POR -- Power-On Reset Flag

1 = Power-on reset since last read of SRSR
0 = Read of SRSR since last power-on reset

PIN -- External Reset Flag

1 = External reset via RST pin since last read of SRSR
0 = POR or read of SRSR since last external reset

COP -- Computer Operating Properly Reset Bit

1 = Last reset caused by timeout of COP counter
0 = POR or read of SRSR

Address:

$FE01

Bit 7

Bit 0

Read:

POR

COP

ILOP

ILAD

LVI

Write:

POR:

= Unimplemented

Figure 4-3. SIM Reset Status Register (SRSR)

Resets and Interrupts

Technical Data

MC68HC908GR8 -- Rev 4.0

Resets and Interrupts

MOTOROLA

4.4.2 Sources

The sources in

Table 4-1

can generate CPU interrupt requests.

Table 4-1. Interrupt Sources

Source

Flag

Mask

(1)

INT Register

Flag

Priority

(2)

Vector

Address

Reset

None

$FFFE

�

$FFFF

SWI instruction

None

$FFFC

�

$FFFD

IRQ pin

IRQF

IMASK1

IF1

$FFFA

�

$FFFB

CGM (PLL)

PLLF

PLLIE

IF2

$FFF8�$FFF9

TIM1 channel 0

CH0F

CH0IE

IF3

$FFF6�$FFF7

TIM1 channel 1

CH1F

CH1IE

IF4

$FFF4�$FFF5

TIM1 overflow

TOF

TOIE

IF5

$FFF2�$FFF3

TIM2 channel 0

CH0F

CH0IE

IF6

$FFF0�$FFF1

TIM2 overflow

TOF

TOIE

IF8

$FFEC�$FFED

SPI receiver full

SPRF

SPRIE

IF9

$FFEA�$FFEB

SPI overflow

OVRF

ERRIE

SPI mode fault

MODF

ERRIE

SPI transmitter empty

SPTE

SPTIE

IF10

$FFE8�$FFE9

SCI receiver overrun

ORIE

IF11

$FFE6�$FFE7

SCI noise fag

NEIE

SCI framing error

FEIE

SCI parity error

PEIE

SCI receiver full

SCRF

SCRIE

IF12

$FFE4�$FFE5

SCI input idle

IDLE

ILIE

SCI transmitter empty

SCTE

SCTIE

IF13

$FFE2�$FFE3

SCI transmission complete

TCIE

Keyboard pin

KEYF

IMASKK

IF14

$FFDE�$FFDF

ADC conversion complete

COCO

AIEN

IF15

$FFDE�$FFDF

Timebase

TBIF

TBIE

IF16

$FFDC�$FFDD

Note:

1. The I bit in the condition code register is a global mask for all interrupt sources except the SWI instruction.
2. 0 = highest priority

Resets and Interrupts

Interrupts

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Resets and Interrupts

4.4.2.1 SWI Instruction

The software interrupt instruction (SWI) causes a non-maskable
interrupt.

NOTE:

A software interrupt pushes PC onto the stack. An SWI does not push
PC � 1, as a hardware interrupt does.

4.4.2.2 Break Interrupt

The break module causes the CPU to execute an SWI instruction at a
software-programmable break point.

4.4.2.3 IRQ Pin

A logic 0 on the IRQ1 pin latches an external interrupt request.

4.4.2.4 CGM

The CGM can generate a CPU interrupt request every time the phase-
locked loop circuit (PLL) enters or leaves the locked state. When the
LOCK bit changes state, the PLL flag (PLLF) is set. The PLL interrupt
enable bit (PLLIE) enables PLLF CPU interrupt requests. LOCK is in the
PLL bandwidth control register. PLLF is in the PLL control register.

4.4.2.5 TIM1

TIM1 CPU interrupt sources:

�

TIM1 overflow flag (TOF) -- The TOF bit is set when the TIM1
counter value rolls over to $0000 after matching the value in the
TIM1 counter modulo registers. The TIM1 overflow interrupt
enable bit, TOIE, enables TIM1 overflow CPU interrupt requests.
TOF and TOIE are in the TIM1 status and control register.

�

TIM1 channel flags (CH1F�CH0F) -- The CHxF bit is set when an
input capture or output compare occurs on channel x. The channel
x interrupt enable bit, CHxIE, enables channel x TIM1 CPU
interrupt requests. CHxF and CHxIE are in the TIM1 channel x
status and control register.

Resets and Interrupts

Technical Data

MC68HC908GR8 -- Rev 4.0

Resets and Interrupts

MOTOROLA

4.4.2.6 TIM2

TIM2 CPU interrupt sources:

�

TIM2 overflow flag (TOF) -- The TOF bit is set when the TIM2
counter value rolls over to $0000 after matching the value in the
TIM2 counter modulo registers. The TIM2 overflow interrupt
enable bit, TOIE, enables TIM2 overflow CPU interrupt requests.
TOF and TOIE are in the TIM2 status and control register.

�

TIM2 channel flag (CH0F) -- The CH0F bit is set when an input
capture or output compare occurs on channel 0. The channel 0
interrupt enable bit, CH0IE, enables channel 0 TIM2 CPU interrupt
requests. CH0F and CH0IE are in the TIM2 channel 0 status and
control register.

4.4.2.7 SPI

SPI CPU interrupt sources:

�

SPI receiver full bit (SPRF) -- The SPRF bit is set every time a
byte transfers from the shift register to the receive data register.
The SPI receiver interrupt enable bit, SPRIE, enables SPRF CPU
interrupt requests. SPRF is in the SPI status and control register
and SPRIE is in the SPI control register.

�

SPI transmitter empty (SPTE) -- The SPTE bit is set every time a
byte transfers from the transmit data register to the shift register.
The SPI transmit interrupt enable bit, SPTIE, enables SPTE CPU
interrupt requests. SPTE is in the SPI status and control register
and SPTIE is in the SPI control register.

�

Mode fault bit (MODF) -- The MODF bit is set in a slave SPI if the
SS pin goes high during a transmission with the mode fault enable
bit (MODFEN) set. In a master SPI, the MODF bit is set if the SS
pin goes low at any time with the MODFEN bit set. The error
interrupt enable bit, ERRIE, enables MODF CPU interrupt
requests. MODF, MODFEN, and ERRIE are in the SPI status and
control register.

Resets and Interrupts

Interrupts

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Resets and Interrupts

�

Overflow bit (OVRF) -- The OVRF bit is set if software does not
read the byte in the receive data register before the next full byte
enters the shift register. The error interrupt enable bit, ERRIE,
enables OVRF CPU interrupt requests. OVRF and ERRIE are in
the SPI status and control register.

4.4.2.8 SCI

SCI CPU interrupt sources:

�

SCI transmitter empty bit (SCTE) -- SCTE is set when the SCI
data register transfers a character to the transmit shift register.
The SCI transmit interrupt enable bit, SCTIE, enables transmitter
CPU interrupt requests. SCTE is in SCI status register 1. SCTIE is
in SCI control register 2.

�

Transmission complete bit (TC) -- TC is set when the transmit
shift register and the SCI data register are empty and no break or
idle character has been generated. The transmission complete
interrupt enable bit, TCIE, enables transmitter CPU interrupt
requests. TC is in SCI status register 1. TCIE is in SCI control
register 2.

�

SCI receiver full bit (SCRF) -- SCRF is set when the receive shift
register transfers a character to the SCI data register. The SCI
receive interrupt enable bit, SCRIE, enables receiver CPU
interrupts. SCRF is in SCI status register 1. SCRIE is in SCI
control register 2.

�

Idle input bit (IDLE) -- IDLE is set when 10 or 11 consecutive logic
1s shift in from the RxD pin. The idle line interrupt enable bit, ILIE,
enables IDLE CPU interrupt requests. IDLE is in SCI status
register 1. ILIE is in SCI control register 2.

�

Receiver overrun bit (OR) -- OR is set when the receive shift
register shifts in a new character before the previous character
was read from the SCI data register. The overrun interrupt enable
bit, ORIE, enables OR to generate SCI error CPU interrupt
requests. OR is in SCI status register 1. ORIE is in SCI control
register 3.

Resets and Interrupts

Technical Data

MC68HC908GR8 -- Rev 4.0

Resets and Interrupts

MOTOROLA

�

Noise flag (NF) -- NF is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status
register 1. NEIE is in SCI control register 3.

�

Framing error bit (FE) -- FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.

�

Parity error bit (PE) -- PE is set when the SCI detects a parity error
in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.

4.4.2.9 KBD0�KBD4 Pins

A logic 0 on a keyboard interrupt pin latches an external interrupt
request.

4.4.2.10 ADC (Analog-to-Digital Converter)

When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not
used as a conversion complete flag when interrupts are enabled.

4.4.2.11 TBM (Timebase Module)

The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2�TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

Analog-to-Digital Converter (ADC)

Technical Data

MC68HC908GR8 -- Rev 4.0

Analog-to-Digital Converter (ADC)

MOTOROLA

5.4.2 Voltage Conversion

When the input voltage to the ADC equals V

REFH

, the ADC converts the

signal to $FF (full scale). If the input voltage equals V

REFL,

the ADC

converts it to $00. Input voltages between V

REFH

and V

REFL

are a

straight-line linear conversion. All other input voltages will result in $FF,
if greater than V

REFH

NOTE:

Inside the ADC module, the reference voltage, V

REFH

is connected to the

ADC analog power V

DDAD

; and V

REFL

is connected to the ADC analog

ground V

DDAD

. Therefore, the ADC input voltage should not exceed the

analog supply voltages

For operation, V

DDAD

should be tied to the same potential as V

via

separate traces

5.4.3 Conversion Time

Conversion starts after a write to the ADSCR. One conversion will take
between 16 and 17 ADC clock cycles. The ADIVx and ADICLK bits
should be set to provide a 1 MHz ADC clock frequency.

5.4.4 Conversion

In continuous conversion mode, the ADC data register will be filled with
new data after each conversion. Data from the previous conversion will
be overwritten whether that data has been read or not. Conversions will
continue until the ADCO bit is cleared. The COCO/IDMAS bit is set after
the first conversion and will stay set until the next write of the ADC status
and control register or the next read of the ADC data register.

In single conversion mode, conversion begins with a write to the
ADSCR. Only one conversion occurs between writes to the ADSCR.

16 to17 ADC cycles

ADC frequency

Conversion time =

Number of bus cycles = conversion time x bus frequency

Analog-to-Digital Converter (ADC)

Interrupts

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Analog-to-Digital Converter (ADC)

5.4.5 Accuracy and Precision

The conversion process is monotonic and has no missing codes.

5.5 Interrupts

When the AIEN bit is set, the ADC module is capable of generating CPU
interrupts after each ADC conversion. A CPU interrupt is generated if the
COCO/IDMAS bit is at logic 0. If COCO/IDMAS bit is set, a DMA interrupt
is generated. The COCO/IDMAS bit is not used as a conversion
complete flag when interrupts are enabled.

5.6 Low-Power Modes

The WAIT and STOP instruction can put the MCU in low power-
consumption standby modes.

5.6.1 Wait Mode

5.6.2 Stop Mode

5.7 I/O Signals

The ADC module has six pins shared with port B,
PTB5/AD5�PTB0/ATD0.

Analog-to-Digital Converter (ADC)

I/O Registers

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Analog-to-Digital Converter (ADC)

5.8 I/O Registers

These I/O registers control and monitor ADC operation:

�

ADC status and control register (ADSCR)

�

ADC data register (ADR)

�

ADC clock register (ADCLK)

5.8.1 ADC Status and Control Register

Function of the ADC status and control register (ADSCR) is described
here.

COCO/IDMAS -- Conversions Complete/Interrupt DMA Select Bit

When the AIEN bit is a logic 0, the COCO/IDMAS is a read-only bit
which is set each time a conversion is completed except in the
continuous conversion mode where it is set after the first conversion.
This bit is cleared whenever the ADSCR is written or whenever the
ADR is read.

If the AIEN bit is a logic 1, the COCO/IDMAS is a read/write bit which
selects either CPU or DMA to service the ADC interrupt request.
Reset clears this bit.

1 = Conversion completed (AIEN = 0)/DMA interrupt (AIEN = 1)
0 = Conversion not completed (AIEN = 0)/CPU interrupt (AIEN = 1)

CAUTION:

Because the MC68HC908GR8 does NOT have a DMA module, the
IDMAS bit should NEVER be set when AIEN is set. Doing so will mask
ADC interrupts and cause unwanted results.

Address:

$0003C

Bit 7

Bit 0

Read:

COCO/

IDMAS

AIEN

ADCO

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

Write:

Reset:

Figure 5-2. ADC Status and Control Register (ADSCR)

Analog-to-Digital Converter (ADC)

Technical Data

MC68HC908GR8 -- Rev 4.0

Analog-to-Digital Converter (ADC)

MOTOROLA

AIEN -- ADC Interrupt Enable Bit

When this bit is set, an interrupt is generated at the end of an ADC
conversion. The interrupt signal is cleared when the data register is
read or the status/control register is written. Reset clears the AIEN bit.

1 = ADC interrupt enabled
0 = ADC interrupt disabled

ADCO -- ADC Continuous Conversion Bit

When this bit is set, the ADC will convert samples continuously and
update the ADR register at the end of each conversion. Only one
conversion is completed between writes to the ADSCR when this bit
is cleared. Reset clears the ADCO bit.

1 = Continuous ADC conversion
0 = One ADC conversion

ADCH4�ADCH0 -- ADC Channel Select Bits

ADCH4�ADCH0 form a 5-bit field which is used to select one of 16
ADC channels. Only six channels, AD5�AD0, are available on this
MCU. The channels are detailed in

Table 5-1

. Care should be taken

when using a port pin as both an analog and digital input
simultaneously to prevent switching noise from corrupting the analog
signal. See

Table 5-1

The ADC subsystem is turned off when the channel select bits are all
set to 1. This feature allows for reduced power consumption for the
MCU when the ADC is not being used.

NOTE:

Recovery from the disabled state requires one conversion cycle to
stabilize.

The voltage levels supplied from internal reference nodes, as specified
in

Table 5-1

, are used to verify the operation of the ADC converter both

in production test and for user applications.

Table 5-1. Mux Channel Select

ADCH4

ADCH3

ADCH2

ADCH1

ADCH0

Input Select

PTB0/ATD0

PTB1/ATD1

PTB2/ATD2

Break Module (BRK)

Technical Data

MC68HC908GR8 -- Rev 4.0

Break Module (BRK)

MOTOROLA

6.4 Functional Description

When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal to the
CPU. The CPU then loads the instruction register with a software
interrupt instruction (SWI) after completion of the current CPU
instruction. The program counter vectors to $FFFC and $FFFD ($FEFC
and $FEFD in monitor mode).

The following events can cause a break interrupt to occur:

�

A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.

�

Software writes a logic 1 to the BRKA bit in the break status and
control register.

When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation.

Figure 6-1

shows the structure of the break module.

Figure 6-1. Break Module Block Diagram

IAB15�IAB8

IAB7�IAB0

8-BIT COMPARATOR

CONTROL

BREAK ADDRESS REGISTER LOW

BREAK ADDRESS REGISTER HIGH

IAB15�IAB0

BREAK

Break Module (BRK)

Functional Description

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Break Module (BRK)

6.4.1 Flag Protection During Break Interrupts

The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear status bits during the break state.

6.4.2 CPU During Break Interrupts

The CPU starts a break interrupt by:

�

Loading the instruction register with the SWI instruction

�

Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)

Addr.

Register Name

Bit 7

Bit 0

$FE00

SIM Break Status Register

(SBSR)

Read:

Write:

NOTE

Reset:

$FE03

SIM Break Flag Control

Read:

BCFE

Write:

Reset:

$FE09

Break Address Register

High (BRKH)

Read:

Bit 15

Bit 8

Write:

Reset:

$FE0A

Break Address Register

Low (BRKL)

Read:

Bit 7

Bit 0

Write:

Reset:

$FE0B

Break Status and Control

Read:

BRKE

BRKA

Write:

Reset:

Note: Writing a logic 0 clears BW.

= Unimplemented

= Reserved

Figure 6-2. I/O Register Summary

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Clock Generator Module (CGMC)

Technical Data -- MC68HC908GR8

Section 7. Clock Generator Module (CGMC)

7.1 Contents

7.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

7.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

7.5

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

7.6

CGMC Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

7.7

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.8

Special Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

7.9

Acquisition/Lock Time Specifications . . . . . . . . . . . . . . . . . . .125

7.2 Introduction

This section describes the clock generator module. The CGMC
generates the crystal clock signal, CGMXCLK, which operates at the
frequency of the crystal. The CGMC also generates the base clock
signal, CGMOUT, which is based on either the crystal clock divided by
two or the phase-locked loop (PLL) clock, CGMVCLK, divided by two. In
user mode, CGMOUT is the clock from which the SIM derives the
system clocks, including the bus clock, which is at a frequency of
CGMOUT/2. In monitor mode, PTC3 determines the bus clock. The PLL
is a fully functional frequency generator designed for use with crystals or
ceramic resonators. The PLL can generate an 8-MHz bus frequency
using a 32-kHz crystal.

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

7.3 Features

Features of the CGMC include:

�

Phase-locked loop with output frequency in integer multiples of an
integer dividend of the crystal reference

�

Low-frequency crystal operation with low-power operation and
high-output frequency resolution

�

Programmable prescaler for power-of-two increases in frequency

�

Programmable hardware voltage-controlled oscillator (VCO) for
low-jitter operation

�

Automatic bandwidth control mode for low-jitter operation

�

Automatic frequency lock detector

�

CPU interrupt on entry or exit from locked condition

�

Configuration register bit to allow oscillator operation during stop
mode

7.4 Functional Description

The CGMC consists of three major submodules:

�

Crystal oscillator circuit -- The crystal oscillator circuit generates
the constant crystal frequency clock, CGMXCLK.

�

Phase-locked loop (PLL) -- The PLL generates the
programmable VCO frequency clock, CGMVCLK.

�

Base clock selector circuit -- This software-controlled circuit
selects either CGMXCLK divided by two or the VCO clock,
CGMVCLK, divided by two as the base clock, CGMOUT. The SIM
derives the system clocks from either CGMOUT or CGMXCLK.

Figure 7-1

shows the structure of the CGMC.

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

7.4.1 Crystal Oscillator Circuit

The crystal oscillator circuit consists of an inverting amplifier and an
external crystal. The OSC1 pin is the input to the amplifier and the OSC2
pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable
the crystal oscillator circuit.

The CGMXCLK signal is the output of the crystal oscillator circuit and
runs at a rate equal to the crystal frequency. CGMXCLK is then buffered
to produce CGMRCLK, the PLL reference clock.

CGMXCLK can be used by other modules which require precise timing
for operation. The duty cycle of CGMXCLK is not guaranteed to be 50%
and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the
OSC1 pin of the crystal oscillator circuit. Connect the external clock to
the OSC1 pin and let the OSC2 pin float.

7.4.2 Phase-Locked Loop Circuit (PLL)

The PLL is a frequency generator that can operate in either acquisition
mode or tracking mode, depending on the accuracy of the output
frequency. The PLL can change between acquisition and tracking
modes either automatically or manually.

7.4.3 PLL Circuits

The PLL consists of these circuits:

�

Voltage-controlled oscillator (VCO)

�

Reference divider

�

Frequency prescaler

�

Modulo VCO frequency divider

�

Phase detector

�

Loop filter

�

Lock detector

Clock Generator Module (CGMC)

Functional Description

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Technical Data

MOTOROLA

Clock Generator Module (CGMC)

103

The operating range of the VCO is programmable for a wide range of
frequencies and for maximum immunity to external noise, including
supply and CGM/XFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f

VRS

Modulating the voltage on the CGM/XFC pin changes the frequency
within this range. By design, f

VRS

is equal to the nominal center-of-range

frequency, f

NOM

, (38.4 kHz) times a linear factor, L, and a power-of-two

factor, E, or (L

�

NOM

CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK.
CGMRCLK runs at a frequency, f

RCLK

, and is fed to the PLL through a

programmable modulo reference divider, which divides f

RCLK

by a

factor, R. The divider's output is the final reference clock, CGMRDV,
running at a frequency, f

RDV

= f

RCLK

/R. With an external crystal

(30 kHz�100 kHz), always set R = 1 for specified performance. With an
external high-frequency clock source, use R to divide the external
frequency to between 30 kHz and 100 kHz.

The VCO's output clock, CGMVCLK, running at a frequency, f

VCLK

, is

fed back through a programmable prescale divider and a programmable
modulo divider. The prescaler divides the VCO clock by a power-of-two
factor P and the modulo divider reduces the VCO clock by a factor, N.
The dividers' output is the VCO feedback clock, CGMVDV, running at a
frequency, f

VDV

= f

VCLK

/(N

�

). (See

Programming the PLL

for more

information.)

The phase detector then compares the VCO feedback clock, CGMVDV,
with the final reference clock, CGMRDV. A correction pulse is generated
based on the phase difference between the two signals. The loop filter
then slightly alters the DC voltage on the external capacitor connected
to CGM/XFC based on the width and direction of the correction pulse.
The filter can make fast or slow corrections depending on its mode,
described in

Acquisition and Tracking Modes

. The value of the external

capacitor and the reference frequency determine the speed of the
corrections and the stability of the PLL.

The lock detector compares the frequencies of the VCO feedback clock,
CGMVDV, and the final reference clock, CGMRDV. Therefore, the
speed of the lock detector is directly proportional to the final reference

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

frequency, f

RDV

. The circuit determines the mode of the PLL and the lock

condition based on this comparison.

7.4.4 Acquisition and Tracking Modes

The PLL filter is manually or automatically configurable into one of two
operating modes:

�

Acquisition mode -- In acquisition mode, the filter can make large
frequency corrections to the VCO. This mode is used at PLL
startup or when the PLL has suffered a severe noise hit and the
VCO frequency is far off the desired frequency. When in
acquisition mode, the ACQ bit is clear in the PLL bandwidth control
register. (See

PLL Bandwidth Control Register

�

Tracking mode -- In tracking mode, the filter makes only small
corrections to the frequency of the VCO. PLL jitter is much lower
in tracking mode, but the response to noise is also slower. The
PLL enters tracking mode when the VCO frequency is nearly
correct, such as when the PLL is selected as the base clock
source. (See

Base Clock Selector Circuit

.) The PLL is

automatically in tracking mode when not in acquisition mode or
when the ACQ bit is set.

7.4.5 Manual and Automatic PLL Bandwidth Modes

The PLL can change the bandwidth or operational mode of the loop filter
manually or automatically. Automatic mode is recommended for most
users.

In automatic bandwidth control mode (AUTO = 1), the lock detector
automatically switches between acquisition and tracking modes.
Automatic bandwidth control mode also is used to determine when the
VCO clock, CGMVCLK, is safe to use as the source for the base clock,
CGMOUT. (See

PLL Bandwidth Control Register

.) If PLL interrupts are

enabled, the software can wait for a PLL interrupt request and then
check the LOCK bit. If interrupts are disabled, software can poll the
LOCK bit continuously (during PLL startup, usually) or at periodic
intervals. In either case, when the LOCK bit is set, the VCO clock is safe

Clock Generator Module (CGMC)

Functional Description

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Technical Data

MOTOROLA

Clock Generator Module (CGMC)

105

to use as the source for the base clock. (See

Base Clock Selector

Circuit

.) If the VCO is selected as the source for the base clock and the

LOCK bit is clear, the PLL has suffered a severe noise hit and the
software must take appropriate action, depending on the application.
(See

Interrupts

for information and precautions on using interrupts.)

The following conditions apply when the PLL is in automatic bandwidth
control mode:

�

The ACQ bit (see

PLL Bandwidth Control Register

) is a read-only

indicator of the mode of the filter. (See

Acquisition and Tracking

Modes

�

The ACQ bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See

Acquisition/Lock Time Specifications

for

more information.)

�

The LOCK bit is a read-only indicator of the locked state of the PLL.

�

The LOCK bit is set when the VCO frequency is within a certain
tolerance and is cleared when the VCO frequency is out of a
certain tolerance. (See

Acquisition/Lock Time Specifications

for

more information.)

�

CPU interrupts can occur if enabled (PLLIE = 1) when the PLL's
lock condition changes, toggling the LOCK bit. (See

PLL Control

The PLL also may operate in manual mode (AUTO = 0). Manual mode is
used by systems that do not require an indicator of the lock condition for
proper operation. Such systems typically operate well below f

BUSMAX

The following conditions apply when in manual mode:

�

ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.

�

Before entering tracking mode (ACQ = 1), software must wait a
given time, t

ACQ

(see

Acquisition/Lock Time Specifications

), after

turning on the PLL by setting PLLON in the PLL control register
(PCTL).

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

�

Software must wait a given time, t

, after entering tracking mode

before selecting the PLL as the clock source to CGMOUT
(BCS = 1).

�

The LOCK bit is disabled.

�

CPU interrupts from the CGMC are disabled.

7.4.6 Programming the PLL

The following procedure shows how to program the PLL.

NOTE:

The round function in the following equations means that the real
number should be rounded to the nearest integer number.

1. Choose the desired bus frequency, f

BUSDES

2. Calculate the desired VCO frequency (four times the desired bus

frequency).

3. Choose a practical PLL (crystal) reference frequency, f

RCLK

, and

the reference clock divider, R. Typically, the reference crystal is
32.768 kHz and R = 1.

Frequency errors to the PLL are corrected at a rate of f

RCLK

/R. For

stability and lock time reduction, this rate must be as fast as
possible. The VCO frequency must be an integer multiple of this
rate. The relationship between the VCO frequency, f

VCLK

, and the

reference frequency, f

RCLK

P, the power of two multiplier, and N, the range multiplier, are
integers.

In cases where desired bus frequency has some tolerance,
choose f

RCLK

to a value determined either by other module

requirements (such as modules which are clocked by CGMXCLK),
cost requirements, or ideally, as high as the specified range

VC LKD ES

BUSDES

�

VCLK

----------- f

R CLK

(

)

Clock Generator Module (CGMC)

Functional Description

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Technical Data

MOTOROLA

Clock Generator Module (CGMC)

107

allows. See

Electrical Specifications

. Choose the reference

divider, R = 1. After choosing N and P, the actual bus frequency
can be determined using equation in 2 above.

When the tolerance on the bus frequency is tight, choose f

RCLK

an integer divisor of f

BUSDES

, and R = 1. If f

RCLK

cannot meet this

requirement, use the following equation to solve for R with
practical choices of f

RCLK

, and choose the f

RCLK

that gives the

lowest R.

4. Select a VCO frequency multiplier, N.

Reduce N/R to the lowest possible R.

5. If N is < N

max

, use P = 0. If N > N

max

, choose P using this table:

Then recalculate N:

6. Calculate and verify the adequacy of the VCO and bus

frequencies f

VCLK

and f

BUS

7. Select the VCO's power-of-two range multiplier E, according to

Current N Value

round R

MAX

VCL KDES

RCL K

--------------------------

integer

VCLKDES

RCLK

--------------------------

�

round

VCLKDES

�

RCL K

-------------------------------------

max

�

max

�

max

�

max

�

max

�

round

VC LKD ES

�

RCLK

�

-------------------------------------

VCL K

N R

�

(

)

RCL K

�

BU S

VC LK

(

)

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

this table:

8. Select a VCO linear range multiplier, L, where f

NOM

= 38.4 kHz

9. Calculate and verify the adequacy of the VCO programmed

center-of-range frequency, f

VRS

. The center-of-range frequency is

the midpoint between the minimum and maximum frequencies
attainable by the PLL.

For proper operation,

10. Verify the choice of P, R, N, E, and L by comparing f

VCLK

to f

VRS

and f

VCLKDES

. For proper operation, f

VCLK

must be within the

application's tolerance of f

VCLKDES

, and f

VRS

must be as close as

possible to f

VCLK

NOTE:

Exceeding the recommended maximum bus frequency or VCO
frequency can crash the MCU.

11. Program the PLL registers accordingly:

a. In the PRE bits of the PLL control register (PCTL), program

the binary equivalent of P.

b. In the VPR bits of the PLL control register (PCTL), program

the binary equivalent of E.

Frequency Range

0 < f

VCLK

< 9,830,400

9,830,400

VCLK

< 19,660,800

19,660,800

VCLK

< 39,321,600

NOTE: Do not program E to a value of 3.

round

VCLK

NOM

�

--------------------------

VRS

�

(

)

NOM

VRS

VCLK

�

N OM

�

--------------------------

Clock Generator Module (CGMC)

Functional Description

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Technical Data

MOTOROLA

Clock Generator Module (CGMC)

109

c. In the PLL multiplier select register low (PMSL) and the PLL

multiplier select register high (PMSH), program the binary
equivalent of N.

d. In the PLL VCO range select register (PMRS), program the

binary coded equivalent of L.

e. In the PLL reference divider select register (PMDS), program

the binary coded equivalent of R.

Table 7-1

provides numeric examples (numbers are in hexadecimal

notation):

7.4.7 Special Programming Exceptions

The programming method described in

Programming the PLL

does not

account for three possible exceptions. A value of 0 for R, N, or L is
meaningless when used in the equations given. To account for these
exceptions:

�

A 0 value for R or N is interpreted exactly the same as a value of 1.

�

A 0 value for L disables the PLL and prevents its selection as the
source for the base clock.

(See

Base Clock Selector Circuit

Table 7-1. Numeric Example

BUS

RCLK

2.0 MHz

32.768 kHz

2.4576 MHz

32.768 kHz

12C

2.5 MHz

32.768 kHz

132

4.0 MHz

32.768 kHz

1E9

4.9152 MHz

32.768 kHz

258

5.0 MHz

32.768 kHz

263

7.3728 MHz

32.768 kHz

384

8.0 MHz

32.768 kHz

3D1

Clock Generator Module (CGMC)

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Clock Generator Module (CGMC)

MOTOROLA

7.4.8 Base Clock Selector Circuit

This circuit is used to select either the crystal clock, CGMXCLK, or the
VCO clock, CGMVCLK, as the source of the base clock, CGMOUT. The
two input clocks go through a transition control circuit that waits up to
three CGMXCLK cycles and three CGMVCLK cycles to change from
one clock source to the other. During this time, CGMOUT is held in
stasis. The output of the transition control circuit is then divided by two
to correct the duty cycle. Therefore, the bus clock frequency, which is
one-half of the base clock frequency, is one-fourth the frequency of the
selected clock (CGMXCLK or CGMVCLK).

The BCS bit in the PLL control register (PCTL) selects which clock drives
CGMOUT. The VCO clock cannot be selected as the base clock source
if the PLL is not turned on. The PLL cannot be turned off if the VCO clock
is selected. The PLL cannot be turned on or off simultaneously with the
selection or deselection of the VCO clock. The VCO clock also cannot
be selected as the base clock source if the factor L is programmed to a
0. This value would set up a condition inconsistent with the operation of
the PLL, so that the PLL would be disabled and the crystal clock would
be forced as the source of the base clock.

7.4.9 CGMC External Connections

In its typical configuration, the CGMC requires up to nine external
components. Five of these are for the crystal oscillator and two or four
are for the PLL.

The crystal oscillator is normally connected in a Pierce oscillator
configuration, as shown in

Figure 7-2

shows only the logical

representation of the internal components and may not represent actual
circuitry. The oscillator configuration uses five components:

�

Crystal, X

�

Fixed capacitor, C

�

Tuning capacitor, C

(can also be a fixed capacitor)

�

Feedback resistor, R

�

Series resistor, R

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

7.5 I/O Signals

The following paragraphs describe the CGMC I/O signals.

7.5.1 Crystal Amplifier Input Pin (OSC1)

The OSC1 pin is an input to the crystal oscillator amplifier.

7.5.2 Crystal Amplifier Output Pin (OSC2)

The OSC2 pin is the output of the crystal oscillator inverting amplifier.

7.5.3 External Filter Capacitor Pin (CGMXFC)

The CGMXFC pin is required by the loop filter to filter out phase
corrections. An external filter network is connected to this pin. (See

Figure 7-2

NOTE:

To prevent noise problems, the filter network should be placed as close
to the CGMXFC pin as possible, with minimum routing distances and no
routing of other signals across the network.

7.5.4 PLL Analog Power Pin (V

DDA

)

DDA

is a power pin used by the analog portions of the PLL. Connect the

DDA

pin to the same voltage potential as the V

pin.

NOTE:

Route V

DDA

carefully for maximum noise immunity and place bypass

capacitors as close as possible to the package.

7.5.5 PLL Analog Ground Pin (V

SSA

)

SSA

is a ground pin used by the analog portions of the PLL. Connect

the V

SSA

pin to the same voltage potential as the V

pin.

NOTE:

Route V

SSA

carefully for maximum noise immunity and place bypass

capacitors as close as possible to the package.

Clock Generator Module (CGMC)

I/O Signals

MC68HC908GR8 -- Rev 4.0

Technical Data

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Clock Generator Module (CGMC)

113

7.5.6 Oscillator Enable Signal (SIMOSCEN)

The SIMOSCEN signal comes from the system integration module (SIM)
and enables the oscillator and PLL.

7.5.7 Oscillator Stop Mode Enable Bit (OSCSTOPENB)

OSCSTOPENB is a bit in the CONFIG register that enables the oscillator
to continue operating during stop mode. If this bit is set, the Oscillator
continues running during stop mode. If this bit is not set (default), the
oscillator is controlled by the SIMOSCEN signal which will disable the
oscillator during stop mode.

7.5.8 Crystal Output Frequency Signal (CGMXCLK)

CGMXCLK is the crystal oscillator output signal. It runs at the full speed
of the crystal (f

XCLK

) and comes directly from the crystal oscillator circuit.

Figure 7-2

shows only the logical relation of CGMXCLK to OSC1 and

OSC2 and may not represent the actual circuitry. The duty cycle of
CGMXCLK is unknown and may depend on the crystal and other
external factors. Also, the frequency and amplitude of CGMXCLK can be
unstable at startup.

7.5.9 CGMC Base Clock Output (CGMOUT)

CGMOUT is the clock output of the CGMC. This signal goes to the SIM,
which generates the MCU clocks. CGMOUT is a 50 percent duty cycle
clock running at twice the bus frequency. CGMOUT is software
programmable to be either the oscillator output, CGMXCLK, divided by
two or the VCO clock, CGMVCLK, divided by two.

7.5.10 CGMC CPU Interrupt (CGMINT)

CGMINT is the interrupt signal generated by the PLL lock detector.

Clock Generator Module (CGMC)

Technical Data

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114

Clock Generator Module (CGMC)

MOTOROLA

7.6 CGMC Registers

These registers control and monitor operation of the CGMC:

�

PLL control register (PCTL)
(See

PLL Control Register

�

PLL bandwidth control register (PBWC)
(See

PLL Bandwidth Control Register

�

PLL multiplier select register high (PMSH)
(See

PLL Multiplier Select Register High

�

PLL multiplier select register low (PMSL)
(See

PLL Multiplier Select Register Low

�

PLL VCO range select register (PMRS)
(See

PLL VCO Range Select Register

�

PLL reference divider select register (PMDS)
(See

PLL Reference Divider Select Register

Figure 7-3

is a summary of the CGMC registers.

Addr.

Register Name

Bit 7

Bit 0

$0036

PLL Control Register

(PCTL)

Read:

PLLIE

PLLF

PLLON

BCS

PRE1

PRE0

VPR1

VPR0

Write:

Reset:

$0037

PLL Bandwidth Control

Read:

AUTO

LOCK

ACQ

Write:

Reset:

$0038

PLL Multiplier Select High

Read:

MUL11

MUL10

MUL9

MUL8

Write:

Reset:

$0039

PLL Multiplier Select Low

Read:

MUL7

MUL6

MUL5

MUL4

MUL3

MUL2

MUL1

MUL0

Write:

Reset:

Figure 7-3. CGMC I/O Register Summary

Clock Generator Module (CGMC)

CGMC Registers

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Clock Generator Module (CGMC)

115

7.6.1 PLL Control Register

The PLL control register (PCTL) contains the interrupt enable and flag
bits, the on/off switch, the base clock selector bit, the prescaler bits, and
the VCO power-of-two range selector bits.

PLLIE -- PLL Interrupt Enable Bit

This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.

$003A

PLL VCO Select Range

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

$003B

PLL Reference Divider

Select Register (PMDS)

Read:

RDS3

RDS2

RDS1

RDS0

Write:

Reset:

= Unimplemented

= Reserved

NOTES:

1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.

Figure 7-3. CGMC I/O Register Summary

Address:

$0036

Bit 7

Bit 0

Read:

PLLIE

PLLF

PLLON

BCS

PRE1

PRE0

VPR1

VPR0

Write:

Reset:

= Unimplemented

Figure 7-4. PLL Control Register (PCTL)

Clock Generator Module (CGMC)

Technical Data

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Clock Generator Module (CGMC)

MOTOROLA

1 = PLL interrupts enabled
0 = PLL interrupts disabled

PLLF -- PLL Interrupt Flag Bit

This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.

1 = Change in lock condition
0 = No change in lock condition

NOTE:

Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.

PLLON -- PLL On Bit

This read/write bit activates the PLL and enables the VCO clock,
CGMVCLK. PLLON cannot be cleared if the VCO clock is driving the
base clock, CGMOUT (BCS = 1). (See

Base Clock Selector Circuit

Reset sets this bit so that the loop can stabilize as the MCU is
powering up.

1 = PLL on
0 = PLL off

BCS -- Base Clock Select Bit

This read/write bit selects either the crystal oscillator output,
CGMXCLK, or the VCO clock, CGMVCLK, as the source of the
CGMC output, CGMOUT. CGMOUT frequency is one-half the
frequency of the selected clock. BCS cannot be set while the PLLON
bit is clear. After toggling BCS, it may take up to three CGMXCLK and
three CGMVCLK cycles to complete the transition from one source
clock to the other. During the transition, CGMOUT is held in stasis.
(See

Base Clock Selector Circuit

.) Reset clears the BCS bit.

1 = CGMVCLK divided by two drives CGMOUT
0 = CGMXCLK divided by two drives CGMOUT

NOTE:

PLLON and BCS have built-in protection that prevents the base clock
selector circuit from selecting the VCO clock as the source of the base
clock if the PLL is off. Therefore, PLLON cannot be cleared when BCS

Clock Generator Module (CGMC)

CGMC Registers

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Clock Generator Module (CGMC)

117

is set, and BCS cannot be set when PLLON is clear. If the PLL is off
(PLLON = 0), selecting CGMVCLK requires two writes to the PLL control
register. (See

Base Clock Selector Circuit

PRE1 and PRE0 -- Prescaler Program Bits

These read/write bits control a prescaler that selects the prescaler
power-of-two multiplier, P. (See

PLL Circuits

and

Programming the

PLL

.) PRE1 and PRE0 cannot be written when the PLLON bit is set.

Reset clears these bits.

NOTE:

The value of P is normally 0 when using a 32.768-kHz crystal as the
reference.

VPR1 and 0 -- VCO Power-of-Two Range Select Bits

These read/write bits control the VCO's hardware power-of-two range
multiplier E that, in conjunction with L (See

PLL Circuits

Programming the PLL

, and

PLL VCO Range Select Register

controls the hardware center-of-range frequency, f

VRS

. VPR1:VPR0

cannot be written when the PLLON bit is set. Reset clears these bits.

Table 7-2. PRE 1 and PRE0 Programming

PRE1 and PRE0

Prescaler Multiplier

Table 7-3. VPR1 and VPR0 Programming

VPR1 and VPR0

VCO Power-of-Two

Range Multiplier

(1)

1. Do not program E to a value of 3.

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7.6.2 PLL

Bandwidth Control Register

The PLL bandwidth control register (PBWC):

�

Selects automatic or manual (software-controlled) bandwidth
control mode

�

Indicates when the PLL is locked

�

In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode

�

In manual operation, forces the PLL into acquisition or tracking
mode

AUTO -- Automatic Bandwidth Control Bit

This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.

1 = Automatic bandwidth control
0 = Manual bandwidth control

LOCK -- Lock Indicator Bit

When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. The write one function of this bit is
reserved for test, so this bit must always be written a 0. Reset clears
the LOCK bit.

Address:

$0037

Bit 7

Bit 0

Read:

AUTO

LOCK

ACQ

Write:

Reset:

= Unimplemented

= Reserved

Figure 7-5. PLL Bandwidth Control Register (PBWC)

Clock Generator Module (CGMC)

CGMC Registers

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119

1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked

ACQ -- Acquisition Mode Bit

When the AUTO bit is set, ACQ is a read-only bit that indicates
whether the PLL is in acquisition mode or tracking mode. When the
AUTO bit is clear, ACQ is a read/write bit that controls whether the
PLL is in acquisition or tracking mode.

In automatic bandwidth control mode (AUTO = 1), the last-written
value from manual operation is stored in a temporary location and is
recovered when manual operation resumes. Reset clears this bit,
enabling acquisition mode.

1 = Tracking mode
0 = Acquisition mode

7.6.3 PLL Multiplier Select Register High

The PLL multiplier select register high (PMSH) contains the
programming information for the high byte of the modulo feedback
divider.

MUL11�MUL8 -- Multiplier Select Bits

These read/write bits control the high byte of the modulo feedback
divider that selects the VCO frequency multiplier N. (See

PLL Circuits

and

Programming the PLL

.) A value of $0000 in the multiplier select

registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $0040 for a default multiply
value of 64.

Address:

$0038

Bit 7

Bit 0

Read:

MUL11

MUL10

MUL9

MUL8

Write:

Reset:

= Unimplemented

Figure 7-6. PLL Multiplier Select Register High (PMSH)

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NOTE:

The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).

PMSH[7:4] -- Unimplemented Bits

These bits have no function and always read as logic 0s.

7.6.4 PLL Multiplier Select Register Low

The PLL multiplier select register low (PMSL) contains the programming
information for the low byte of the modulo feedback divider.

MUL7�MUL0 -- Multiplier Select Bits

These read/write bits control the low byte of the modulo feedback
divider that selects the VCO frequency multiplier, N. (See

PLL Circuits

and

Programming the PLL

.) MUL7�MUL0 cannot be written when the

PLLON bit in the PCTL is set. A value of $0000 in the multiplier select
registers configures the modulo feedback divider the same as a value
of $0001. Reset initializes the register to $40 for a default multiply
value of 64.

NOTE:

The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).

Address:

$0038

Bit 7

Bit 0

Read:

MUL7

MUL6

MUL5

MUL4

MUL3

MUL2

MUL1

MUL0

Write:

Reset:

Figure 7-7. PLL Multiplier Select Register Low (PMSL)

Clock Generator Module (CGMC)

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121

7.6.5 PLL VCO Range Select Register

NOTE:

PMRS may be called PVRS on other HC08 derivatives.

The PLL VCO range select register (PMRS) contains the programming
information required for the hardware configuration of the VCO.

VRS7�VRS0 -- VCO Range Select Bits

These read/write bits control the hardware center-of-range linear
multiplier L which, in conjunction with E (see

PLL Circuits

Programming the PLL

, and

PLL Control Register

), controls the

hardware center-of-range frequency, f

VRS

. VRS7�VRS0 cannot be

written when the PLLON bit in the PCTL is set. (See

Special

Programming Exceptions

A value of $00 in the VCO range select

Base Clock Selector Circuit

and

Special

Programming Exceptions

.). Reset initializes the register to $40 for a

default range multiply value of 64.

NOTE:

The VCO range select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.

The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.

Address:

$003A

Bit 7

Bit 0

Read:

VRS7

VRS6

VRS5

VRS4

VRS3

VRS2

VRS1

VRS0

Write:

Reset:

Figure 7-8. PLL VCO Range Select Register (PMRS)

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7.6.6 PLL Reference Divider Select Register

NOTE:

PMDS may be called PRDS on other HC08 derivatives.

The PLL reference divider select register (PMDS) contains the
programming information for the modulo reference divider.

RDS3�RDS0 -- Reference Divider Select Bits

These read/write bits control the modulo reference divider that selects
the reference division factor, R. (See

PLL Circuits

and

Programming

the PLL

.) RDS7�RDS0 cannot be written when the PLLON bit in the

PCTL is set. A value of $00 in the reference divider select register
configures the reference divider the same as a value of $01. (See

Special Programming Exceptions

.) Reset initializes the register to

$01 for a default divide value of 1.

NOTE:

The reference divider select bits have built-in protection such that they
cannot be written when the PLL is on (PLLON = 1).

NOTE:

The default divide value of 1 is recommended for all applications.

PMDS7�PMDS4 -- Unimplemented Bits

These bits have no function and always read as logic 0s.

Address:

$003B

Bit 7

Bit 0

Read:

RDS3

RDS2

RDS1

RDS0

Write:

Reset:

= Unimplemented

Figure 7-9. PLL Reference Divider Select Register (PMDS)

Clock Generator Module (CGMC)

Interrupts

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123

7.7 Interrupts

When the AUTO bit is set in the PLL bandwidth control register (PBWC),
the PLL can generate a CPU interrupt request every time the LOCK bit
changes state. The PLLIE bit in the PLL control register (PCTL) enables
CPU interrupts from the PLL. PLLF, the interrupt flag in the PCTL,
becomes set whether interrupts are enabled or not. When the AUTO bit
is clear, CPU interrupts from the PLL are disabled and PLLF reads as
logic 0.

Software should read the LOCK bit after a PLL interrupt request to see
if the request was due to an entry into lock or an exit from lock. When the
PLL enters lock, the VCO clock, CGMVCLK, divided by two can be
selected as the CGMOUT source by setting BCS in the PCTL. When the
PLL exits lock, the VCO clock frequency is corrupt, and appropriate
precautions should be taken. If the application is not frequency sensitive,
interrupts should be disabled to prevent PLL interrupt service routines
from impeding software performance or from exceeding stack
limitations.

NOTE:

Software can select the CGMVCLK divided by two as the CGMOUT
source even if the PLL is not locked (LOCK = 0). Therefore, software
should make sure the PLL is locked before setting the BCS bit.

7.8 Special Modes

The WAIT instruction puts the MCU in low power-consumption standby
modes.

7.8.1 Wait Mode

The WAIT instruction does not affect the CGMC. Before entering wait
mode, software can disengage and turn off the PLL by clearing the BCS
and PLLON bits in the PLL control register (PCTL) to save power. Less
power-sensitive applications can disengage the PLL without turning it
off, so that the PLL clock is immediately available at WAIT exit. This
would be the case also when the PLL is to wake the MCU from wait

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MOTOROLA

mode, such as when the PLL is first enabled and waiting for LOCK or
LOCK is lost.

7.8.2 Stop Mode

If the OSCSTOPENB bit in the CONFIG register is cleared (default),
then the STOP instruction disables the CGMC (oscillator and phase
locked loop) and holds low all CGMC outputs (CGMXCLK, CGMOUT,
and CGMINT).

If the OSCSTOPENB bit in the CONFIG register is set, then the phase
locked loop is shut off but the oscillator will continue to operate in stop
mode.

7.8.3 CGMC During Break Interrupts

The system integration module (SIM) controls whether status bits in
other modules can be cleared during the break state. The BCFE bit in
the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See

SIM Break Flag Control

To allow software to clear status bits during a break interrupt, write a
logic 1 to the BCFE bit. If a status bit is cleared during the break state, it
remains cleared when the MCU exits the break state.

To protect the PLLF bit during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
the PLL control register during the break state without affecting the PLLF
bit.

Clock Generator Module (CGMC)

Acquisition/Lock Time Specifications

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125

7.9 Acquisition/Lock Time Specifications

The acquisition and lock times of the PLL are, in many applications, the
most critical PLL design parameters. Proper design and use of the PLL
ensures the highest stability and lowest acquisition/lock times.

7.9.1 Acquisition/Lock Time Definitions

Typical control systems refer to the acquisition time or lock time as the
reaction time, within specified tolerances, of the system to a step input.
In a PLL, the step input occurs when the PLL is turned on or when it
suffers a noise hit. The tolerance is usually specified as a percentage of
the step input or when the output settles to the desired value plus or
minus a percentage of the frequency change. Therefore, the reaction
time is constant in this definition, regardless of the size of the step input.
For example, consider a system with a 5 percent acquisition time
tolerance. If a command instructs the system to change from 0 Hz to
1 MHz, the acquisition time is the time taken for the frequency to reach
1 MHz

�

50 kHz. Fifty kHz = 5% of the 1-MHz step input. If the system is

operating at 1 MHz and suffers a �100-kHz noise hit, the acquisition time
is the time taken to return from 900 kHz to 1 MHz

�

5 kHz. Five kHz = 5%

of the 100-kHz step input.

Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.

7.9.2 Parametric Influences on Reaction Time

Acquisition and lock times are designed to be as short as possible while
still providing the highest possible stability. These reaction times are not
constant, however. Many factors directly and indirectly affect the
acquisition time.

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Clock Generator Module (CGMC)

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The most critical parameter which affects the reaction times of the PLL
is the reference frequency, f

RDV

. This frequency is the input to the phase

detector and controls how often the PLL makes corrections. For stability,
the corrections must be small compared to the desired frequency, so
several corrections are required to reduce the frequency error.
Therefore, the slower the reference the longer it takes to make these
corrections. This parameter is under user control via the choice of crystal
frequency f

XCLK

and the R value programmed in the reference divider.

(See

PLL Circuits

Programming the PLL

, and

PLL Reference Divider

Select Register

Another critical parameter is the external filter network. The PLL
modifies the voltage on the VCO by adding or subtracting charge from
capacitors in this network. Therefore, the rate at which the voltage
changes for a given frequency error (thus change in charge) is
proportional to the capacitance. The size of the capacitor also is related
to the stability of the PLL. If the capacitor is too small, the PLL cannot
make small enough adjustments to the voltage and the system cannot
lock. If the capacitor is too large, the PLL may not be able to adjust the
voltage in a reasonable time. (See

Choosing a Filter

Also important is the operating voltage potential applied to V

DDA

. The

power supply potential alters the characteristics of the PLL. A fixed value
is best. Variable supplies, such as batteries, are acceptable if they vary
within a known range at very slow speeds. Noise on the power supply is
not acceptable, because it causes small frequency errors which
continually change the acquisition time of the PLL.

Temperature and processing also can affect acquisition time because
the electrical characteristics of the PLL change. The part operates as
specified as long as these influences stay within the specified limits.
External factors, however, can cause drastic changes in the operation of
the PLL. These factors include noise injected into the PLL through the
filter capacitor, filter capacitor leakage, stray impedances on the circuit
board, and even humidity or circuit board contamination.

MC68HC908GR8 -- Rev 4.0

Technical Data

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Configuration Register (CONFIG)

129

Technical Data -- MC68HC908GR8

Section 8. Configuration Register (CONFIG)

8.1 Contents

8.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

8.2 Introduction

This section describes the configuration registers, CONFIG1 and
CONFIG2. The configuration registers enable or disable these options:

�

Stop mode recovery time (32 CGMXCLK cycles or 4096
CGMXCLK cycles)

�

COP timeout period (2

� 2

or 2

� 2

CGMXCLK cycles)

�

STOP instruction

�

Computer operating properly module (COP)

�

Low-voltage inhibit (LVI) module control and voltage trip point
selection

�

Enable/disable the oscillator (OSC) during stop mode

8.3 Functional Description

The configuration registers are used in the initialization of various
options. The configuration registers can be written once after each reset.
All of the configuration register bits are cleared during reset. Since the
various options affect the operation of the MCU, it is recommended that
these registers be written immediately after reset. The configuration
registers are located at $001E and $001F. The configuration register
may be read at anytime.

Configuration Register (CONFIG)

Technical Data

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Configuration Register (CONFIG)

MOTOROLA

NOTE:

To ensure correct operation of the MCU under all operating conditions,
the user must write data $1C to address $0033 immediately after reset.
This is to ensure proper termination of an unused module within the
MCU.

NOTE:

On a FLASH device, the options except LVI5OR3 are one-time writeable
by the user after each reset. The LVI5OR3 bit is one-time writeable by
the user only after each POR (power-on reset). The CONFIG registers
are not in the FLASH memory but are special registers containing one-
time writeable latches after each reset. Upon a reset, the CONFIG
registers default to predetermined settings as shown in

Figure 8-1

and

Figure 8-2

Address:

$001E

Bit 7

Bit 0

Read:

OSC-

STOPEN

SCIBD-

SRC

Write:

Reset:

= Unimplemented

Figure 8-1. Configuration Register 2 (CONFIG2)

Address:

$001F

Bit 7

Bit 0

Read:

COPRS

LVISTOP LVIRSTD

LVIP-

WRD

LVI5OR3

SSREC

STOP

COPD

Write:

Reset:

See Note

Note: LVI5OR3 bit is only reset via POR (power-on reset)

Figure 8-2. Configuration Register 1 (CONFIG1)

Configuration Register (CONFIG)

Functional Description

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131

OSCSTOPENB-- Oscillator Stop Mode Enable Bar Bit

OSCSTOPENB enables the oscillator to continue operating during stop
mode. Setting the OSCSTOPENB bit allows the oscillator to operate
continuously even during stop mode. This is useful for driving the
timebase module to allow it to generate periodic wakeup while in stop
mode. (See

Clock Generator Module (CGM)

subsection

Stop Mode

1 = Oscillator enabled to operate during stop mode
0 = Oscillator disabled during stop mode (default)

SCIBDSRC -- SCI Baud Rate Clock Source Bit

SCIBDSRC controls the clock source used for the SCI. The setting of
this bit affects the frequency at which the SCI operates.

1 = Internal data bus clock used as clock source for SCI
0 = External oscillator used as clock source for SCI

COPRS -- COP Rate Select Bit

COPRS selects the COP timeout period. Reset clears COPRS. See

Computer Operating Properly (COP)

1 = COP timeout period = 2

� 2

CGMXCLK cycles

0 = COP timeout period = 2

� 2

CGMXCLK cycles

LVISTOP -- LVI Enable in Stop Mode Bit

When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. See

Stop

Mode

1 = LVI enabled during stop mode
0 = LVI disabled during stop mode

LVIRSTD -- LVI Reset Disable Bit

LVIRSTD disables the reset signal from the LVI module. See

Low-

Voltage Inhibit (LVI)

1 = LVI module resets disabled
0 = LVI module resets enabled

LVIPWRD -- LVI Power Disable Bit

LVIPWRD disables the LVI module. See

Low-Voltage Inhibit (LVI)

1 = LVI module power disabled
0 = LVI module power enabled

Configuration Register (CONFIG)

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Configuration Register (CONFIG)

MOTOROLA

LVI5OR3 -- LVI 5V or 3V Operating Mode Bit

LVI5OR3 selects the voltage operating mode of the LVI module. See

Low-Voltage Inhibit (LVI)

. The voltage mode selected for the LVI

should match the operating V

. See

Electrical Specifications

for the

LVI's voltage trip points for each of the modes.

1 = LVI operates in 5V mode.
0 = LVI operates in 3V mode.

SSREC -- Short Stop Recovery Bit

SSREC enables the CPU to exit stop mode with a delay of 32
CGMXCLK cycles instead of a 4096-CGMXCLK cycle delay.

1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLKC cycles

NOTE:

Exiting stop mode by pulling reset will result in the long stop recovery.
If using an external crystal oscillator, do not set the SSREC bit.

NOTE:

When the LVISTOP is enabled, the system stabilization time for power
on reset and long stop recovery (both 4096 CGMXCLK cycles) gives a
delay longer than the enable time for the LVI. There is no period where
the MCU is not protected from a low power condition. However, when
using the short stop recovery configuration option, the 32-CGMXCLK
delay is less than the LVI's turn-on time and there exists a period in
startup where the LVI is not protecting the MCU.

STOP -- STOP Instruction Enable Bit

STOP enables the STOP instruction.

1 = STOP instruction enabled
0 = STOP instruction treated as illegal opcode

COPD -- COP Disable Bit

COPD disables the COP module. See

Computer Operating Properly

(COP)

1 = COP module disabled
0 = COP module enabled

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Technical Data -- MC68HC908GR8

Section 9. Computer Operating Properly (COP)

9.1 Contents

9.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

9.4

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

9.5

COP Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.6

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

9.7

Monitor Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

9.8

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137

9.9

COP Module During Break Mode . . . . . . . . . . . . . . . . . . . . . .137

9.2 Introduction

The computer operating properly (COP) module contains a free-running
counter that generates a reset if allowed to overflow. The COP module
helps software recover from runaway code. Prevent a COP reset by
clearing the COP counter periodically. The COP module can be disabled
through the COPD bit in the CONFIG register.

9.3 Functional Description

Figure 9-1

shows the structure of the COP module.

Computer Operating Properly (COP)

Technical Data

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134

Computer Operating Properly (COP)

MOTOROLA

Figure 9-1. COP Block Diagram

The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2

� 2

or 2

� 2

CGMXCLK cycles, depending on the state of the COP rate select bit,
COPRS, in the configuration register. With a 2

� 2

CGMXCLK cycle

overflow option, a 32.768-kHz crystal gives a COP timeout period of
250 ms. Writing any value to location $FFFF before an overflow occurs
prevents a COP reset by clearing the COP counter and stages 12
through 5 of the prescaler.

NOTE:

Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.

A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the reset status register (RSR).

COPCTL WRITE

CGMXCLK

RESET VECTOR FETCH

RESET CIRCUIT

RESET STATUS REGISTER

INTERNAL RESET SOURCES

EAR

STAG

ES 5

�

12-BIT COP PRESCALER

EAR

ALL STAG

6-BIT COP COUNTER

COP DISABLE

RESET

COPCTL WRITE

CLEAR

COP MODULE

COPEN (FROM SIM)

COP COUNTER

COP CLOCK

I
M

STOP INSTRUCTION

(FROM CONFIG)

COP RATE SEL

(FROM CONFIG)

Computer Operating Properly (COP)

I/O Signals

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Computer Operating Properly (COP)

135

In monitor mode, the COP is disabled if the RST pin or the IRQ1 is held
at V

TST

. During the break state, V

TST

on the RST pin disables the COP.

NOTE:

Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.

9.4 I/O Signals

The following paragraphs describe the signals shown in

Figure 9-1

9.4.1 CGMXCLK

CGMXCLK is the crystal oscillator output signal. CGMXCLK frequency
is equal to the crystal frequency.

9.4.2 STOP Instruction

The STOP instruction clears the COP prescaler.

9.4.3 COPCTL Write

Writing any value to the COP control register (COPCTL) (see

COP

Control Register

) clears the COP counter and clears bits 12 through 5 of

the prescaler. Reading the COP control register returns the low byte of
the reset vector.

9.4.4 Power-On Reset

The power-on reset (POR) circuit clears the COP prescaler 4096
CGMXCLK cycles after power-up.

9.4.5 Internal Reset

An internal reset clears the COP prescaler and the COP counter.

Computer Operating Properly (COP)

Monitor Mode

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137

9.7 Monitor Mode

When monitor mode is entered with V

TST

on the IRQ pin, the COP is

disabled as long as V

TST

remains on the IRQ pin or the RST pin. When

monitor mode is entered by having blank reset vectors and not having
V

TST

on the IRQ pin, the COP is automatically disabled until a POR

occurs.

9.8 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.

9.8.1 Wait Mode

The COP remains active during wait mode. To prevent a COP reset
during wait mode, periodically clear the COP counter in a CPU interrupt
routine.

9.8.2 Stop Mode

To prevent inadvertently turning off the COP with a STOP instruction, a
configuration option is available that disables the STOP instruction.
When the STOP bit in the configuration register has the STOP
instruction disabled, execution of a STOP instruction results in an illegal
opcode reset.

9.9 COP Module During Break Mode

The COP is disabled during a break interrupt when V

TST

is present on

the RST pin.

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Central Processing Unit (CPU)

139

Technical Data -- MC68HC908GR8

Section 10. Central Processing Unit (CPU)

10.1 Contents

10.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

10.4

CPU registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

10.5

Arithmetic/logic unit (ALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . 145

10.6

Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145

10.7

CPU during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 146

10.8

Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

10.9

Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154

10.2 Introduction

The M68HC08 CPU (central processor unit) is an enhanced and fully
object-code-compatible version of the M68HC05 CPU. The CPU08
Reference Manual (Motorola document order number CPU08RM/AD)
contains a description of the CPU instruction set, addressing modes,
and architecture.

10.3 Features

�

Object code fully upward-compatible with M68HC05 Family

�

16-bit stack pointer with stack manipulation instructions

�

16-bit index register with x-register manipulation instructions

�

8-MHz CPU internal bus frequency

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

142

Central Processing Unit (CPU)

MOTOROLA

10.4.3 Stack pointer (SP)

The stack pointer is a 16-bit register that contains the address of the next
location on the stack. During a reset, the stack pointer is preset to
$00FF. The reset stack pointer (RSP) instruction sets the least
significant byte to $FF and does not affect the most significant byte. The
stack pointer decrements as data is pushed onto the stack and
increments as data is pulled from the stack.

In the stack pointer 8-bit offset and 16-bit offset addressing modes, the
stack pointer can function as an index register to access data on the
stack. The CPU uses the contents of the stack pointer to determine the
conditional address of the operand.

NOTE:

The location of the stack is arbitrary and may be relocated anywhere in
RAM. Moving the SP out of page zero ($0000 to $00FF) frees direct
address (page zero) space. For correct operation, the stack pointer must
point only to RAM locations.

10.4.4 Program counter (PC)

The program counter is a 16-bit register that contains the address of the
next instruction or operand to be fetched.

Normally, the program counter automatically increments to the next
sequential memory location every time an instruction or operand is
fetched. Jump, branch, and interrupt operations load the program
counter with an address other than that of the next sequential location.

Bit
15

Bit

Read:

Write:

Reset:

Figure 10-4. Stack pointer (SP)

Central Processing Unit (CPU)

CPU registers

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

143

During reset, the program counter is loaded with the reset vector
address located at $FFFE and $FFFF. The vector address is the
address of the first instruction to be executed after exiting the reset state.

10.4.5 Condition code register (CCR)

The 8-bit condition code register contains the interrupt mask and five
flags that indicate the results of the instruction just executed. Bits 6 and
5 are set permanently to `1'. The following paragraphs describe the
functions of the condition code register.

V -- Overflow flag

The CPU sets the overflow flag when a two's complement overflow
occurs. The signed branch instructions BGT, BGE, BLE, and BLT use
the overflow flag.

1 = Overflow
0 = No overflow

H -- Half-carry flag

Bit
15

Bit

Read:

Write:

Reset:

Loaded with vector from $FFFE and $FFFF

Figure 10-5. Program counter (PC)

Bit 7

Bit 0

CCR

Read:

Write:

Reset:

X = Indeterminate

Figure 10-6. Condition code register (CCR)

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

144

Central Processing Unit (CPU)

MOTOROLA

The CPU sets the half-carry flag when a carry occurs between
accumulator bits 3 and 4 during an ADD or ADC operation. The half-
carry flag is required for binary-coded decimal (BCD) arithmetic
operations. The DAA instruction uses the states of the H and C flags
to determine the appropriate correction factor.

1 = Carry between bits 3 and 4
0 = No carry between bits 3 and 4

I -- Interrupt mask

When the interrupt mask is set, all maskable CPU interrupts are
disabled. CPU interrupts are enabled when the interrupt mask is
cleared. When a CPU interrupt occurs, the interrupt mask is set
automatically after the CPU registers are saved on the stack, but
before the interrupt vector is fetched.

1 = Interrupts disabled
0 = Interrupts enabled

NOTE:

To maintain M6805 compatibility, the upper byte of the index register (H)
is not stacked automatically. If the interrupt service routine modifies H,
then the user must stack and unstack H using the PSHH and PULH
instructions.

After the I bit is cleared, the highest-priority interrupt request is
serviced first.

A return from interrupt (RTI) instruction pulls the CPU registers from the
stack and restores the interrupt mask from the stack. After any reset, the
interrupt mask is set and can only be cleared by the clear interrupt mask
software instruction (CLI).

Central Processing Unit (CPU)

Arithmetic/logic unit (ALU)

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

145

N -- Negative flag

The CPU sets the negative flag when an arithmetic operation, logic
operation, or data manipulation produces a negative result, setting bit
7 of the result.

1 = Negative result
0 = Non-negative result

Z -- Zero flag

The CPU sets the zero flag when an arithmetic operation, logic
operation, or data manipulation produces a result of $00.

1 = Zero result
0 = Non-zero result

C -- Carry/borrow flag

The CPU sets the carry/borrow flag when an addition operation
produces a carry out of bit 7 of the accumulator or when a subtraction
operation requires a borrow. Some instructions - such as bit test and
branch, shift, and rotate - also clear or set the carry/borrow flag.

1 = Carry out of bit 7
0 = No carry out of bit 7

10.5 Arithmetic/logic unit (ALU)

The ALU performs the arithmetic and logic operations defined by the
instruction set.

Refer to the CPU08 Reference Manual (Motorola document number
CPU08RM/AD) for a description of the instructions and addressing
modes and more detail about CPU architecture.

10.6 Low-power modes

The WAIT and STOP instructions put the MCU in low--power
consumption standby modes.

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

146

Central Processing Unit (CPU)

MOTOROLA

10.6.1 WAIT mode

The WAIT instruction:

�

clears the interrupt mask (I bit) in the condition code register,
enabling interrupts. After exit from WAIT mode by interrupt, the I
bit remains clear. After exit by reset, the I bit is set.

�

Disables the CPU clock

10.6.2 STOP mode

The STOP instruction:

�

clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from STOP mode by
external interrupt, the I bit remains clear. After exit by reset, the I
bit is set.

�

Disables the CPU clock

After exiting STOP mode, the CPU clock begins running after the
oscillator stabilization delay.

10.7 CPU during break interrupts

If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. See

Break Module (BRK)

. The program counter

vectors to $FFFC�$FFFD ($FEFC�$FEFD in monitor mode).

A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.

Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

147

10.8 Instruction Set Summary

Table 10-1

provides a summary of the M68HC08 instruction set.

Table 10-1. Instruction Set Summary

Source

Form

Operation

Description

Effect on

CCR

r
ess

ode

r
a

Cycle

V H I N Z C

ADC #opr
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
ADC opr,SP
ADC opr,SP

Add with Carry

(A) + (M) + (C)

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A9
B9
C9
D9
E9
F9

9EE9
9ED9

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
ADD opr,SP
ADD opr,SP

Add without Carry

(A) + (M)

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

AB
BB
CB
DB
EB
FB

9EEB
9EDB

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

AIS #opr

Add Immediate Value (Signed) to SP

(SP) + (16

�

� � � � � � IMM

ii 2

AIX #opr

Add Immediate Value (Signed) to H:X

H:X

(H:X) + (16

�

� � � � � � IMM

AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
AND opr,SP
AND opr,SP

Logical AND

(A) & (M)

0 � �

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A4
B4
C4
D4
E4
F4

9EE4
9ED4

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
ASL opr,SP

Arithmetic Shift Left
(Same as LSL)

� �

DIR
INH
INH
IX1
IX
SP1

38
48
58
68
78

9E68

4
1
1
4
3
5

ASR opr
ASRA
ASRX
ASR opr,X
ASR opr,X
ASR opr,SP

Arithmetic Shift Right

� �

DIR
INH
INH
IX1
IX
SP1

37
47
57
67
77

9E67

4
1
1
4
3
5

BCC rel

Branch if Carry Bit Clear

(PC) + 2 + rel ? (C) = 0

� � � � � � REL

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

148

Central Processing Unit (CPU)

MOTOROLA

BCLR n, opr

Clear Bit n in M

� � � � � �

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

13
15
17
19

1B
1D
1F

dd
dd
dd
dd
dd
dd
dd
dd

4
4
4
4
4
4
4
4

BCS rel

Branch if Carry Bit Set (Same as BLO)

(PC) + 2 + rel ? (C) = 1

� � � � � � REL

BEQ rel

Branch if Equal

(PC) + 2 + rel ? (Z) = 1

� � � � � � REL

BGE opr

Branch if Greater Than or Equal To
(Signed Operands)

(PC) + 2 + rel ? (N

) = 0

� � � � � � REL

BGT opr

Branch if Greater Than (Signed
Operands)

(PC) + 2 + rel ? (Z)

| (N

) = 0

� � � � � � REL

BHCC rel

Branch if Half Carry Bit Clear

(PC) + 2 + rel ? (H) = 0

� � � � � � REL

BHCS rel

Branch if Half Carry Bit Set

(PC) + 2 + rel ? (H) = 1

� � � � � � REL

BHI rel

Branch if Higher

(PC) + 2 + rel ? (C) | (Z) = 0

� � � � � � REL

BHS rel

Branch if Higher or Same
(Same as BCC)

(PC) + 2 + rel ? (C) = 0

� � � � � � REL

BIH rel

Branch if IRQ Pin High

(PC) + 2 + rel ? IRQ = 1

� � � � � � REL

BIL rel

Branch if IRQ Pin Low

(PC) + 2 + rel ? IRQ = 0

� � � � � � REL

BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
BIT opr,SP
BIT opr,SP

Bit Test

(A) & (M)

0 � �

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A5
B5
C5
D5
E5
F5

9EE5
9ED5

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

BLE opr

Branch if Less Than or Equal To
(Signed Operands)

(PC) + 2 + rel ? (Z)

| (N

) =

1 � � � � � � REL

BLO rel

Branch if Lower (Same as BCS)

(PC) + 2 + rel ? (C) = 1

� � � � � � REL

BLS rel

Branch if Lower or Same

(PC) + 2 + rel ? (C) | (Z) = 1

� � � � � � REL

BLT opr

Branch if Less Than (Signed Operands)

(PC) + 2 + rel ? (N

) =

� � � � � � REL

BMC rel

Branch if Interrupt Mask Clear

(PC) + 2 + rel ? (I) = 0

� � � � � � REL

BMI rel

Branch if Minus

(PC) + 2 + rel ? (N) = 1

� � � � � � REL

BMS rel

Branch if Interrupt Mask Set

(PC) + 2 + rel ? (I) = 1

� � � � � � REL

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

149

BNE rel

Branch if Not Equal

(PC) + 2 + rel ? (Z) = 0

� � � � � � REL

BPL rel

Branch if Plus

(PC) + 2 + rel ? (N) = 0

� � � � � � REL

BRA rel

Branch Always

(PC) + 2 + rel

� � � � � � REL

BRCLR n,opr,rel Branch if Bit n in M Clear

(PC) + 3 + rel ? (Mn) = 0

� � � � �

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

01
03
05
07
09

0B
0D
0F

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

5
5
5
5
5
5
5
5

BRN rel

Branch Never

(PC) + 2

� � � � � � REL

BRSET n,opr,rel Branch if Bit n in M Set

(PC) + 3 + rel ? (Mn) = 1

� � � � �

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

00
02
04
06
08

0A
0C
0E

dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr
dd rr

5
5
5
5
5
5
5
5

BSET n,opr

Set Bit n in M

� � � � � �

DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)

10
12
14
16
18

1A
1C
1E

dd
dd
dd
dd
dd
dd
dd
dd

4
4
4
4
4
4
4
4

BSR rel

Branch to Subroutine

(PC) + 2; push (PCL)

(SP) � 1; push (PCH)

(SP) � 1

(PC) + rel

� � � � � � REL

CBEQ opr,rel
CBEQA #opr,rel
CBEQX #opr,rel
CBEQ opr,X+,rel
CBEQ X+,rel
CBEQ opr,SP,rel

Compare and Branch if Equal

(PC) + 3 + rel ? (A) � (M) = $00

(PC) + 3 + rel ? (X) � (M) = $00

(PC) + 3 + rel ? (A) � (M) = $00

(PC) + 2 + rel ? (A) � (M) = $00

(PC) + 4 + rel ? (A) � (M) = $00

� � � � � �

DIR
IMM
IMM
IX1+
IX+
SP1

31
41
51
61
71

9E61

dd rr
ii rr
ii rr
ff rr
rr
ff rr

5
4
4
5
4
6

CLC

Clear Carry Bit

� � � � � 0 INH

CLI

Clear Interrupt Mask

� � 0 � � � INH

CLR opr
CLRA
CLRX
CLRH
CLR opr,X
CLR ,X
CLR opr,SP

Clear

$00

0 � � 0 1 �

DIR
INH
INH
INH
IX1
IX
SP1

3F
4F
5F

6F
7F

9E6F

3
1
1
1
3
2
4

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

150

Central Processing Unit (CPU)

MOTOROLA

CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
CMP opr,SP
CMP opr,SP

Compare A with M

(A) � (M)

� �

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A1
B1
C1
D1
E1
F1

9EE1
9ED1

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

COM opr
COMA
COMX
COM opr,X
COM ,X
COM opr,SP

Complement (One's Complement)

(M) = $FF � (M)

(A) = $FF � (M)

(X) = $FF � (M)

(M) = $FF � (M)

0 � �

DIR
INH
INH
IX1
IX
SP1

33
43
53
63
73

9E63

4
1
1
4
3
5

CPHX #opr
CPHX opr

Compare H:X with M

(H:X) � (M:M + 1)

� �

IMM
DIR

65
75

ii ii+1
dd

3
4

CPX #opr
CPX opr
CPX opr
CPX ,X
CPX opr,X
CPX opr,X
CPX opr,SP
CPX opr,SP

Compare X with M

(X) � (M)

� �

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A3
B3
C3
D3
E3
F3

9EE3
9ED3

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

DAA

Decimal Adjust A

(A)

U � �

INH

DBNZ opr,rel
DBNZA rel
DBNZX rel
DBNZ opr,X,rel
DBNZ X,rel
DBNZ opr,SP,rel

Decrement and Branch if Not Zero

(A) � 1 or M

(M) � 1 or X

(X) � 1

(PC) + 3 + rel ? (result)

(PC) + 2 + rel ? (result)

(PC) + 3 + rel ? (result)

(PC) + 2 + rel ? (result)

(PC) + 4 + rel ? (result)

� � � � � �

DIR
INH
INH
IX1
IX
SP1

3B
4B
5B
6B
7B

9E6B

dd rr
rr
rr
ff rr
rr
ff rr

5
3
3
5
4
6

DEC opr
DECA
DECX
DEC opr,X
DEC ,X
DEC opr,SP

Decrement

(M) � 1

(A) � 1

(X) � 1

(M) � 1

� �

�

DIR
INH
INH
IX1
IX
SP1

3A
4A
5A
6A
7A

9E6A

4
1
1
4
3
5

DIV

Divide

(H:A)/(X)

Remainder

� � � �

INH

EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
EOR opr,SP
EOR opr,SP

Exclusive OR M with A

0 � �

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A8
B8
C8
D8
E8
F8

9EE8
9ED8

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

151

INC opr
INCA
INCX
INC opr,X
INC ,X
INC opr,SP

Increment

(M) + 1

(A) + 1

(X) + 1

(M) + 1

� �

�

DIR
INH
INH
IX1
IX
SP1

3C
4C
5C
6C
7C

9E6C

4
1
1
4
3
5

JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X

Jump

Jump Address

� � � � � �

DIR
EXT
IX2
IX1
IX

BC
CC
DC
EC
FC

dd
hh ll
ee ff
ff

2
3
4
3
2

JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X

Jump to Subroutine

(PC) + n (n = 1, 2, or 3)

Push (PCL); SP

(SP) � 1

Push (PCH); SP

(SP) � 1

Unconditional Address

� � � � � �

DIR
EXT
IX2
IX1
IX

BD
CD
DD
ED
FD

dd
hh ll
ee ff
ff

4
5
6
5
4

LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDA opr,SP
LDA opr,SP

Load A from M

(M)

0 � �

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A6
B6
C6
D6
E6
F6

9EE6
9ED6

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

LDHX #opr
LDHX opr

Load H:X from M

H:X

(

M:M

+ 1

)

0 � �

�

IMM
DIR

45
55

ii jj
dd

3
4

LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LDX opr,SP
LDX opr,SP

Load X from M

(M)

0 � �

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

AE
BE
CE
DE
EE
FE

9EEE
9EDE

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSL opr,SP

Logical Shift Left
(Same as ASL)

� �

DIR
INH
INH
IX1
IX
SP1

38
48
58
68
78

9E68

4
1
1
4
3
5

LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
LSR opr,SP

Logical Shift Right

� � 0

DIR
INH
INH
IX1
IX
SP1

34
44
54
64
74

9E64

4
1
1
4
3
5

MOV opr,opr
MOV opr,X+
MOV #opr,opr
MOV X+,opr

Move

(M)

Destination

(M)

Source

H:X

(H:X) + 1 (IX+D, DIX+)

0 � �

�

DD
DIX+
IMD
IX+D

4E
5E
6E
7E

dd dd
dd
ii dd
dd

5
4
4
4

MUL

Unsigned multiply

X:A

(X)

�

(A)

� 0 � � � 0 INH

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

152

Central Processing Unit (CPU)

MOTOROLA

NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NEG opr,SP

Negate (Two's Complement)

�(M) = $00 � (M)

�(A) = $00 � (A)

�(X) = $00 � (X)

�(M) = $00 � (M)

� �

DIR
INH
INH
IX1
IX
SP1

30
40
50
60
70

9E60

4
1
1
4
3
5

NOP

No Operation

None

� � � � � � INH

NSA

Nibble Swap A

(A[3:0]:A[7:4])

� � � � � � INH

ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ORA opr,SP
ORA opr,SP

Inclusive OR A and M

(A) | (M)

0 � �

�

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

AA
BA
CA
DA
EA

9EEA
9EDA

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

PSHA

Push A onto Stack

Push (A); SP

(SP

) �

� � � � � � INH

PSHH

Push H onto Stack

Push (H)

;

(SP

) �

� � � � � � INH

PSHX

Push X onto Stack

Push (X)

;

(SP

) �

� � � � � � INH

PULA

Pull A from Stack

(SP +

1); Pull

(

)

� � � � � � INH

PULH

Pull H from Stack

(SP +

1); Pull

(

)

� � � � � � INH

PULX

Pull X from Stack

(SP +

1); Pull

(

)

� � � � � � INH

ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
ROL opr,SP

Rotate Left through Carry

� �

DIR
INH
INH
IX1
IX
SP1

39
49
59
69
79

9E69

4
1
1
4
3
5

ROR opr
RORA
RORX
ROR opr,X
ROR ,X
ROR opr,SP

Rotate Right through Carry

� �

DIR
INH
INH
IX1
IX
SP1

36
46
56
66
76

9E66

4
1
1
4
3
5

RSP

Reset Stack Pointer

$FF

� � � � � � INH

RTI

Return from Interrupt

(SP) + 1; Pull (CCR)

(SP) + 1; Pull (A)

(SP) + 1; Pull (X)

(SP) + 1; Pull (PCH)

(SP) + 1; Pull (PCL)

INH

RTS

Return from Subroutine

SP + 1

;

Pull

(

PCH)

SP + 1; Pull (PCL)

� � � � � � INH

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

Central Processing Unit (CPU)

Instruction Set Summary

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Central Processing Unit (CPU)

153

SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
SBC opr,SP
SBC opr,SP

Subtract with Carry

(A) � (M) � (C)

� �

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A2
B2
C2
D2
E2
F2

9EE2
9ED2

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

SEC

Set Carry Bit

� � � � � 1 INH

SEI

Set Interrupt Mask

� � 1 � � � INH

STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
STA opr,SP
STA opr,SP

Store A in M

(A)

0 � �

�

DIR
EXT
IX2
IX1
IX
SP1
SP2

B7
C7
D7
E7
F7

9EE7
9ED7

dd
hh ll
ee ff
ff

ff
ee ff

3
4
4
3
2
4
5

STHX opr

Store H:X in M

(M:M + 1)

(H:X)

0 � �

� DIR

STOP

Enable IRQ Pin; Stop Oscillator

0; Stop Oscillator

� � 0 � � � INH

STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
STX opr,SP
STX opr,SP

Store X in M

(X)

0 � �

�

DIR
EXT
IX2
IX1
IX
SP1
SP2

BF
CF
DF
EF
FF

9EEF
9EDF

dd
hh ll
ee ff
ff

ff
ee ff

3
4
4
3
2
4
5

SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
SUB opr,SP
SUB opr,SP

Subtract A

(A)

�

(M)

� �

IMM
DIR
EXT
IX2
IX1
IX
SP1
SP2

A0
B0
C0
D0
E0
F0

9EE0
9ED0

ii
dd
hh ll
ee ff
ff

ff
ee ff

2
3
4
4
3
2
4
5

SWI

Software Interrupt

(PC) + 1; Push (PCL)

(SP) � 1; Push (PCH)

(SP) � 1; Push (X)

(SP) � 1; Push (A)

(SP) � 1; Push (CCR)

(SP) � 1; I

PCH

Interrupt Vector High Byte

PCL

Interrupt Vector Low Byte

� � 1 � � � INH

TAP

Transfer A to CCR

CCR

(A)

INH

TAX

Transfer A to X

(A)

� � � � � � INH

TPA

Transfer CCR to A

(CCR)

� � � � � � INH

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

Central Processing Unit (CPU)

Technical Data

MC68HC908GR8 -- Rev 4.0

154

Central Processing Unit (CPU)

MOTOROLA

10.9 Opcode Map

See

Table 10-2

TST opr
TSTA
TSTX
TST opr,X
TST ,X
TST opr,SP

Test for Negative or Zero

(A) � $00 or (X) � $00 or (M) � $00

0 � �

�

DIR
INH
INH
IX1
IX
SP1

3D
4D
5D
6D
7D

9E6D

3
1
1
3
2
4

TSX

Transfer SP to H:X

H:X

(SP) + 1

� � � � � � INH

TXA

Transfer X to A

(X)

� � � � � � INH

TXS

Transfer H:X to SP

(SP)

(H:X) � 1

� � � � � � INH

A Accumulatorn

Any bit

C Carry/borrow bitopr

Operand (one or two bytes)

CCRCondition code registerPC

Program counter

ddDirect address of operandPCH

Program counter high byte

dd rrDirect address of operand and relative offset of branch instructionPCL

Program counter low byte

DDDirect to direct addressing modeREL

Relative addressing mode

DIRDirect addressing moderel

Relative program counter offset byte

DIX+Direct to indexed with post increment addressing moderr

Relative program counter offset byte

ee ffHigh and low bytes of offset in indexed, 16-bit offset addressingSP1

Stack pointer, 8-bit offset addressing mode

EXTExtended addressing modeSP2

Stack pointer 16-bit offset addressing mode

ff Offset byte in indexed, 8-bit offset addressingSP

Stack pointer

H Half-carry bitU

Undefined

H Index register high byteV

Overflow bit

hh llHigh and low bytes of operand address in extended addressingX

Index register low byte

I Interrupt maskZ

Zero bit

ii Immediate operand byte&

Logical AND

IMDImmediate source to direct destination addressing mode|

Logical OR

IMMImmediate addressing mode

Logical EXCLUSIVE OR

INHInherent addressing mode( )

Contents of

IXIndexed, no offset addressing mode�( )

Negation (two's complement)

IX+Indexed, no offset, post increment addressing mode#

Immediate value

IX+DIndexed with post increment to direct addressing mode

�

Sign extend

IX1Indexed, 8-bit offset addressing mode

Loaded with

IX1+Indexed, 8-bit offset, post increment addressing mode?

IX2Indexed, 16-bit offset addressing mode:

Concatenated with

MMemory location

Set or cleared

N Negative bit--

Not affected

Table 10-1. Instruction Set Summary (Continued)

Source

Form

Operation

Description

Effect on

CCR

Addr

ode

Opc

ode

Ope

r
a

Cyc

l
es

V H I N Z C

hni
c

l D
a

MC6

HC9

08G

--
Re

.
0

t
r
a

l Pr

oc
es
si

ng
U
n

i
t
(

)

Centr

l Pr

ocessi

ng
Un

i
t
(CPU)

Bit Manipulation

Branch

Read-Modify-Write

Control

Register/Memory

DIR

REL

DIR

INH

IX1

SP1

INH

IMM

DIR

EXT

IX2

SP2

IX1

SP1

9E6

9ED

9EE

BRSET0
3

DIR

BSET0

DIR

BRA

REL

NEG

DIR

NEGA

INH

NEGX

INH

NEG

IX1

NEG

SP1

NEG

RTI

INH

BGE

REL

SUB

IMM

SUB

DIR

SUB

EXT

SUB

IX2

SUB

SP2

SUB

IX1

SUB

SP1

SUB

BRCLR0
3

DIR

BCLR0

DIR

BRN

REL

CBEQ

DIR

CBEQA

IMM

CBEQX

IMM

CBEQ

3 IX1+

CBEQ

SP1

CBEQ

IX+

RTS

INH

BLT

REL

CMP

IMM

CMP

DIR

CMP

EXT

CMP

IX2

CMP

SP2

CMP

IX1

CMP

SP1

CMP

BRSET1
3

DIR

BSET1

DIR

BHI

REL

MUL

INH

DIV

INH

NSA

INH

DAA

INH

BGT

REL

SBC

IMM

SBC

DIR

SBC

EXT

SBC

IX2

SBC

SP2

SBC

IX1

SBC

SP1

SBC

BRCLR1
3

DIR

BCLR1

DIR

BLS

REL

COM

DIR

COMA

INH

COMX

INH

COM

IX1

COM

SP1

COM

SWI

INH

BLE

REL

CPX

IMM

CPX

DIR

CPX

EXT

CPX

IX2

CPX

SP2

CPX

IX1

CPX

SP1

CPX

BRSET2
3

DIR

BSET2

DIR

BCC

REL

LSR

DIR

LSRA

INH

LSRX

INH

LSR

IX1

LSR

SP1

LSR

TAP

INH

TXS

INH

AND

IMM

AND

DIR

AND

EXT

AND

IX2

AND

SP2

AND

IX1

AND

SP1

AND

BRCLR2
3

DIR

BCLR2

DIR

BCS

REL

STHX

DIR

LDHX

IMM

LDHX

DIR

CPHX

IMM

CPHX

DIR

TPA

INH

TSX

INH

BIT

IMM

BIT

DIR

BIT

EXT

BIT

IX2

BIT

SP2

BIT

IX1

BIT

SP1

BIT

BRSET3
3

DIR

BSET3

DIR

BNE

REL

ROR

DIR

RORA

INH

RORX

INH

ROR

IX1

ROR

SP1

ROR

PULA

INH

LDA

IMM

LDA

DIR

LDA

EXT

LDA

IX2

LDA

SP2

LDA

IX1

LDA

SP1

LDA

BRCLR3
3

DIR

BCLR3

DIR

BEQ

REL

ASR

DIR

ASRA

INH

ASRX

INH

ASR

IX1

ASR

SP1

ASR

PSHA

INH

TAX

INH

AIS

IMM

STA

DIR

STA

EXT

STA

IX2

STA

SP2

STA

IX1

STA

SP1

STA

BRSET4
3

DIR

BSET4

DIR

BHCC

REL

LSL

DIR

LSLA

INH

LSLX

INH

LSL

IX1

LSL

SP1

LSL

PULX

INH

CLC

INH

EOR

IMM

EOR

DIR

EOR

EXT

EOR

IX2

EOR

SP2

EOR

IX1

EOR

SP1

EOR

BRCLR4
3

DIR

BCLR4

DIR

BHCS

REL

ROL

DIR

ROLA

INH

ROLX

INH

ROL

IX1

ROL

SP1

ROL

PSHX

INH

SEC

INH

ADC

IMM

ADC

DIR

ADC

EXT

ADC

IX2

ADC

SP2

ADC

IX1

ADC

SP1

ADC

BRSET5
3

DIR

BSET5

DIR

BPL

REL

DEC

DIR

DECA

INH

DECX

INH

DEC

IX1

DEC

SP1

DEC

PULH

INH

CLI

INH

ORA

IMM

ORA

DIR

ORA

EXT

ORA

IX2

ORA

SP2

ORA

IX1

ORA

SP1

ORA

BRCLR5
3

DIR

BCLR5

DIR

BMI

REL

DBNZ

DIR

DBNZA

INH

DBNZX

INH

DBNZ

IX1

DBNZ

SP1

DBNZ

PSHH

INH

SEI

INH

ADD

IMM

ADD

DIR

ADD

EXT

ADD

IX2

ADD

SP2

ADD

IX1

ADD

SP1

ADD

BRSET6
3

DIR

BSET6

DIR

BMC

REL

INC

DIR

INCA

INH

INCX

INH

INC

IX1

INC

SP1

INC

CLRH

INH

RSP

INH

JMP

DIR

JMP

EXT

JMP

IX2

JMP

IX1

JMP

BRCLR6
3

DIR

BCLR6

DIR

BMS

REL

TST

DIR

TSTA

INH

TSTX

INH

TST

IX1

TST

SP1

TST

NOP

INH

BSR

REL

JSR

DIR

JSR

EXT

JSR

IX2

JSR

IX1

JSR

BRSET7
3

DIR

BSET7

DIR

BIL

REL

MOV

2 DIX+

MOV

IMD

MOV

2 IX+D

STOP

INH

LDX

IMM

LDX

DIR

LDX

EXT

LDX

IX2

LDX

SP2

LDX

IX1

LDX

SP1

LDX

BRCLR7
3

DIR

BCLR7

DIR

BIH

REL

CLR

DIR

CLRA

INH

CLRX

INH

CLR

IX1

CLR

SP1

CLR

WAIT

INH

TXA

INH

AIX

IMM

STX

DIR

STX

EXT

STX

IX2

STX

SP2

STX

IX1

STX

SP1

STX

INH Inherent

REL Relative

SP1 Stack Pointer, 8-Bit Offset

IMM Immediate

Indexed, No Offset

SP2 Stack Pointer, 16-Bit Offset

DIR Direct

IX1

Indexed, 8-Bit Offset

IX+

Indexed, No Offset with

EXT Extended

IX2

Indexed, 16-Bit Offset

Post Increment

Direct-Direct

IMD Immediate-Direct

IX1+ Indexed, 1-Byte Offset with

IX+D Indexed-Direct

DIX+ Direct-Indexed

Post Increment

Pre-byte for stack pointer indexed instructions

High Byte of Opcode in Hexadecimal

Low Byte of Opcode in Hexadecimal

BRSET0
3

DIR

Cycles
Opcode Mnemonic
Number of Bytes / Addressing Mode

Table 10-2. Opcode Map

MSB

LSB

MSB

LSB

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Flash Memory

157

Technical Data -- MC68HC908GR8

Section 11. Flash Memory

11.1 Contents

11.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

11.4

FLASH Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159

11.5

FLASH Page Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 160

11.6

FLASH Mass Erase Operation . . . . . . . . . . . . . . . . . . . . . . . . 161

11.7

FLASH Program/Read Operation . . . . . . . . . . . . . . . . . . . . . .162

11.8

FLASH Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163

11.9

Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.10 STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

11.2 Introduction

This section describes the operation of the embedded FLASH memory.
This memory can be read, programmed, and erased from a single
external supply. The program, erase, and read operations are enabled
through the use of an internal charge pump.

11.3 Functional Description

The FLASH memory is an array of 7,680 bytes for the MC68HC908GR8
or 4,096 bytes for the MC68HC908GR4 with an additional 36 bytes of
user vectors and one byte used for block protection. An erased bit reads
as logic 1 and a programmed bit reads as a logic 0. The program and
erase operations are facilitated through control bits in the Flash Control

Flash Memory

FLASH Control Register

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Flash Memory

159

11.4 FLASH Control Register

The FLASH control register (FLCR) controls FLASH program and erase
operations.

HVEN -- High-Voltage Enable Bit

This read/write bit enables the charge pump to drive high voltages for
program and erase operations in the array. HVEN can only be set if
either PGM = 1 or ERASE = 1 and the proper sequence for program
or erase is followed.

1 = High voltage enabled to array and charge pump on
0 = High voltage disabled to array and charge pump off

MASS -- Mass Erase Control Bit

Setting this read/write bit configures the 8K byte FLASH array for
mass erase operation.

1 = MASS erase operation selected
0 = MASS erase operation unselected

ERASE -- Erase Control Bit

This read/write bit configures the memory for erase operation.
ERASE is interlocked with the PGM bit such that both bits cannot be
equal to 1 or set to 1 at the same time.

1 = Erase operation selected
0 = Erase operation unselected

Address:

$FE08

Bit 7

Bit 0

Read:

HVEN

MASS

ERASE

PGM

Write:

Reset:

Figure 11-1. FLASH Control Register (FLCR)

Flash Memory

Technical Data

MC68HC908GR8 -- Rev 4.0

162

Flash Memory

MOTOROLA

11.7 FLASH Program/Read Operation

Programming of the FLASH memory is done on a row basis. A row
consists of 32 consecutive bytes starting from addresses $XX00,
$XX20, $XX40, $XX60, $XX80, $XXA0, $XXC0, and $XXE0. Use this
step-by-step procedure to program a row of FLASH memory (

Figure 11-

is a flowchart representation):

1. Set the PGM bit. This configures the memory for program

operation and enables the latching of address and data for
programming.

2. Read from the FLASH block protect register.

3. Write any data to any FLASH address within the row address

range desired.

4. Wait for a time, t

nvs

(min. 10

�

s).

5. Set the HVEN bit.

6. Wait for a time, t

pgs

(min. 5

�

s).

7. Write data to the FLASH address to be programmed.*

8. Wait for a time, t

PROG

(min. 30

�

s).

9. Repeat step 7 and 8 until all the bytes within the row are

programmed.

10. Clear the PGM bit.*

11. Wait for a time, t

nvh

(min. 5

�

s).

12. Clear the HVEN bit.

13. After time, t

rcv

(min. 1

�

s), the memory can be accessed in read

mode again.

* The time between each FLASH address change, or the time between the last FLASH address
programmed to clearing PGM bit, must not exceed the maximum programming time, t

PROG

max.

This program sequence is repeated throughout the memory until all data
is programmed.

Flash Memory

FLASH Block Protection

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Flash Memory

163

NOTE:

Programming and erasing of FLASH locations cannot be performed by
code being executed from the FLASH memory. While these operations
must be performed in the order shown, other unrelated operations may
occur between the steps. Do not exceed t

PROG

maximum. See

Memory

Characteristics.

11.8 FLASH Block Protection

Due to the ability of the on-board charge pump to erase and program the
FLASH memory in the target application, provision is made for protecting
a block of memory from unintentional erase or program operations due
to system malfunction. This protection is done by using of a FLASH
Block Protect Register (FLBPR). The FLBPR determines the range of
the FLASH memory which is to be protected. The range of the protected
area starts from a location defined by FLBPR and ends at the bottom of
the FLASH memory ($FFFF). When the memory is protected, the HVEN
bit cannot be set in either ERASE or PROGRAM operations.

NOTE:

In performing a program or erase operation, the FLASH block protect
register must be read after setting the PGM or ERASE bit and before
asserting the HVEN bit

When the FLBPR is programmed with all 0s, the entire memory is
protected from being programmed and erased. When all the bits are
erased (all 1s), the entire memory is accessible for program and erase.

When bits within the FLBPR are programmed, they lock a block of
memory with address ranges as shown in

FLASH Block Protect

. Once the FLBPR is programmed with a value other than $FF,

any erase or program of the FLBPR or the protected block of FLASH
memory is prohibited. The FLBPR itself can be erased or programmed
only with an external voltage, V

TST

, present on the IRQ pin. This voltage

also allows entry from reset into the monitor mode.

Flash Memory

FLASH Block Protection

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Flash Memory

165

11.8.1 FLASH Block Protect Register

The FLASH block protect register (FLBPR) is implemented as a byte
within the FLASH memory, and therefore can only be written during a
programming sequence of the FLASH memory. The value in this register
determines the starting location of the protected range within the FLASH
memory.

BPR[7:0] -- FLASH Block Protect Bits

These eight bits represent bits [13:6] of a 16-bit memory address.
Bits [15:14] are logic 1s and bits [5:0] are logic 0s.

The resultant 16-bit address is used for specifying the start address
of the FLASH memory for block protection. The FLASH is protected
from this start address to the end of FLASH memory, at $FFFF. With
this mechanism, the protect start address can be $XX00, $XX40,
$XX80, and $XXC0 (64 bytes page boundaries) within the FLASH
memory.

Figure 11-4. FLASH Block Protect Start Address

Address:

$FF7E

Bit 7

Bit 0

Read:

BPR7

BPR6

BPR5

BPR4

BPR3

BPR2

BPR1

BPR0

Write:

Reset:

U = Unaffected by reset. Initial value from factory is 1.
Write to this register is by a programming sequence to the FLASH memory.

Figure 11-3. FLASH Block Protect Register (FLBPR)

FLBPR value

16-bit memory address

Start address of FLASH block protect

Flash Memory

Technical Data

MC68HC908GR8 -- Rev 4.0

166

Flash Memory

MOTOROLA

Examples of protect start address:

11.9 Wait Mode

Putting the MCU into wait mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.

The WAIT instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on Standby Mode.

11.10 STOP Mode

Putting the MCU into stop mode while the FLASH is in read mode does
not affect the operation of the FLASH memory directly, but there will not
be any memory activity since the CPU is inactive.

The STOP instruction should not be executed while performing a
program or erase operation on the FLASH, otherwise the operation will
discontinue, and the FLASH will be on Standby Mode

NOTE:

Standby Mode is the power saving mode of the FLASH module in which
all internal control signals to the FLASH are inactive and the current
consumption of the FLASH is at a minimum.

Table 11-1. Examples of protect start address:

BPR[7:0]

Start of Address of Protect Range

$80

The entire FLASH memory is protected.

$81 (1000 0001)

$E040 (1110 0000 0100 0000)

$82 (1000 0010)

$E080 (1110 0000 1000 0000)

and so on...

$FE (1111 1110)

$FF80 (1111 1111 1000 0000)

$FF

The entire FLASH memory is not protected.

Note:

The end address of the protected range is always $FFFF.

External Interrupt (IRQ)

Technical Data

MC68HC908GR8 -- Rev 4.0

168

External Interrupt (IRQ)

MOTOROLA

12.4 Functional Description

A logic 0 applied to the external interrupt pin can latch a CPU interrupt
request.

Figure 12-1

shows the structure of the IRQ module.

Interrupt signals on the IRQ1 pin are latched into the IRQ latch. An
interrupt latch remains set until one of the following actions occurs:

�

Vector fetch -- A vector fetch automatically generates an interrupt
acknowledge signal that clears the latch that caused the vector
fetch.

�

Software clear -- Software can clear an interrupt latch by writing
to the appropriate acknowledge bit in the interrupt status and
control register (INTSCR). Writing a logic 1 to the ACK bit clears
the IRQ latch.

�

Reset -- A reset automatically clears the interrupt latch.

The external interrupt pin is falling-edge-triggered and is software-
configurable to be either falling-edge or falling-edge and low-level-
triggered. The MODE bit in the INTSCR controls the triggering sensitivity
of the IRQ1 pin.

When an interrupt pin is edge-triggered only, the interrupt remains set
until a vector fetch, software clear, or reset occurs.

When an interrupt pin is both falling-edge and low-level-triggered, the
interrupt remains set until both of the following occur:

�

Vector fetch or software clear

�

Return of the interrupt pin to logic 1

The vector fetch or software clear may occur before or after the interrupt
pin returns to logic 1. As long as the pin is low, the interrupt request
remains pending. A reset will clear the latch and the MODE control bit,
thereby clearing the interrupt even if the pin stays low.

When set, the IMASK bit in the INTSCR mask all external interrupt
requests. A latched interrupt request is not presented to the interrupt
priority logic unless the IMASK bit is clear.

External Interrupt (IRQ)

Technical Data

MC68HC908GR8 -- Rev 4.0

170

External Interrupt (IRQ)

MOTOROLA

12.5 IRQ1 Pin

A logic 0 on the IRQ1 pin can latch an interrupt request into the IRQ
latch. A vector fetch, software clear, or reset clears the IRQ latch.

If the MODE bit is set, the IRQ1 pin is both falling-edge-sensitive and
low-level-sensitive. With MODE set, both of the following actions must
occur to clear IRQ:

�

Vector fetch or software clear -- A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (INTSCR).
The ACK bit is useful in applications that poll the IRQ1 pin and
require software to clear the IRQ latch. Writing to the ACK bit prior
to leaving an interrupt service routine can also prevent spurious
interrupts due to noise. Setting ACK does not affect subsequent
transitions on the IRQ1 pin. A falling edge that occurs after writing
to the ACK bit another interrupt request. If the IRQ mask bit,
IMASK, is clear, the CPU loads the program counter with the
vector address at locations $FFFA and $FFFB.

�

Return of the IRQ1 pin to logic 1 -- As long as the IRQ1 pin is at
logic 0, IRQ remains active.

The vector fetch or software clear and the return of the IRQ1 pin to logic
1 may occur in any order. The interrupt request remains pending as long
as the IRQ1 pin is at logic 0. A reset will clear the latch and the MODE
control bit, thereby clearing the interrupt even if the pin stays low.

If the MODE bit is clear, the IRQ1 pin is falling-edge-sensitive only. With
MODE clear, a vector fetch or software clear immediately clears the IRQ
latch.

External Interrupt (IRQ)

IRQ Module During Break Interrupts

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

External Interrupt (IRQ)

171

The IRQF bit in the INTSCR register can be used to check for pending
interrupts. The IRQF bit is not affected by the IMASK bit, which makes it
useful in applications where polling is preferred.

Use the BIH or BIL instruction to read the logic level on the IRQ1 pin.

NOTE:

When using the level-sensitive interrupt trigger, avoid false interrupts by
masking interrupt requests in the interrupt routine.

12.6 IRQ Module During Break Interrupts

The BCFE bit in the SIM break flag control register (SBFCR) enables
software to clear the latch during the break state. See

Break Module

(BRK)

To allow software to clear the IRQ latch during a break interrupt, write a
logic 1 to the BCFE bit. If a latch is cleared during the break state, it
remains cleared when the MCU exits the break state.

To protect CPU interrupt flags during the break state, write a logic 0 to
the BCFE bit. With BCFE at logic 0 (its default state), writing to the ACK
bit in the IRQ status and control register during the break state has no
effect on the IRQ interrupt flags.

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Keyboard Interrupt (KBI)

175

Technical Data -- MC68HC908GR8

Section 13. Keyboard Interrupt (KBI)

13.1 Contents

13.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

13.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

13.5

Keyboard Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179

13.6

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .180

13.7

Keyboard Module During Break Interrupts . . . . . . . . . . . . . . .180

13.8

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181

13.2 Introduction

The keyboard interrupt module (KBI) provides four independently
maskable external interrupts.

13.3 Features

�

Four keyboard interrupt pins with separate keyboard interrupt
enable bits and one keyboard interrupt mask

�

Hysteresis buffers

�

Programmable edge-only or edge- and level- interrupt sensitivity

�

Exit from low-power modes

�

I/O (input/output) port bit(s) software configurable with pullup
device(s) if configured as input port bit(s)

Keyboard Interrupt (KBI)

Technical Data

MC68HC908GR8 -- Rev 4.0

178

Keyboard Interrupt (KBI)

MOTOROLA

If the MODEK bit is set, the keyboard interrupt pins are both falling edge-
and low-level sensitive, and both of the following actions must occur to
clear a keyboard interrupt request:

�

Vector fetch or software clear -- A vector fetch generates an
interrupt acknowledge signal to clear the interrupt request.
Software may generate the interrupt acknowledge signal by
writing a logic 1 to the ACKK bit in the keyboard status and control
register (INTKBSCR). The ACKK bit is useful in applications that
poll the keyboard interrupt pins and require software to clear the
keyboard interrupt request. Writing to the ACKK bit prior to leaving
an interrupt service routine can also prevent spurious interrupts
due to noise. Setting ACKK does not affect subsequent transitions
on the keyboard interrupt pins. A falling edge that occurs after
writing to the ACKK bit latches another interrupt request. If the
keyboard interrupt mask bit, IMASKK, is clear, the CPU loads the
program counter with the vector address at locations $FFDE and
$FFDF.

�

Return of all enabled keyboard interrupt pins to logic 1 -- As long
as any enabled keyboard interrupt pin is at logic 0, the keyboard
interrupt remains set.

The vector fetch or software clear and the return of all enabled keyboard
interrupt pins to logic 1 may occur in any order.

If the MODEK bit is clear, the keyboard interrupt pin is falling-edge-
sensitive only. With MODEK clear, a vector fetch or software clear
immediately clears the keyboard interrupt request.

Reset clears the keyboard interrupt request and the MODEK bit, clearing
the interrupt request even if a keyboard interrupt pin stays at logic 0.

The keyboard flag bit (KEYF) in the keyboard status and control register
can be used to see if a pending interrupt exists. The KEYF bit is not
affected by the keyboard interrupt mask bit (IMASKK) which makes it
useful in applications where polling is preferred.

To determine the logic level on a keyboard interrupt pin, use the data
direction register to configure the pin as an input and read the data
register.

Keyboard Interrupt (KBI)

Keyboard Initialization

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Keyboard Interrupt (KBI)

179

NOTE:

Setting a keyboard interrupt enable bit (KBIEx) forces the corresponding
keyboard interrupt pin to be an input, overriding the data direction
register. However, the data direction register bit must be a logic 0 for
software to read the pin.

13.5 Keyboard Initialization

When a keyboard interrupt pin is enabled, it takes time for the internal
pullup to reach a logic 1. Therefore, a false interrupt can occur as soon
as the pin is enabled.

To prevent a false interrupt on keyboard initialization:

1. Mask keyboard interrupts by setting the IMASKK bit in the

keyboard status and control register.

2. Enable the KBI pins by setting the appropriate KBIEx bits in the

keyboard interrupt enable register.

3. Write to the ACKK bit in the keyboard status and control register

to clear any false interrupts.

4. Clear the IMASKK bit.

An interrupt signal on an edge-triggered pin can be acknowledged
immediately after enabling the pin. An interrupt signal on an edge- and
level-triggered interrupt pin must be acknowledged after a delay that
depends on the external load.

Another way to avoid a false interrupt is:

1. Configure the keyboard pins as outputs by setting the appropriate

DDRA bits in data direction register A.

2. Write logic 1s to the appropriate port A data register bits.

3. Enable the KBI pins by setting the appropriate KBIEx bits in the

keyboard interrupt enable register.

Keyboard Interrupt (KBI)

Technical Data

MC68HC908GR8 -- Rev 4.0

180

Keyboard Interrupt (KBI)

MOTOROLA

13.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.

13.6.1 Wait Mode

The keyboard module remains active in wait mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of wait mode.

13.6.2 Stop Mode

The keyboard module remains active in stop mode. Clearing the
IMASKK bit in the keyboard status and control register enables keyboard
interrupt requests to bring the MCU out of stop mode.

13.7 Keyboard Module During Break Interrupts

The system integration module (SIM) controls whether the keyboard
interrupt latch can be cleared during the break state. The BCFE bit in the
SIM break flag control register (SBFCR) enables software to clear status
bits during the break state.

To allow software to clear the keyboard interrupt latch during a break
interrupt, write a logic 1 to the BCFE bit. If a latch is cleared during the
break state, it remains cleared when the MCU exits the break state.

To protect the latch during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), writing to the keyboard
acknowledge bit (ACKK) in the keyboard status and control register
during the break state has no effect. See

Keyboard Status and Control

Keyboard Interrupt (KBI)

Technical Data

MC68HC908GR8 -- Rev 4.0

182

Keyboard Interrupt (KBI)

MOTOROLA

ACKK -- Keyboard Acknowledge Bit

Writing a logic 1 to this write-only bit clears the keyboard interrupt
request. ACKK always reads as logic 0. Reset clears ACKK.

IMASKK -- Keyboard Interrupt Mask Bit

Writing a logic 1 to this read/write bit prevents the output of the
keyboard interrupt mask from generating interrupt requests. Reset
clears the IMASKK bit.

1 = Keyboard interrupt requests masked
0 = Keyboard interrupt requests not masked

MODEK -- Keyboard Triggering Sensitivity Bit

This read/write bit controls the triggering sensitivity of the keyboard
interrupt pins. Reset clears MODEK.

1 = Keyboard interrupt requests on falling edges and low levels
0 = Keyboard interrupt requests on falling edges only

13.8.2 Keyboard Interrupt Enable Register

The keyboard interrupt enable register enables or disables each port A
pin to operate as a keyboard interrupt pin.

KBIE3�KBIE0 -- Keyboard Interrupt Enable Bits

Each of these read/write bits enables the corresponding keyboard
interrupt pin to latch interrupt requests. Reset clears the keyboard
interrupt enable register.

1 = PTAx pin enabled as keyboard interrupt pin
0 = PTAx pin not enabled as keyboard interrupt pin

Address: $001B

Bit 7

Bit 0

Read:

KBIE3

KBIE2

KBIE1

KBIE0

Write:

Reset:

Figure 13-4. Keyboard Interrupt Enable Register (INTKBIER)

Low-Voltage Inhibit (LVI)

Technical Data

MC68HC908GR8 -- Rev 4.0

184

Low-Voltage Inhibit (LVI)

MOTOROLA

14.4 Functional Description

Figure 14-1

shows the structure of the LVI module. The LVI is enabled

out of reset. The LVI module contains a bandgap reference circuit and
comparator. Clearing the LVI power disable bit, LVIPWRD, enables the
LVI to monitor V

voltage. Clearing the LVI reset disable bit, LVIRSTD,

enables the LVI module to generate a reset when V

falls below the trip

point voltage, V

TRIPF

. Setting the LVI enable in stop mode bit, LVISTOP,

enables the LVI to operate in stop mode. Setting the LVI 5V or 3V trip
point bit, LVI5OR3, enables V

TRIPF

to be configured for 5V operation.

Clearing the LVI5OR3 bit enables V

TRIPF

to be configured for 3V

operation. The actual trip points are shown in

Electrical Specifications

NOTE:

After a power-on reset (POR) the LVI's default mode of operation is 3 V.
If a 5V system is used, the user must set the LVI5OR3 bit to raise the trip
point to 5V operation. Note that this must be done after every POR since
the default will revert back to 3V mode after each POR. If the V

supply

is below the 5V mode trip voltage but above the 3V mode trip voltage
when POR is released, the part will operate because V

TRIPF

defaults to

3V mode after a POR. So, in a 5V system care must be taken to ensure
that V

is above the 5V mode trip voltage after POR is released.

NOTE:

If the user requires 5V mode and sets the LVI5OR3 bit after a POR while
the V

supply is not above the V

TRIPR

for 5V mode, the MCU will

immediately go into reset. The LVI in this case will hold the part in reset
until either V

goes above the rising 5V trip point, V

TRIPR

, which will

release reset or V

decreases to approximately 0 V which will re-trigger

the POR and reset the trip point to 3V operation.

Low-Voltage Inhibit (LVI)

Technical Data

MC68HC908GR8 -- Rev 4.0

186

Low-Voltage Inhibit (LVI)

MOTOROLA

14.4.1 Polled LVI Operation

In applications that can operate at V

levels below the V

TRIPF

level,

software can monitor V

by polling the LVIOUT bit. In the configuration

register, the LVIPWRD bit must be at logic 0 to enable the LVI module,
and the LVIRSTD bit must be at logic 1 to disable LVI resets.

14.4.2 Forced Reset Operation

In applications that require V

to remain above the V

TRIPF

level,

enabling LVI resets allows the LVI module to reset the MCU when V

falls below the V

TRIPF

level. In the configuration register, the LVIPWRD

and LVIRSTD bits must be at logic 0 to enable the LVI module and to
enable LVI resets.

14.4.3 Voltage Hysteresis Protection

Once the LVI has triggered (by having V

fall below V

TRIPF

), the LVI

will maintain a reset condition until V

rises above the rising trip point

voltage, V

TRIPR

. This prevents a condition in which the MCU is

continually entering and exiting reset if V

is approximately equal to

TRIPF

. V

TRIPR

is greater than V

TRIPF

by the hysteresis voltage, V

HYS

Addr.

Register Name

Bit 7

Bit 0

$FE0C

LVI Status Register

(LVISR)

Read: LVIOUT

Write:

Reset:

= Unimplemented

Figure 14-2. LVI I/O Register Summary

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Monitor ROM (MON)

189

Technical Data -- MC68HC908GR8

Section 15. Monitor ROM (MON)

15.1 Contents

15.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189

15.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

15.5

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202

15.2 Introduction

This section describes the monitor ROM (MON) and the monitor mode
entry methods. The monitor ROM allows complete testing of the MCU
through a single-wire interface with a host computer. Monitor mode entry
can be achieved without use of the higher test voltage, V

TST

, as long as

vector addresses $FFFE and $FFFF are blank, thus reducing the
hardware requirements for in-circuit programming.

15.3 Features

Features of the monitor ROM include:

�

Normal user-mode pin functionality

�

One pin dedicated to serial communication between monitor ROM
and host computer

�

Standard mark/space non-return-to-zero (NRZ) communication
with host computer

�

Execution of code in RAM or FLASH

Monitor ROM (MON)

Technical Data

MC68HC908GR8 -- Rev 4.0

190

Monitor ROM (MON)

MOTOROLA

�

FLASH memory security feature

(1)

�

FLASH memory programming interface

�

Enhanced PLL (phase-locked loop) option to allow use of external
32.768-kHz crystal to generate internal frequency of 2.4576 MHz

�

310 byte monitor ROM code size ($FE20 to $FF55)

�

Monitor mode entry without high voltage, V

TST

, if reset vector is

blank ($FFFE and $FFFF contain $FF)

�

Standard monitor mode entry if high voltage, V

TST

, is applied to

IRQ

15.4 Functional Description

The monitor ROM receives and executes commands from a host
computer.

Figure 15-1

shows an example circuit used to enter monitor

mode and communicate with a host computer via a standard RS-232
interface.

Simple monitor commands can access any memory address. In monitor
mode, the MCU can execute code downloaded into RAM by a host
computer while most MCU pins retain normal operating mode functions.
All communication between the host computer and the MCU is through
the PTA0 pin. A level-shifting and multiplexing interface is required
between PTA0 and the host computer. PTA0 is used in a wired-OR
configuration and requires a pullup resistor.

1. No security feature is absolutely secure. However, Motorola's strategy is to make reading or
copying the FLASH difficult for unauthorized users.

Monitor ROM (MON)

Technical Data

MC68HC908GR8 -- Rev 4.0

192

Monitor ROM (MON)

MOTOROLA

The monitor code has been updated from previous versions to allow
enabling the PLL to generate the internal clock, provided the reset vector
is blank, when the device is being clocked by a low-frequency crystal.
This addition, which is enabled when IRQ is held low out of rest, is
intended to support serial communication/ programming at 9600 baud in
monitor mode by stepping up the external frequency (assumed to be
32.768 kHz) by a fixed amount to generate the desired internal
frequency (2.4576 MHz). Since this feature is enabled only when IRQ is
held low out of reset, it cannot be used when the reset vector is not blank
because entry into monitor mode in this case requires V

TST

on IRQ.

15.4.1 Entering Monitor Mode

Table 15-1

shows the pin conditions for entering monitor mode. As

specified in the table, monitor mode may be entered after a power-on
reset (POR) and will allow communication at 9600 baud provided one of
the following sets of conditions is met:

1. If $FFFE and $FFFF contain values not cared:

�

The external clock is 9.8304 MHz

�

IRQ = V

TST

(PLL off)

2. If $FFFE and $FFFF contain $FF, blank state:

�

The external clock is 9.8304 MHz

�

IRQ = V

(this can be implemented through the internal IRQ

pullup; PLL off)

3. If $FFFE and $FFFF contain $FF, blank state:

�

The external clock is 32.768 kHz (crystal)

�

IRQ = V

(this setting initiates the PLL to boost the external

32.768 kHz to an internal bus frequency of 2.4576 MHz)

Monitor ROM (MON)

Functional Description

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Monitor ROM (MON)

193

If entering monitor mode with V

TST

applied on IRQ (condition set 1), the

CGMOUT frequency is equal to the CGMXCLK frequency and the OSC1
input directly generates internal bus clocks. In this case, the OSC1
signal must have a 50% duty cycle at maximum bus frequency.

If entering monitor mode without high voltage applied on IRQ (condition
set 2 or 3, where applied voltage is either V

or V

), then all port B pin

Table 15-1. Monitor Mode Signal Requirements and Options

IRQ

RESET

$FFFE/

$FFFF

PLL

PTB0 PTB1

External

Clock

(1)

CGMOUT

Bus

Freq

COP

For Serial

Communication

Comment

PTA0 PTA1

Baud

Rate

(2)

(3)

GND

Disabled

No operation until

reset goes high

TST

OFF

9.8304

MHz

4.9152

MHz

2.4576

MHz

Disabled

9600

PTB0 and PTB1

voltages only

required if

IRQ = V

TST

DNA

$FFFF

OFF

9.8304

MHz

4.9152

MHz

2.4576

MHz

Disabled

9600

External frequency

always divided by

DNA

GND

$FFFF

32.768

kHz

4.9152

MHz

2.4576

MHz

Disabled

9600

PLL enabled (BCS

set) in monitor

code

DNA

GND

TST

$FFFF

OFF

Enabled

Enters user mode

-- will encounter

an illegal address

reset

GND

TST

Not

$FFFF

OFF

Enabled

Enters user mode

Notes:

1. External clock is derived by a 32.768 kHz crystal or a 9.8304 MHz off-chip oscillator

2. PTA0 = 1 if serial communication; PTA0 = X if parallel communication

3. PTA1 = 0

serial, PTA1 = 1

parallel communication for security code entry

4. DNA = does not apply, X = don't care

Monitor ROM (MON)

Technical Data

MC68HC908GR8 -- Rev 4.0

194

Monitor ROM (MON)

MOTOROLA

requirements and conditions, are not in effect. This is to reduce circuit
requirements when performing in-circuit programming.

NOTE:

If the reset vector is blank and monitor mode is entered, the chip will see
an additional reset cycle after the initial POR reset. Once the part has
been programmed, the traditional method of applying a voltage, V

TST

, to

IRQ must be used to enter monitor mode.

The COP module is disabled in monitor mode based on these
conditions:

�

If monitor mode was entered as a result of the reset vector being
blank (condition set 2 or 3), the COP is always disabled regardless
of the state of IRQ or RST.

�

If monitor mode was entered with V

TST

on IRQ (condition set 1),

then the COP is disabled as long as V

TST

is applied to either IRQ

or RST.

The second condition states that as long as V

TST

is maintained on the

IRQ pin after entering monitor mode, or if V

TST

is applied to RST after

the initial reset to get into monitor mode (when V

TST

was applied to IRQ),

then the COP will be disabled. In the latter situation, after V

TST

is applied

to the RST pin, V

TST

can be removed from the IRQ pin in the interest of

freeing the IRQ for normal functionality in monitor mode.

Figure 15-2

shows a simplified diagram of the monitor mode entry when

the reset vector is blank and just 1 x V

voltage is applied to the IRQ

pin. An external oscillator of 9.8304 MHz is required for a baud rate of
9600, as the internal bus frequency is automatically set to the external
frequency divided by four.

Monitor ROM (MON)

Functional Description

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Monitor ROM (MON)

195

Figure 15-2. Low-Voltage Monitor Mode Entry Flowchart

Enter monitor mode with pin configuration shown in

Figure 15-1

pulling RST low and then high. The rising edge of RST latches monitor
mode. Once monitor mode is latched, the values on the specified pins
can change.

Once out of reset, the MCU waits for the host to send eight security
bytes. (See

Security

.) After the security bytes, the MCU sends a break

signal (10 consecutive logic 0s) to the host, indicating that it is ready to
receive a command.

NOTE:

The PTA1 pin must remain at logic 0 for 24 bus cycles after the RST pin
goes high to enter monitor mode properly.

In monitor mode, the MCU uses different vectors for reset, SWI
(software interrupt), and break interrupt than those for user mode. The
alternate vectors are in the $FE page instead of the $FF page and allow
code execution from the internal monitor firmware instead of user code.

NOTE:

Exiting monitor mode after it has been initiated by having a blank reset
vector requires a power-on reset. Pulling RST low will not exit monitor
mode in this situation.

IS VECTOR

BLANK?

POR

TRIGGERED?

NORMAL USER

MODE

MONITOR MODE

EXECUTE
MONITOR

CODE

YES

POR RESET

Monitor ROM (MON)

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Monitor ROM (MON)

MOTOROLA

Table 15-2

summarizes the differences between user mode and monitor

mode.

15.4.2 Data Format

Communication with the monitor ROM is in standard non-return-to-zero
(NRZ) mark/space data format. Transmit and receive baud rates must
be identical.

Figure 15-3. Monitor Data Format

15.4.3 Break Signal

A start bit (logic 0) followed by nine logic 0 bits is a break signal. When
the monitor receives a break signal, it drives the PTA0 pin high for the
duration of two bits and then echoes back the break signal.

Figure 15-4. Break Transaction

Table 15-2. Mode Differences

Modes

Functions

Reset

Vector

High

Reset

Vector

Low

Break

Vector

High

Break

Vector

Low

SWI

Vector

High

SWI

Vector

Low

User

$FFFE

$FFFF

$FFFC

$FFFD

$FFFC

$FFFD

Monitor

$FEFE

$FEFF

$FEFC

$FEFD

$FEFC

$FEFD

BIT 5

START

BIT

BIT 1

STOP

BIT

START

BIT

BIT 2

BIT 3

BIT 4

BIT 7

BIT 0

BIT 6

MISSING STOP BIT

2-STOP BIT DELAY BEFORE ZERO ECHO

Monitor ROM (MON)

Functional Description

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Monitor ROM (MON)

197

15.4.4 Baud Rate

The communication baud rate is controlled by the crystal frequency upon
entry into monitor mode. The divide by ratio is 1024.

If monitor mode was entered with V

on IRQ, then the divide by ratio is

also set at 1024. If monitor mode was entered with V

on IRQ, then the

internal PLL steps up the external frequency, presumed to be 32.768
kHz, to 2.4576 MHz. These latter two conditions for monitor mode entry
require that the reset vector is blank.

Table 15-3

lists external frequencies required to achieve a standard

baud rate of 9600 BPS. Other standard baud rates can be accomplished
using proportionally higher or lower frequency generators. If using a
crystal as the clock source, be aware of the upper frequency limit that the
internal clock module can handle. See

5.0 V Control Timing

and

3.0 V

Control Timing

for this limit.

15.4.5 Commands

The monitor ROM firmware uses these commands:

�

READ (read memory)

�

WRITE (write memory)

�

IREAD (indexed read)

�

IWRITE (indexed write)

�

READSP (read stack pointer)

�

RUN (run user program)

Table 15-3. Monitor Baud Rate Selection

External

Frequency

IRQ

Internal

Frequency

Baud Rate

(BPS)

9.8304 MHz

TST

2.4576 MHz

9600

9.8304 MHz

2.4576 MHz

9600

32.768 kHz

2.4576 MHz

9600

Monitor ROM (MON)

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Monitor ROM (MON)

MOTOROLA

The MCU executes the SWI and PSHH instructions when it enters
monitor mode. The RUN command tells the MCU to execute the PULH
and RTI instructions. Before sending the RUN command, the host can
modify the stacked CPU registers to prepare to run the host program.
The READSP command returns the incremented stack pointer value,
SP + 1. The high and low bytes of the program counter are at addresses
SP + 5 and SP + 6.

Figure 15-7. Stack Pointer at Monitor Mode Entry

15.5 Security

A security feature discourages unauthorized reading of FLASH locations
while in monitor mode. The host can bypass the security feature at
monitor mode entry by sending eight security bytes that match the bytes
at locations $FFF6�$FFFD. Locations $FFF6�$FFFD contain user-
defined data.

NOTE:

Do not leave locations $FFF6�$FFFD blank. For security reasons, they
should be programmed even if they are not used for vectors.

During monitor mode entry, the MCU waits after the power-on reset for
the host to send the eight security bytes on pin PTA0. If the received
bytes match those at locations $FFF6�$FFFD, the host bypasses the
security feature and can read all FLASH locations and execute code
from FLASH. Security remains bypassed until a power-on reset occurs.
If the reset was not a power-on reset, security remains bypassed and
security code entry is not required. (See

Figure 15-8

CONDITION CODE REGISTER

ACCUMULATOR

LOW BYTE OF INDEX REGISTER

HIGH BYTE OF PROGRAM COUNTER

LOW BYTE OF PROGRAM COUNTER

SP + 1

SP + 2

SP + 3

SP + 4

SP + 5

SP + 6

HIGH BYTE OF INDEX REGISTER

SP + 7

Monitor ROM (MON)

Security

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Monitor ROM (MON)

203

Figure 15-8. Monitor Mode Entry Timing

Upon power-on reset, if the received bytes of the security code do not
match the data at locations $FFF6�$FFFD, the host fails to bypass the
security feature. The MCU remains in monitor mode, but reading a
FLASH location returns an invalid value and trying to execute code from
FLASH causes an illegal address reset. After receiving the eight security
bytes from the host, the MCU transmits a break character, signifying that
it is ready to receive a command.

NOTE:

The MCU does not transmit a break character until after the host sends
the eight security bytes.

To determine whether the security code entered is correct, check to see
if bit 6 of RAM address $40 is set. If it is, then the correct security code
has been entered and FLASH can be accessed.

CHO

COMM

ND E

CHO

PA0

PA1

RST

4096 + 32 CGMXCLK CYCLES

24 BUS CYCLES

256 BUS CYCLES (MINIMUM)

NOTES:

2 = Data return delay, 2 bit times
4 = Wait 1 bit time before sending next byte.

FROM HOST

FROM MCU

1 = Echo delay, 2 bit times

MC68HC908GR8 -- Rev 4.0

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Input/Output Ports (I/O)

205

Technical Data -- MC68HC908GR8

Section 16. Input/Output Ports (I/O)

16.1 Contents

16.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205

16.3

Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209

16.4

Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

16.5

Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216

16.6

Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220

16.7

Port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225

16.2 Introduction

Twenty one (21) bidirectional input-output (I/O) pins form five parallel
ports. All I/O pins are programmable as inputs or outputs. All individual
bits within port A, port C, and port D are software configurable with pullup
devices if configured as input port bits. The pullup devices are
automatically and dynamically disabled when a port bit is switched to
output mode.

NOTE:

Connect any unused I/O pins to an appropriate logic level, either V

. Although the I/O ports do not require termination for proper

operation, termination reduces excess current consumption and the
possibility of electrostatic damage.

Input/Output Ports (I/O)

Technical Data

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Input/Output Ports (I/O)

MOTOROLA

Addr.

Register Name

Bit 7

Bit 0

$0000

Port A Data Register

(PTA)

Read:

PTA3

PTA2

PTA1

PTA0

Write:

Reset:

Unaffected by reset

$0001

Port B Data Register

(PTB)

Read:

PTB5

PTB4

PTB3

PTB2

PTB1

PTB0

Write:

Reset:

Unaffected by reset

$0002

Port C Data Register

(PTC)

Read:

PTC1

PTC0

Write:

Reset:

Unaffected by reset

$0003

Port D Data Register

(PTD)

Read:

PTD6

PTD5

PTD4

PTD3

PTD2

PTD1

PTD0

Write:

Reset:

Unaffected by reset

$0004

Data Direction Register A

(DDRA)

Read:

DDRA3

DDRA2

DDRA1

DDRA0

Write:

Reset:

$0005

Data Direction Register B

(DDRB)

Read:

DDRB5

DDRB4

DDRB3

DDRB2

DDRB1

DDRB0

Write:

Reset:

$0006

Data Direction Register C

(DDRC)

Read:

DDRC1

DDRC0

Write:

Reset:

$0007

Data Direction Register D

(DDRD)

Read:

DDRD6

DDRD5

DDRD4

DDRD3

DDRD2

DDRD1

DDRD0

Write:

Reset:

= Unimplemented

Figure 16-1. I/O Port Register Summary

Input/Output Ports (I/O)

Port B

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213

16.4 Port B

Port B is an 6-bit special-function port that shares all six of its pins with
the analog-to-digital converter (ADC) module.

16.4.1 Port B Data Register

The port B data register (PTB) contains a data latch for each of the six
port pins.

PTB5�PTB0 -- Port B Data Bits

These read/write bits are software-programmable. Data direction of
each port B pin is under the control of the corresponding bit in data
direction register B. Reset has no effect on port B data.

AD5�AD0 -- Analog-to-Digital Input Bits

AD5�AD0 are pins used for the input channels to the analog-to-digital
converter module. The channel select bits in the ADC status and
control register define which port B pin will be used as an ADC input
and overrides any control from the port I/O logic by forcing that pin as
the input to the analog circuitry.

NOTE:

Care must be taken when reading port B while applying analog voltages
to AD5�AD0 pins. If the appropriate ADC channel is not enabled,
excessive current drain may occur if analog voltages are applied to the
PTBx/ADx pin, while PTB is read as a digital input. Those ports not
selected as analog input channels are considered digital I/O ports.

NOTE:

PTB4 and 5 are not available in a 28-pin DIP and SOIC package

Address:

$0001

Bit 7

Bit 0

Read:

PTB5

PTB4

PTB3

PTB2

PTB1

PTB0

Write:

Reset:

Unaffected by reset

Alternate

Function:

AD5

AD4

AD3

AD2

AD1

AD0

Figure 16-6. Port B Data Register (PTB)

Input/Output Ports (I/O)

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Input/Output Ports (I/O)

MOTOROLA

16.6 Port D

Port D is an 7-bit special-function port that shares four of its pins with the
serial peripheral interface (SPI) module and three of its pins with two
timer interface (TIM1 and TIM2) modules. Port D also has software
configurable pullup devices if configured as an input port.

16.6.1 Port D Data Register

The port D data register (PTD) contains a data latch for each of the
seven port D pins.

PTD6�PTD0 -- Port D Data Bits

These read/write bits are software-programmable. Data direction of
each port D pin is under the control of the corresponding bit in data
direction register D. Reset has no effect on port D data.

T2CH0 -- Timer 2 Channel I/O Bits

The PTD6/T2CH0 pin is the TIM2 input capture/output compare pin.
The edge/level select bits, ELSxB:ELSxA, determine whether the
PTD6/T2CH0 pin is a timer channel I/O pin or a general-purpose I/O
pin. See

Timer Interface Module (TIM)

Address:

$0003

Bit 7

Bit 0

Read:

PTD6

PTD5

PTD4

PTD3

PTD2

PTD1

PTD0

Write:

Reset:

Unaffected by reset

Alternate

Function:

T2CH0

T1CH1

T1CH0

SPSCK

MOSI

MISO

Figure 16-13. Port D Data Register (PTD)

Input/Output Ports (I/O)

Port D

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Input/Output Ports (I/O)

221

T1CH1 and T1CH0 -- Timer 1 Channel I/O Bits

The PTD5/T1CH1�PTD4/T1CH0 pins are the TIM1 input
capture/output compare pins. The edge/level select bits, ELSxB and
ELSxA, determine whether the PTD5/T1CH1�PTD4/T1CH0 pins are
timer channel I/O pins or general-purpose I/O pins. See

Timer

Interface Module (TIM)

SPSCK -- SPI Serial Clock

The PTD3/SPSCK pin is the serial clock input of the SPI module.
When the SPE bit is clear, the PTD3/SPSCK pin is available for
general-purpose I/O.

MOSI -- Master Out/Slave In

The PTD2/MOSI pin is the master out/slave in terminal of the SPI
module. When the SPE bit is clear, the PTD2/MOSI pin is available
for general-purpose I/O.

MISO -- Master In/Slave Out

The PTD1/MISO pin is the master in/slave out terminal of the SPI
module. When the SPI enable bit, SPE, is clear, the SPI module is
disabled, and the PTD0/SS pin is available for general-purpose I/O.

Data direction register D (DDRD) does not affect the data direction of
port D pins that are being used by the SPI module. However, the
DDRD bits always determine whether reading port D returns the
states of the latches or the states of the pins. See

Table 16-5

SS -- Slave Select

The PTD0/SS pin is the slave select input of the SPI module. When
the SPE bit is clear, or when the SPI master bit, SPMSTR, is set, the
PTD0/SS pin is available for general-purpose I/O. When the SPI is
enabled, the DDRB0 bit in data direction register B (DDRB) has no
effect on the PTD0/SS pin.

Input/Output Ports (I/O)

Port E

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Input/Output Ports (I/O)

225

16.7 Port E

Port E is a 2-bit special-function port that shares two of its pins with the
serial communications interface (SCI) module.

16.7.1 Port E Data Register

The port E data register contains a data latch for each of the two port E
pins.

PTE1 and PTE0 -- Port E Data Bits

PTE1 and PTE0 are read/write, software programmable bits. Data
direction of each port E pin is under the control of the corresponding
bit in data direction register E.

NOTE:

Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. See

Table 16-6

RxD -- SCI Receive Data Input

The PTE1/RxD pin is the receive data input for the SCI module. When
the enable SCI bit, ENSCI, is clear, the SCI module is disabled, and
the PTE1/RxD pin is available for general-purpose I/O. See

Serial

Communications Interface (SCI)

Address:

$0008

Bit 7

Bit 0

Read:

PTE1

PTE0

Write:

Reset:

Unaffected by reset

Alternate

Function:

RxD

TxD

= Unimplemented

Figure 16-17. Port E Data Register (PTE)

Input/Output Ports (I/O)

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Input/Output Ports (I/O)

MOTOROLA

TxD -- SCI Transmit Data Output

The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. See

Serial

Communications Interface (SCI)

16.7.2 Data Direction Register E

Data direction register E (DDRE) determines whether each port E pin is
an input or an output. Writing a logic 1 to a DDRE bit enables the output
buffer for the corresponding port E pin; a logic 0 disables the output
buffer.

DDRE1 and DDRE0 -- Data Direction Register E Bits

These read/write bits control port E data direction. Reset clears
DDRE1 and DDRE0, configuring all port E pins as inputs.

1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input

NOTE:

Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.

Figure 16-19

shows the port E I/O logic.

Address:

$000C

Bit 7

Bit 0

Read:

DDRE1

DDRE0

Write:

Reset:

= Unimplemented

Figure 16-18. Data Direction Register E (DDRE)

MC68HC908GR8 -- Rev 4.0

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RAM

229

Technical Data -- MC68HC908GR8

Section 17. RAM

17.1 Contents

17.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

17.3

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

17.2 Introduction

This section describes the 384 bytes of RAM (random-access memory).

17.3 Functional Description

Addresses $0040 through $01BF are RAM locations. The location of the
stack RAM is programmable. The 16-bit stack pointer allows the stack to
be anywhere in the 64K byte memory space.

NOTE:

For correct operation, the stack pointer must point only to RAM
locations.

Within page zero are 192 bytes of RAM. Because the location of the
stack RAM is programmable, all page zero RAM locations can be used
for I/O control and user data or code. When the stack pointer is moved
from its reset location at $00FF out of page zero, direct addressing mode
instructions can efficiently access all page zero RAM locations. Page
zero RAM, therefore, provides ideal locations for frequently accessed
global variables.

Before processing an interrupt, the CPU uses five bytes of the stack to
save the contents of the CPU registers.

NOTE:

For M6805 compatibility, the H register is not stacked.

MC68HC908GR8 -- Rev 4.0

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Technical Data -- MC68HC908GR8

Section 18. Serial Communications Interface (SCI)

18.1 Contents

18.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231

18.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

18.4

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

18.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233

18.6

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .250

18.7

SCI During Break Module Interrupts. . . . . . . . . . . . . . . . . . . . 251

18.8

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

18.9

I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

18.2 Introduction

This section describes the serial communications interface (SCI)
module, which allows high-speed asynchronous communications with
peripheral devices and other MCUs.

NOTE:

References to DMA (direct-memory access) and associated functions
are only valid if the MCU has a DMA module. This MCU does not have
the DMA function. Any DMA-related register bits should be left in their
reset state for normal MCU operation.

Serial Communications Interface (SCI)

Pin Name Conventions

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233

18.4 Pin Name Conventions

The generic names of the SCI I/O pins are:

�

RxD (receive data)

�

TxD (transmit data)

SCI I/O (input/output) lines are implemented by sharing parallel I/O port
pins. The full name of an SCI input or output reflects the name of the
shared port pin.

Table 18-1

shows the full names and the generic names

of the SCI I/O pins.

The generic pin names appear in the text of this section.

18.5 Functional Description

Figure 18-1

shows the structure of the SCI module. The SCI allows full-

duplex, asynchronous, NRZ serial communication among the MCU and
remote devices, including other MCUs. The transmitter and receiver of
the SCI operate independently, although they use the same baud rate
generator. During normal operation, the CPU monitors the status of the
SCI, writes the data to be transmitted, and processes received data.

The baud rate clock source for the SCI can be selected via the
configuration bit, SCIBDSRC, of the CONFIG2 register ($001E). Source
selection values are shown in

Figure 18-1

Table 18-1. Pin Name Conventions

Generic Pin Names:

RxD

TxD

Full Pin Names:

PE1/RxD

PE0/TxD

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

MOTOROLA

18.5.2.2 Character Transmission

During an SCI transmission, the transmit shift register shifts a character
out to the PE2/TxD pin. The SCI data register (SCDR) is the write-only
buffer between the internal data bus and the transmit shift register. To
initiate an SCI transmission:

1. Enable the SCI by writing a logic 1 to the enable SCI bit (ENSCI)

in SCI control register 1 (SCC1).

2. Enable the transmitter by writing a logic 1 to the transmitter enable

bit (TE) in SCI control register 2 (SCC2).

3. Clear the SCI transmitter empty bit by first reading SCI status

4. Repeat step 3 for each subsequent transmission.

At the start of a transmission, transmitter control logic automatically
loads the transmit shift register with a preamble of logic 1s. After the
preamble shifts out, control logic transfers the SCDR data into the
transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes
into the most significant bit position.

The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the
SCDR transfers a byte to the transmit shift register. The SCTE bit
indicates that the SCDR can accept new data from the internal data bus.
If the SCI transmit interrupt enable bit, SCTIE, in SCC2 is also set, the
SCTE bit generates a transmitter CPU interrupt request.

When the transmit shift register is not transmitting a character, the
PE2/TxD pin goes to the idle condition, logic 1. If at any time software
clears the ENSCI bit in SCI control register 1 (SCC1), the transmitter and
receiver relinquish control of the port E pins.

18.5.2.3 Break Characters

Writing a logic 1 to the send break bit, SBK, in SCC2 loads the transmit
shift register with a break character. A break character contains all logic
0s and has no start, stop, or parity bit. Break character length depends
on the M bit in SCC1. As long as SBK is at logic 1, transmitter logic

Serial Communications Interface (SCI)

Functional Description

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Serial Communications Interface (SCI)

239

continuously loads break characters into the transmit shift register. After
software clears the SBK bit, the shift register finishes transmitting the
last break character and then transmits at least one logic 1. The
automatic logic 1 at the end of a break character guarantees the
recognition of the start bit of the next character.

The SCI recognizes a break character when a start bit is followed by
eight or nine logic 0 data bits and a logic 0 where the stop bit should be.

Receiving a break character has these effects on SCI registers:

�

Sets the framing error bit (FE) in SCS1

�

Sets the SCI receiver full bit (SCRF) in SCS1

�

Clears the SCI data register (SCDR)

�

Clears the R8 bit in SCC3

�

Sets the break flag bit (BKF) in SCS2

�

May set the overrun (OR), noise flag (NF), parity error (PE), or
reception in progress flag (RPF) bits

18.5.2.4 Idle Characters

An idle character contains all logic 1s and has no start, stop, or parity bit.
Idle character length depends on the M bit in SCC1. The preamble is a
synchronizing idle character that begins every transmission.

If the TE bit is cleared during a transmission, the PE2/TxD pin becomes
idle after completion of the transmission in progress. Clearing and then
setting the TE bit during a transmission queues an idle character to be
sent after the character currently being transmitted.

NOTE:

When queueing an idle character, return the TE bit to logic 1 before the
stop bit of the current character shifts out to the TxD pin. Setting TE after
the stop bit appears on TxD causes data previously written to the SCDR
to be lost.

Toggle the TE bit for a queued idle character when the SCTE bit
becomes set and just before writing the next byte to the SCDR.

Serial Communications Interface (SCI)

Technical Data

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Serial Communications Interface (SCI)

MOTOROLA

18.5.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)
reverses the polarity of transmitted data. All transmitted values, including
idle, break, start, and stop bits, are inverted when TXINV is at logic 1.
See

SCI Control Register 1

18.5.2.6 Transmitter Interrupts

These conditions can generate CPU interrupt requests from the SCI
transmitter:

�

SCI transmitter empty (SCTE) -- The SCTE bit in SCS1 indicates
that the SCDR has transferred a character to the transmit shift
register. SCTE can generate a transmitter CPU interrupt request.
Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2
enables the SCTE bit to generate transmitter CPU interrupt
requests.

�

Transmission complete (TC) -- The TC bit in SCS1 indicates that
the transmit shift register and the SCDR are empty and that no
break or idle character has been generated. The transmission
complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to
generate transmitter CPU interrupt requests.

18.5.3 Receiver

Figure 18-5

shows the structure of the SCI receiver.

18.5.3.1 Character Length

The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCC1) determines character length.
When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the
ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth
bit (bit 7).

Serial Communications Interface (SCI)

Functional Description

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243

18.5.3.3 Data Sampling

The receiver samples the PE1/RxD pin at the RT clock rate. The RT
clock is an internal signal with a frequency 16 times the baud rate. To
adjust for baud rate mismatch, the RT clock is resynchronized at the
following times (see

Figure 18-6

�

After every start bit

�

After the receiver detects a data bit change from logic 1 to logic 0
(after the majority of data bit samples at RT8, RT9, and RT10
returns a valid logic 1 and the majority of the next RT8, RT9, and
RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search
for a logic 0 preceded by three logic 1s. When the falling edge of a
possible start bit occurs, the RT clock begins to count to 16.

Figure 18-6. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes
samples at RT3, RT5, and RT7.

Table 18-2

summarizes the results of

the start bit verification samples.

RT CLOCK

RESET

RT1

RT2

RT3

RT4

RT5

RT8

RT7

RT6

RT11

RT10

RT9

RT15

RT14

RT13

RT12

RT16

RT1

RT2

RT3

RT4

START BIT

QUALIFICATION

START BIT

VERIFICATION

DATA

SAMPLING

SAMPLES

CLOCK

RT CLOCK

STATE

START BIT

LSB

PE1/RxD

Serial Communications Interface (SCI)

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NOTE:

The RT8, RT9, and RT10 samples do not affect start bit verification. If
any or all of the RT8, RT9, and RT10 start bit samples are logic 1s
following a successful start bit verification, the noise flag (NF) is set and
the receiver assumes that the bit is a start bit.

To verify a stop bit and to detect noise, recovery logic takes samples at
RT8, RT9, and RT10.

Table 18-4

summarizes the results of the stop bit

samples.

18.5.3.4 Framing Errors

If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error bit, FE, in
SCS1. A break character also sets the FE bit because a break character
has no stop bit. The FE bit is set at the same time that the SCRF bit is
set.

18.5.3.5 Baud Rate Tolerance

A transmitting device may be operating at a baud rate below or above
the receiver baud rate. Accumulated bit time misalignment can cause
one of the three stop bit data samples to fall outside the actual stop bit.
Then a noise error occurs. If more than one of the samples is outside the
stop bit, a framing error occurs. In most applications, the baud rate

Table 18-4. Stop Bit Recovery

RT8, RT9, and RT10

Samples

Framing

Error Flag

Noise Flag

000

001

010

011

100

101

110

111

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Serial Communications Interface (SCI)

MOTOROLA

tolerance is much more than the degree of misalignment that is likely to
occur.

As the receiver samples an incoming character, it resynchronizes the RT
clock on any valid falling edge within the character. Resynchronization
within characters corrects misalignments between transmitter bit times
and receiver bit times.

18.5.3.6 Slow Data Tolerance

Figure 18-7

shows how much a slow received character can be

misaligned without causing a noise error or a framing error. The slow
stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit
data samples at RT8, RT9, and RT10.

Figure 18-7. Slow Data

For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times

�

16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in

Figure 18-7

, the receiver counts

154 RT cycles at the point when the count of the transmitting device is
9 bit times

�

16 RT cycles + 3 RT cycles = 147 RT cycles.

The maximum percent difference between the receiver count and the
transmitter count of a slow 8-bit character with no errors is

For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times

�

16 RT cycles + 10 RT cycles = 170 RT cycles.

MSB

STOP

RT10

RT11

RT12

RT13

RT14

RT15

RT16

DATA

SAMPLES

RECEIVER
RT CLOCK

154

147

�

154

--------------------------

100

�

4.54%

Serial Communications Interface (SCI)

Functional Description

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247

With the misaligned character shown in

Figure 18-7

, the receiver counts

170 RT cycles at the point when the count of the transmitting device is
10 bit times

�

16 RT cycles + 3 RT cycles = 163 RT cycles.

The maximum percent difference between the receiver count and the
transmitter count of a slow 9-bit character with no errors is

18.5.3.7 Fast Data Tolerance

Figure 18-8

shows how much a fast received character can be

misaligned without causing a noise error or a framing error. The fast stop
bit ends at RT10 instead of RT16 but is still there for the stop bit data
samples at RT8, RT9, and RT10.

Figure 18-8. Fast Data

For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times

�

16 RT cycles + 10 RT cycles = 154 RT cycles.

With the misaligned character shown in

Figure 18-8

, the receiver counts

154 RT cycles at the point when the count of the transmitting device is
10 bit times

�

16 RT cycles = 160 RT cycles.

The maximum percent difference between the receiver count and the
transmitter count of a fast 8-bit character with no errors is

170

163

�

170

--------------------------

100

�

4.12%

IDLE OR NEXT CHARACTER

STOP

RT1

RT2

RT3

RT4

RT5

RT6

RT7

RT8

RT9

RT10

RT11

RT12

RT13

RT14

RT15

RT16

DATA

SAMPLES

RECEIVER
RT CLOCK

154

160

�

154

--------------------------

100

�

3.90%

�

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

MOTOROLA

For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times

�

16 RT cycles + 10 RT cycles = 170 RT cycles.

With the misaligned character shown in

Figure 18-8

, the receiver counts

170 RT cycles at the point when the count of the transmitting device is
11 bit times

�

16 RT cycles = 176 RT cycles.

The maximum percent difference between the receiver count and the
transmitter count of a fast 9-bit character with no errors is

18.5.3.8 Receiver Wakeup

So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup bit, RWU, in SCC2 puts the
receiver into a standby state during which receiver interrupts are
disabled.

Depending on the state of the WAKE bit in SCC1, either of two
conditions on the PE1/RxD pin can bring the receiver out of the standby
state:

�

Address mark -- An address mark is a logic 1 in the most
significant bit position of a received character. When the WAKE bit
is set, an address mark wakes the receiver from the standby state
by clearing the RWU bit. The address mark also sets the SCI
receiver full bit, SCRF. Software can then compare the character
containing the address mark to the user-defined address of the
receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same,
software can set the RWU bit and put the receiver back into the
standby state.

�

Idle input line condition -- When the WAKE bit is clear, an idle
character on the PE1/RxD pin wakes the receiver from the
standby state by clearing the RWU bit. The idle character that
wakes the receiver does not set the receiver idle bit, IDLE, or the

170

176

�

170

--------------------------

100

�

3.53%

Serial Communications Interface (SCI)

Functional Description

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Technical Data

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Serial Communications Interface (SCI)

249

SCI receiver full bit, SCRF. The idle line type bit, ILTY, determines
whether the receiver begins counting logic 1s as idle character bits
after the start bit or after the stop bit.

NOTE:

With the WAKE bit clear, setting the RWU bit after the RxD pin has been
idle may cause the receiver to wake up immediately.

18.5.3.9 Receiver Interrupts

The following sources can generate CPU interrupt requests from the SCI
receiver:

�

SCI receiver full (SCRF) -- The SCRF bit in SCS1 indicates that
the receive shift register has transferred a character to the SCDR.
SCRF can generate a receiver CPU interrupt request. Setting the
SCI receive interrupt enable bit, SCRIE, in SCC2 enables the
SCRF bit to generate receiver CPU interrupts.

�

Idle input (IDLE) -- The IDLE bit in SCS1 indicates that 10 or 11
consecutive logic 1s shifted in from the PE1/RxD pin. The idle line
interrupt enable bit, ILIE, in SCC2 enables the IDLE bit to generate
CPU interrupt requests.

18.5.3.10 Error Interrupts

The following receiver error flags in SCS1 can generate CPU interrupt
requests:

�

Receiver overrun (OR) -- The OR bit indicates that the receive
shift register shifted in a new character before the previous
character was read from the SCDR. The previous character
remains in the SCDR, and the new character is lost. The overrun
interrupt enable bit, ORIE, in SCC3 enables OR to generate SCI
error CPU interrupt requests.

�

Noise flag (NF) -- The NF bit is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, in SCC3 enables
NF to generate SCI error CPU interrupt requests.

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Serial Communications Interface (SCI)

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�

Framing error (FE) -- The FE bit in SCS1 is set when a logic 0
occurs where the receiver expects a stop bit. The framing error
interrupt enable bit, FEIE, in SCC3 enables FE to generate SCI
error CPU interrupt requests.

�

Parity error (PE) -- The PE bit in SCS1 is set when the SCI
detects a parity error in incoming data. The parity error interrupt
enable bit, PEIE, in SCC3 enables PE to generate SCI error CPU
interrupt requests.

18.6 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.

18.6.1 Wait Mode

The SCI module remains active after the execution of a WAIT
instruction. In wait mode, the SCI module registers are not accessible by
the CPU. Any enabled CPU interrupt request from the SCI module can
bring the MCU out of wait mode.

If SCI module functions are not required during wait mode, reduce power
consumption by disabling the module before executing the WAIT
instruction.

Refer to

Low Power Modes

for information on exiting wait mode.

18.6.2 Stop Mode

The SCI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect SCI register states. SCI module
operation resumes after an external interrupt.

Because the internal clock is inactive during stop mode, entering stop
mode during an SCI transmission or reception results in invalid data.

Refer to

Low Power Modes

for information on exiting stop mode.

Serial Communications Interface (SCI)

SCI During Break Module Interrupts

MC68HC908GR8 -- Rev 4.0

Technical Data

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Serial Communications Interface (SCI)

251

18.7 SCI During Break Module Interrupts

To protect status bits during the break state, write a logic 0 to the BCFE
bit. With BCFE at logic 0 (its default state), software can read and write
I/O registers during the break state without affecting status bits. Some
status bits have a 2-step read/write clearing procedure. If software does
the first step on such a bit before the break, the bit cannot change during
the break state as long as BCFE is at logic 0. After the break, doing the
second step clears the status bit.

18.8 I/O Signals

Port E shares two of its pins with the SCI module. The two SCI I/O pins
are:

�

PE2/TxD -- Transmit data

�

PE1/RxD -- Receive data

18.8.1 PE2/TxD (Transmit Data)

The PE2/TxD pin is the serial data output from the SCI transmitter. The
SCI shares the PE2/TxD pin with port E. When the SCI is enabled, the
PE2/TxD pin is an output regardless of the state of the DDRE0 bit in data
direction register E (DDRE).

Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 -- Rev 4.0

Technical Data

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Serial Communications Interface (SCI)

253

LOOPS -- Loop Mode Select Bit

This read/write bit enables loop mode operation. In loop mode the
PE1/RxD pin is disconnected from the SCI, and the transmitter output
goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.

1 = Loop mode enabled
0 = Normal operation enabled

ENSCI -- Enable SCI Bit

This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.

1 = SCI enabled
0 = SCI disabled

TXINV -- Transmit Inversion Bit

This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.

1 = Transmitter output inverted
0 = Transmitter output not inverted

NOTE:

Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.

M -- Mode (Character Length) Bit

This read/write bit determines whether SCI characters are eight or
nine bits long. See

Table 18-5

. The ninth bit can serve as an extra

stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.

Address:

$0013

Bit 7

Bit 0

Read:

LOOPS

ENSCI

TXINV

WAKE

ILTY

PEN

PTY

Write:

Reset:

Figure 18-9. SCI Control Register 1 (SCC1)

Serial Communications Interface (SCI)

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254

Serial Communications Interface (SCI)

MOTOROLA

1 = 9-bit SCI characters
0 = 8-bit SCI characters

WAKE -- Wakeup Condition Bit

This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition on the PE1/RxD pin. Reset clears the
WAKE bit.

1 = Address mark wakeup
0 = Idle line wakeup

ILTY -- Idle Line Type Bit

This read/write bit determines when the SCI starts counting logic 1s
as idle character bits. The counting begins either after the start bit or
after the stop bit. If the count begins after the start bit, then a string of
logic 1s preceding the stop bit may cause false recognition of an idle
character. Beginning the count after the stop bit avoids false idle
character recognition, but requires properly synchronized
transmissions. Reset clears the ILTY bit.

1 = Idle character bit count begins after stop bit
0 = Idle character bit count begins after start bit

PEN -- Parity Enable Bit

This read/write bit enables the SCI parity function. See

Table 18-5

When enabled, the parity function inserts a parity bit in the most
significant bit position. See

Figure 18-3

. Reset clears the PEN bit.

1 = Parity function enabled
0 = Parity function disabled

PTY -- Parity Bit

This read/write bit determines whether the SCI generates and checks
for odd parity or even parity. See

Table 18-5

. Reset clears the PTY bit.

1 = Odd parity
0 = Even parity

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256

Serial Communications Interface (SCI)

MOTOROLA

SCTIE -- SCI Transmit Interrupt Enable Bit

This read/write bit enables the SCTE bit to generate SCI transmitter
CPU interrupt requests. Reset clears the SCTIE bit.

1 = SCTE enabled to generate CPU interrupt
0 = SCTE not enabled to generate CPU interrupt

TCIE -- Transmission Complete Interrupt Enable Bit

This read/write bit enables the TC bit to generate SCI transmitter CPU
interrupt requests. Reset clears the TCIE bit.

1 = TC enabled to generate CPU interrupt requests
0 = TC not enabled to generate CPU interrupt requests

SCRIE -- SCI Receive Interrupt Enable Bit

This read/write bit enables the SCRF bit to generate SCI receiver
CPU interrupt requests. Reset clears the SCRIE bit.

1 = SCRF enabled to generate CPU interrupt
0 = SCRF not enabled to generate CPU interrupt

ILIE -- Idle Line Interrupt Enable Bit

This read/write bit enables the IDLE bit to generate SCI receiver CPU
interrupt requests. Reset clears the ILIE bit.

1 = IDLE enabled to generate CPU interrupt requests
0 = IDLE not enabled to generate CPU interrupt requests

TE -- Transmitter Enable Bit

Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PE2/TxD pin. If software clears the TE bit, the transmitter completes
any transmission in progress before the PE2/TxD returns to the idle

Address:

$0014

Bit 7

Bit 0

Read:

SCTIE

TCIE

SCRIE

ILIE

RWU

SBK

Write:

Reset:

Figure 18-10. SCI Control Register 2 (SCC2)

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

257

condition (logic 1). Clearing and then setting TE during a transmission
queues an idle character to be sent after the character currently being
transmitted. Reset clears the TE bit.

1 = Transmitter enabled
0 = Transmitter disabled

NOTE:

Writing to the TE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.

RE -- Receiver Enable Bit

Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver but does not affect receiver interrupt flag bits.
Reset clears the RE bit.

1 = Receiver enabled
0 = Receiver disabled

NOTE:

Writing to the RE bit is not allowed when the enable SCI bit (ENSCI) is
clear. ENSCI is in SCI control register 1.

RWU -- Receiver Wakeup Bit

This read/write bit puts the receiver in a standby state during which
receiver interrupts are disabled. The WAKE bit in SCC1 determines
whether an idle input or an address mark brings the receiver out of the
standby state and clears the RWU bit. Reset clears the RWU bit.

1 = Standby state
0 = Normal operation

SBK -- Send Break Bit

Setting and then clearing this read/write bit transmits a break
character followed by a logic 1. The logic 1 after the break character
guarantees recognition of a valid start bit. If SBK remains set, the
transmitter continuously transmits break characters with no logic 1s
between them. Reset clears the SBK bit.

1 = Transmit break characters
0 = No break characters being transmitted

NOTE:

Do not toggle the SBK bit immediately after setting the SCTE bit.
Toggling SBK before the preamble begins causes the SCI to send a
break character instead of a preamble.

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

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18.9.3 SCI Control Register 3

SCI control register 3:

�

Stores the ninth SCI data bit received and the ninth SCI data bit to
be transmitted

�

Enables these interrupts:

�

Receiver overrun interrupts

�

Noise error interrupts

�

Framing error interrupts

�

Parity error interrupts

R8 -- Received Bit 8

When the SCI is receiving 9-bit characters, R8 is the read-only ninth
bit (bit 8) of the received character. R8 is received at the same time
that the SCDR receives the other 8 bits.
When the SCI is receiving 8-bit characters, R8 is a copy of the eighth
bit (bit 7). Reset has no effect on the R8 bit.

T8 -- Transmitted Bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write
ninth bit (bit 8) of the transmitted character. T8 is loaded into the
transmit shift register at the same time that the SCDR is loaded into
the transmit shift register. Reset has no effect on the T8 bit.

Address:

$0015

Bit 7

Bit 0

Read:

DMARE

DMATE

ORIE

NEIE

FEIE

PEIE

Write:

Reset:

= Unimplemented

U = Unaffected

Figure 18-11. SCI Control Register 3 (SCC3)

Serial Communications Interface (SCI)

I/O Registers

MC68HC908GR8 -- Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

259

DMARE -- DMA Receive Enable Bit

CAUTION:

The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.

1 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)

0 = DMA not enabled to service SCI receiver DMA service requests

generated by the SCRF bit (SCI receiver CPU interrupt
requests enabled)

DMATE -- DMA Transfer Enable Bit

CAUTION:

The DMA module is not included on this MCU. Writing a logic 1 to
DMARE or DMATE may adversely affect MCU performance.

1 = SCTE DMA service requests enabled; SCTE CPU interrupt

requests disabled

0 = SCTE DMA service requests disabled; SCTE CPU interrupt

requests enabled

ORIE -- Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests
generated by the receiver overrun bit, OR.

1 = SCI error CPU interrupt requests from OR bit enabled
0 = SCI error CPU interrupt requests from OR bit disabled

NEIE -- Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests
generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled
0 = SCI error CPU interrupt requests from NE bit disabled

FEIE -- Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests
generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled
0 = SCI error CPU interrupt requests from FE bit disabled

Serial Communications Interface (SCI)

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260

Serial Communications Interface (SCI)

MOTOROLA

PEIE -- Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI receiver CPU interrupt requests
generated by the parity error bit, PE. See

SCI Status Register 1

Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled
0 = SCI error CPU interrupt requests from PE bit disabled

18.9.4 SCI Status Register 1

SCI status register 1 (SCS1) contains flags to signal these conditions:

�

Transfer of SCDR data to transmit shift register complete

�

Transmission complete

�

Transfer of receive shift register data to SCDR complete

�

Receiver input idle

�

Receiver overrun

�

Noisy data

�

Framing error

�

Parity error

SCTE -- SCI Transmitter Empty Bit

This clearable, read-only bit is set when the SCDR transfers a
character to the transmit shift register. SCTE can generate an SCI
transmitter CPU interrupt request. When the SCTIE bit in SCC2 is set,
SCTE generates an SCI transmitter CPU interrupt request. In normal

Address:

$0016

Bit 7

Bit 0

Read:

SCTE

SCRF

IDLE

Write:

Reset:

= Unimplemented

Figure 18-12. SCI Status Register 1 (SCS1)

Serial Communications Interface (SCI)

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Technical Data

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Serial Communications Interface (SCI)

261

operation, clear the SCTE bit by reading SCS1 with SCTE set and
then writing to SCDR. Reset sets the SCTE bit.

1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register

TC -- Transmission Complete Bit

This read-only bit is set when the SCTE bit is set, and no data,
preamble, or break character is being transmitted. TC generates an
SCI transmitter CPU interrupt request if the TCIE bit in SCC2 is also
set. TC is automatically cleared when data, preamble or break is
queued and ready to be sent. There may be up to 1.5 transmitter
clocks of latency between queueing data, preamble, and break and
the transmission actually starting. Reset sets the TC bit.

1 = No transmission in progress
0 = Transmission in progress

SCRF -- SCI Receiver Full Bit

This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. SCRF can generate an SCI
receiver CPU interrupt request. When the SCRIE bit in SCC2 is set,
SCRF generates a CPU interrupt request. In normal operation, clear
the SCRF bit by reading SCS1 with SCRF set and then reading the
SCDR. Reset clears SCRF.

1 = Received data available in SCDR
0 = Data not available in SCDR

IDLE -- Receiver Idle Bit

This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an SCI error CPU
interrupt request if the ILIE bit in SCC2 is also set. Clear the IDLE bit
by reading SCS1 with IDLE set and then reading the SCDR. After the
receiver is enabled, it must receive a valid character that sets the
SCRF bit before an idle condition can set the IDLE bit. Also, after the
IDLE bit has been cleared, a valid character must again set the SCRF
bit before an idle condition can set the IDLE bit. Reset clears the IDLE
bit.

1 = Receiver input idle
0 = Receiver input active (or idle since the IDLE bit was cleared)

Serial Communications Interface (SCI)

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Serial Communications Interface (SCI)

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OR -- Receiver Overrun Bit

This clearable, read-only bit is set when software fails to read the
SCDR before the receive shift register receives the next character.
The OR bit generates an SCI error CPU interrupt request if the ORIE
bit in SCC3 is also set. The data in the shift register is lost, but the data
already in the SCDR is not affected. Clear the OR bit by reading SCS1
with OR set and then reading the SCDR. Reset clears the OR bit.

1 = Receive shift register full and SCRF = 1
0 = No receiver overrun

Software latency may allow an overrun to occur between reads of
SCS1 and SCDR in the flag-clearing sequence.

Figure 18-13

shows

the normal flag-clearing sequence and an example of an overrun
caused by a delayed flag-clearing sequence. The delayed read of
SCDR does not clear the OR bit because OR was not set when SCS1
was read. Byte 2 caused the overrun and is lost. The next flag-
clearing sequence reads byte 3 in the SCDR instead of byte 2.

In applications that are subject to software latency or in which it is
important to know which byte is lost due to an overrun, the flag-
clearing routine can check the OR bit in a second read of SCS1 after
reading the data register.

NF -- Receiver Noise Flag Bit

This clearable, read-only bit is set when the SCI detects noise on the
PE1/RxD pin. NF generates an NF CPU interrupt request if the NEIE
bit in SCC3 is also set. Clear the NF bit by reading SCS1 and then
reading the SCDR. Reset clears the NF bit.

1 = Noise detected
0 = No noise detected

FE -- Receiver Framing Error Bit

This clearable, read-only bit is set when a logic 0 is accepted as the
stop bit. FE generates an SCI error CPU interrupt request if the FEIE
bit in SCC3 also is set. Clear the FE bit by reading SCS1 with FE set
and then reading the SCDR. Reset clears the FE bit.

1 = Framing error detected
0 = No framing error detected

Serial Communications Interface (SCI)

Technical Data

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264

Serial Communications Interface (SCI)

MOTOROLA

18.9.5 SCI Status Register 2

SCI status register 2 contains flags to signal the following conditions:

�

Break character detected

�

Incoming data

BKF -- Break Flag Bit

This clearable, read-only bit is set when the SCI detects a break
character on the PE1/RxD pin. In SCS1, the FE and SCRF bits are
also set. In 9-bit character transmissions, the R8 bit in SCC3 is
cleared. BKF does not generate a CPU interrupt request. Clear BKF
by reading SCS2 with BKF set and then reading the SCDR. Once
cleared, BKF can become set again only after logic 1s again appear
on the PE1/RxD pin followed by another break character. Reset
clears the BKF bit.

1 = Break character detected
0 = No break character detected

RPF -- Reception in Progress Flag Bit

This read-only bit is set when the receiver detects a logic 0 during the
RT1 time period of the start bit search. RPF does not generate an
interrupt request. RPF is reset after the receiver detects false start bits
(usually from noise or a baud rate mismatch) or when the receiver
detects an idle character. Polling RPF before disabling the SCI
module or entering stop mode can show whether a reception is in
progress.

1 = Reception in progress
0 = No reception in progress

Address:

$0017

Bit 7

Bit 0

Read:

BKF

RPF

Write:

Reset:

= Unimplemented

Figure 18-14. SCI Status Register 2 (SCS2)

Serial Communications Interface (SCI)

I/O Registers

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18.9.6 SCI Data Register

The SCI data register (SCDR) is the buffer between the internal data bus
and the receive and transmit shift registers. Reset has no effect on data
in the SCI data register.

R7/T7�R0/T0 -- Receive/Transmit Data Bits

Reading address $0018 accesses the read-only received data bits,
R7:R0. Writing to address $0018 writes the data to be transmitted,
T7:T0. Reset has no effect on the SCI data register.

NOTE:

Do not use read/modify/write instructions on the SCI data register.

18.9.7 SCI Baud Rate Register

The baud rate register (SCBR) selects the baud rate for both the receiver
and the transmitter.

Address:

$0018

Bit 7

Bit 0

Read:

Write:

Reset:

Unaffected by reset

Figure 18-15. SCI Data Register (SCDR)

Address:

$0019

Bit 7

Bit 0

Read:

SCP1

SCP0

SCR2

SCR1

SCR0

Write:

Reset:

= Unimplemented

= Reserved

Figure 18-16. SCI Baud Rate Register (SCBR)

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Section 19. System Integration Module (SIM)

19.1 Contents

19.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271

19.3

SIM Bus Clock Control and Generation . . . . . . . . . . . . . . . . . 275

19.4

Reset and System Initialization. . . . . . . . . . . . . . . . . . . . . . . . 276

19.5

SIM Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281

19.6

Exception Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282

19.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290

19.8

SIM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

19.2 Introduction

This section describes the system integration module (SIM). Together
with the CPU, the SIM controls all MCU activities. A block diagram of the
SIM is shown in

Figure 19-1

Table 19-1

is a summary of the SIM

input/output (I/O) registers. The SIM is a system state controller that
coordinates CPU and exception timing. The SIM is responsible for:

�

Bus clock generation and control for CPU and peripherals:

�

Stop/wait/reset/break entry and recovery

�

Internal clock control

�

Master reset control, including power-on reset (POR) and COP
timeout

�

Interrupt control:

�

Acknowledge timing

�

Arbitration control timing

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Addr.

Register Name

Bit 7

Bit 0

$FE00

SIM Break Status Register

(SBSR)

Read:

SBSW

Write:

NOTE

Reset:

Note: Writing a logic 0 clears SBSW.

$FE01

SIM Reset Status Register

(SRSR)

Read:

POR

COP

ILOP

ILAD

MODRST

LVI

Write:

POR:

$FE02

SIM Upper Byte Address

Read:

Write:

Reset:

$FE03

SIM Break Flag Control

Read:

BCFE

Write:

Reset:

$FE09

Interrupt Status Register 1

(INT1)

Read:

IF6

IF5

IF4

IF3

IF2

IF1

Write:

Reset:

$FE0A

Interrupt Status Register 2

(INT2)

Read:

IF14

IF13

IF12

IF11

IF10

IF9

IF8

IF7

Write:

Reset:

$FE0B

Interrupt Status Register 3

(INT3)

Read:

IF16

IF15

Write:

Reset:

= Unimplemented

Figure 19-2. SIM I/O Register Summary

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19.3.2 Clock Startup from POR or LVI Reset

When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 CGMXCLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.

19.3.3 Clocks in Stop Mode and Wait Mode

Upon exit from stop mode by an interrupt, break, or reset, the SIM allows
CGMXCLK to clock the SIM counter. The CPU and peripheral clocks do
not become active until after the stop delay timeout. This timeout is
selectable as 4096 or 32 CGMXCLK cycles. See

Stop Mode

In wait mode, the CPU clocks are inactive. The SIM also produces two
sets of clocks for other modules. Refer to the wait mode subsection of
each module to see if the module is active or inactive in wait mode.
Some modules can be programmed to be active in wait mode.

19.4 Reset and System Initialization

The MCU has these reset sources:

�

Power-on reset module (POR)

�

External reset pin (RST)

�

Computer operating properly module (COP)

�

Low-voltage inhibit module (LVI)

�

Illegal opcode

�

Illegal address

All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in
monitor mode) and assert the internal reset signal (IRST). IRST causes
all registers to be returned to their default values and all modules to be
returned to their reset states.

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Reset and System Initialization

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An internal reset clears the SIM counter (see

SIM Counter

), but an

external reset does not. Each of the resets sets a corresponding bit in
the SIM reset status register (SRSR). See

SIM Registers

19.4.1 External Pin Reset

The RST pin circuit includes an internal pullup device. Pulling the
asynchronous RST pin low halts all processing. The PIN bit of the SIM
reset status register (SRSR) is set as long as RST is held low for a
minimum of 67 CGMXCLK cycles, assuming that neither the POR nor
the LVI was the source of the reset. See

Table 19-2

for details.

Figure

19-4

shows the relative timing.

Figure 19-4. External Reset Timing

19.4.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset signal
IRST continues to be asserted for an additional 32 cycles. See

Figure

19-5

. An internal reset can be caused by an illegal address, illegal

opcode, COP timeout, LVI, or POR. See

Figure 19-6

NOTE:

For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal

Table 19-2. PIN Bit Set Timing

Reset Type

Number of Cycles Required to Set PIN

POR/LVI

4163 (4096 + 64 + 3)

All others

67 (64 + 3)

RST

IAB

VECT H VECT L

CGMOUT

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Reset and System Initialization

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279

�

The internal reset signal is asserted.

�

The SIM enables CGMOUT.

�

Internal clocks to the CPU and modules are held inactive for 4096
CGMXCLK cycles to allow stabilization of the oscillator.

�

The RST pin is driven low during the oscillator stabilization time.

�

The POR bit of the SIM reset status register (SRSR) is set and all
other bits in the register are cleared.

Figure 19-7. POR Recovery

19.4.2.2 Computer Operating Properly (COP) Reset

An input to the SIM is reserved for the COP reset signal. The overflow of
the COP counter causes an internal reset and sets the COP bit in the
SIM reset status register (SRSR). The SIM actively pulls down the RST
pin for all internal reset sources.

To prevent a COP module timeout, write any value to location $FFFF.
Writing to location $FFFF clears the COP counter and bits 12 through 4
of the SIM counter. The SIM counter output, which occurs at least every
2

� 2

CGMXCLK cycles, drives the COP counter. The COP should be

serviced as soon as possible out of reset to guarantee the maximum
amount of time before the first timeout.

PORRST

OSC1

CGMXCLK

CGMOUT

RST

IAB

4096

CYCLES

$FFFE

$FFFF

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The COP module is disabled if the RST pin or the IRQ pin is held at V

tst

while the MCU is in monitor mode. The COP module can be disabled
only through combinational logic conditioned with the high voltage signal
on the RST or the IRQ pin. This prevents the COP from becoming
disabled as a result of external noise. During a break state, V

tst

on the

RST pin disables the COP module.

19.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An
illegal instruction sets the ILOP bit in the SIM reset status register
(SRSR) and causes a reset.

If the stop enable bit, STOP, in the mask option register is logic 0, the
SIM treats the STOP instruction as an illegal opcode and causes an
illegal opcode reset. The SIM actively pulls down the RST pin for all
internal reset sources.

19.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal
address reset. The SIM verifies that the CPU is fetching an opcode prior
to asserting the ILAD bit in the SIM reset status register (SRSR) and
resetting the MCU. A data fetch from an unmapped address does not
generate a reset. The SIM actively pulls down the RST pin for all internal
reset sources.

19.4.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when
the V

voltage falls to the LVI

TRIPF

voltage. The LVI bit in the SIM reset

status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four
CGMXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.

System Integration Module (SIM)

SIM Counter

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19.4.2.6 Monitor Mode Entry Module Reset (MODRST)

The monitor mode entry module reset (MODRST) asserts its output to
the SIM when monitor mode is entered in the condition where the reset
vectors are blank ($00). (See

Entering Monitor Mode

.) When MODRST

gets asserted, an internal reset occurs. The SIM actively pulls down the
RST pin for all internal reset sources.

19.5 SIM Counter

The SIM counter is used by the power-on reset module (POR) and in
stop mode recovery to allow the oscillator time to stabilize before
enabling the internal bus (IBUS) clocks. The SIM counter also serves as
a prescaler for the computer operating properly module (COP). The SIM
counter overflow supplies the clock for the COP module. The SIM
counter is 13 bits long and is clocked by the falling edge of CGMXCLK.

19.5.1 SIM Counter During Power-On Reset

The power-on reset module (POR) detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation module (CGM) to drive the
bus clock state machine.

19.5.2 SIM Counter During Stop Mode Recovery

The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the mask
option register. If the SSREC bit is a logic 1, then the stop recovery is
reduced from the normal delay of 4096 CGMXCLK cycles down to 32
CGMXCLK cycles. This is ideal for applications using canned oscillators
that do not require long startup times from stop mode. External crystal
applications should use the full stop recovery time, that is, with SSREC
cleared.

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19.5.3 SIM Counter and Reset States

External reset has no effect on the SIM counter. (See

Stop Mode

for

details.) The SIM counter is free-running after all reset states. (See

Active Resets from Internal Sources

for counter control and internal

reset recovery sequences.)

19.6 Exception Control

Normal, sequential program execution can be changed in three different
ways:

�

Interrupts:

�

Maskable hardware CPU interrupts

�

Non-maskable software interrupt instruction (SWI)

�

Reset

�

Break interrupts

19.6.1 Interrupts

At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.

Figure 19-8

shows interrupt entry timing.

Figure

19-9

shows interrupt recovery timing.

Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced (or the I bit is cleared). See

Figure

19-10

System Integration Module (SIM)

Exception Control

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285

condition code register) and if the corresponding interrupt enable bit is
set, the SIM proceeds with interrupt processing; otherwise, the next
instruction is fetched and executed.

If more than one interrupt is pending at the end of an instruction
execution, the highest priority interrupt is serviced first.

Figure 19-11

demonstrates what happens when two interrupts are pending. If an
interrupt is pending upon exit from the original interrupt service routine,
the pending interrupt is serviced before the LDA instruction is executed.

Figure 19-11

Interrupt Recognition Example

The LDA opcode is prefetched by both the INT1 and INT2 RTI
instructions. However, in the case of the INT1 RTI prefetch, this is a
redundant operation.

NOTE:

To maintain compatibility with the M6805 Family, the H register is not
pushed on the stack during interrupt entry. If the interrupt service routine
modifies the H register or uses the indexed addressing mode, software
should save the H register and then restore it prior to exiting the routine.

CLI

LDA

INT1

PULH
RTI

INT2

BACKGROUND

#$FF

PSHH

INT1 INTERRUPT SERVICE ROUTINE

PULH
RTI

PSHH

INT2 INTERRUPT SERVICE ROUTINE

ROUTINE

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19.6.4 Status Flag Protection in Break Mode

The SIM controls whether status flags contained in other modules can
be cleared during break mode. The user can select whether flags are
protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).

Protecting flags in break mode ensures that set flags will not be cleared
while in break mode. This protection allows registers to be freely read
and written during break mode without losing status flag information.

Setting the BCFE bit enables the clearing mechanisms. Once cleared in
break mode, a flag remains cleared even when break mode is exited.
Status flags with a 2-step clearing mechanism -- for example, a read of
one register followed by the read or write of another -- are protected,
even when the first step is accomplished prior to entering break mode.
Upon leaving break mode, execution of the second step will clear the flag
as normal.

19.7 Low-Power Modes

Executing the WAIT or STOP instruction puts the MCU in a low power-
consumption mode for standby situations. The SIM holds the CPU in a
non-clocked state. The operation of each of these modes is described in
the following subsections. Both STOP and WAIT clear the interrupt mask
(I) in the condition code register, allowing interrupts to occur.

19.7.1 Wait Mode

In wait mode, the CPU clocks are inactive while the peripheral clocks
continue to run.

Figure 19-15

shows the timing for wait mode entry.

A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred. In
wait mode, the CPU clocks are inactive. Refer to the wait mode
subsection of each module to see if the module is active or inactive in

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System Integration Module (SIM)

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Figure 19-17. Wait Recovery from Internal Reset

19.7.2 Stop Mode

In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.

The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.

NOTE:

External crystal applications should use the full stop recovery time by
clearing the SSREC bit.

A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).

The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.

Figure 19-18

shows stop mode entry timing.

NOTE:

To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.

IAB

IDB

RST

$A6

$6E0B

RST VCT H RST VCT L

$A6

CGMXCLK

CYCLES

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19.8.1 SIM Break Status Register

The SIM break status register (SBSR) contains a flag to indicate that a
break caused an exit from stop mode or wait mode.

SBSW -- SIM Break Stop/Wait

This status bit is useful in applications requiring a return to wait or stop
mode after exiting from a break interrupt. Clear SBSW by writing a
logic 0 to it. Reset clears SBSW.

1 = Stop mode or wait mode was exited by break interrupt.
0 = Stop mode or wait mode was not exited by break interrupt.

SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this. Writing 0 to the SBSW bit clears it.

Address:

$FE00

Bit 7

Bit 0

Read:

SBSW

Write:

Note

(1)

Reset:

= Reserved

Note: 1. Writing a logic 0 clears SBSW.

Figure 19-20. SIM Break Status Register (SBSR)

This code works if the H register has been pushed onto the stack in the break

service routine software. This code should be executed at the end of the break

service routine software.

HIBYTE

EQU

;

LOBYTE

EQU

;

If not SBSW, do RTI

;

BRCLR

SBSW,SBSR, RETURN

;

See if wait mode or stop mode was exited by

break.

TST

LOBYTE,SP

;If RETURNLO is not zero,

BNE

DOLO

;then just decrement low byte.

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ILAD -- Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR

MODRST -- Monitor Mode Entry Module Reset Bit

1 = Last reset caused by monitor mode entry when vector locations

$FFFE and $FFFF are $00 after POR while IRQ = V

0 = POR or read of SRSR

LVI -- Low-Voltage Inhibit Reset Bit

1 = Last reset caused by the LVI circuit
0 = POR or read of SRSR

19.8.3 SIM Break Flag Control Register

The SIM break control register contains a bit that enables software to
clear status bits while the MCU is in a break state.

BCFE -- Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing
status registers while the MCU is in a break state. To clear status bits
during the break state, the BCFE bit must be set.

1 = Status bits clearable during break
0 = Status bits not clearable during break

Address:

$FE03

Bit 7

Bit 0

Read:

BCFE

Write:

Reset:

= Reserved

Figure 19-22. SIM Break Flag Control Register (SBFCR)

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Section 20. Serial Peripheral Interface (SPI)

20.1 Contents

20.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

20.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

20.4

Pin Name Conventions and I/O Register Addresses . . . . . . . 298

20.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299

20.6

Transmission Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303

20.7

Queuing Transmission Data . . . . . . . . . . . . . . . . . . . . . . . . . . 309

20.8

Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 310

20.9

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314

20.10 Resetting the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316

20.11 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317

20.12 SPI During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . .318

20.13 I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318

20.14 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322

20.2 Introduction

This section describes the serial peripheral interface (SPI) module,
which allows full-duplex, synchronous, serial communications with
peripheral devices.

Serial Peripheral Interface (SPI)

Technical Data

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20.3 Features

Features of the SPI module include:

�

Full-duplex operation

�

Master and slave modes

�

Double-buffered operation with separate transmit and receive
registers

�

Four master mode frequencies (maximum = bus frequency

�

Maximum slave mode frequency = bus frequency

�

Serial clock with programmable polarity and phase

�

Two separately enabled interrupts:

�

SPRF (SPI receiver full)

�

SPTE (SPI transmitter empty)

�

Mode fault error flag with CPU interrupt capability

�

Overflow error flag with CPU interrupt capability

�

Programmable wired-OR mode

�

C (inter-integrated circuit) compatibility

�

I/O (input/output) port bit(s) software configurable with pullup
device(s) if configured as input port bit(s)

20.4 Pin Name Conventions and I/O Register Addresses

The text that follows describes the SPI. The SPI I/O pin names are SS
(slave select), SPSCK (SPI serial clock), CGND (clock ground), MOSI
(master out slave in), and MISO (master in/slave out). The SPI shares
four I/O pins with four parallel I/O ports.

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The SPR1 and SPR0 bits control the baud rate generator and determine
the speed of the shift register. See

SPI Status and Control Register

Through the SPSCK pin, the baud rate generator of the master also
controls the shift register of the slave peripheral.

As the byte shifts out on the MOSI pin of the master, another byte shifts
in from the slave on the master's MISO pin. The transmission ends when
the receiver full bit, SPRF, becomes set. At the same time that SPRF
becomes set, the byte from the slave transfers to the receive data
register. In normal operation, SPRF signals the end of a transmission.
Software clears SPRF by reading the SPI status and control register with
SPRF set and then reading the SPI data register. Writing to the SPI data
register clears the SPTE bit.

20.5.2 Slave Mode

The SPI operates in slave mode when the SPMSTR bit is clear. In slave
mode, the SPSCK pin is the input for the serial clock from the master
MCU. Before a data transmission occurs, the SS pin of the slave SPI
must be at logic 0. SS must remain low until the transmission is
complete. See

Mode Fault Error

In a slave SPI module, data enters the shift register under the control of
the serial clock from the master SPI module. After a byte enters the shift
register of a slave SPI, it transfers to the receive data register, and the
SPRF bit is set. To prevent an overflow condition, slave software then
must read the receive data register before another full byte enters the
shift register.

The maximum frequency of the SPSCK for an SPI configured as a slave
is the bus clock speed (which is twice as fast as the fastest master
SPSCK clock that can be generated). The frequency of the SPSCK for
an SPI configured as a slave does not have to correspond to any SPI
baud rate. The baud rate only controls the speed of the SPSCK
generated by an SPI configured as a master. Therefore, the frequency
of the SPSCK for an SPI configured as a slave can be any frequency
less than or equal to the bus speed.

Serial Peripheral Interface (SPI)

Transmission Formats

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When the master SPI starts a transmission, the data in the slave shift
register begins shifting out on the MISO pin. The slave can load its shift
register with a new byte for the next transmission by writing to its transmit
data register. The slave must write to its transmit data register at least
one bus cycle before the master starts the next transmission. Otherwise,
the byte already in the slave shift register shifts out on the MISO pin.
Data written to the slave shift register during a transmission remains in
a buffer until the end of the transmission.

When the clock phase bit (CPHA) is set, the first edge of SPSCK starts
a transmission. When CPHA is clear, the falling edge of SS starts a
transmission. See

Transmission Formats

NOTE:

SPSCK must be in the proper idle state before the slave is enabled to
prevent SPSCK from appearing as a clock edge.

20.6 Transmission Formats

During an SPI transmission, data is simultaneously transmitted (shifted
out serially) and received (shifted in serially). A serial clock synchronizes
shifting and sampling on the two serial data lines. A slave select line
allows selection of an individual slave SPI device; slave devices that are
not selected do not interfere with SPI bus activities. On a master SPI
device, the slave select line can optionally be used to indicate multiple-
master bus contention.

20.6.1 Clock Phase and Polarity Controls

Software can select any of four combinations of serial clock (SPSCK)
phase and polarity using two bits in the SPI control register (SPCR). The
clock polarity is specified by the CPOL control bit, which selects an
active high or low clock and has no significant effect on the transmission
format.

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The clock phase (CPHA) control bit selects one of two fundamentally
different transmission formats. The clock phase and polarity should be
identical for the master SPI device and the communicating slave device.
In some cases, the phase and polarity are changed between
transmissions to allow a master device to communicate with peripheral
slaves having different requirements.

NOTE:

Before writing to the CPOL bit or the CPHA bit, disable the SPI by
clearing the SPI enable bit (SPE).

20.6.2 Transmission Format When CPHA = 0

Figure 20-4

shows an SPI transmission in which CPHA is logic 0. The

figure should not be used as a replacement for data sheet parametric
information.

Two waveforms are shown for SPSCK: one for CPOL = 0 and another
for CPOL = 1. The diagram may be interpreted as a master or slave
timing diagram since the serial clock (SPSCK), master in/slave out
(MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. See

Mode Fault Error

. When CPHA = 0, the first SPSCK edge is the

MSB capture strobe. Therefore, the slave must begin driving its data
before the first SPSCK edge, and a falling edge on the SS pin is used to
start the slave data transmission. The slave's SS pin must be toggled
back to high and then low again between each byte transmitted as
shown in

Figure 20-5

Serial Peripheral Interface (SPI)

Transmission Formats

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Figure 20-4. Transmission Format (CPHA = 0)

Figure 20-5. CPHA/SS Timing

When CPHA = 0 for a slave, the falling edge of SS indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the falling edge of SS. Any data
written after the falling edge is stored in the transmit data register and
transferred to the shift register after the current transmission.

20.6.3 Transmission Format When CPHA = 1

Figure 20-6

shows an SPI transmission in which CPHA is logic 1. The

figure should not be used as a replacement for data sheet parametric
information. Two waveforms are shown for SPSCK: one for CPOL = 0
and another for CPOL = 1. The diagram may be interpreted as a master
or slave timing diagram since the serial clock (SPSCK), master in/slave

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

SPSCK CYCLE #

FOR REFERENCE

SPSCK; CPOL = 0

SPSCK; CPOL =1

MOSI

FROM MASTER

MISO

FROM SLAVE

SS; TO SLAVE

CAPTURE STROBE

BYTE 1

BYTE 3

MISO/MOSI

BYTE 2

MASTER SS

SLAVE SS

CPHA = 0

SLAVE SS

CPHA = 1

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out (MISO), and master out/slave in (MOSI) pins are directly connected
between the master and the slave. The MISO signal is the output from
the slave, and the MOSI signal is the output from the master. The SS line
is the slave select input to the slave. The slave SPI drives its MISO
output only when its slave select input (SS) is at logic 0, so that only the
selected slave drives to the master. The SS pin of the master is not
shown but is assumed to be inactive. The SS pin of the master must be
high or must be reconfigured as general-purpose I/O not affecting the
SPI. See

Mode Fault Error

. When CPHA = 1, the master begins driving

its MOSI pin on the first SPSCK edge. Therefore, the slave uses the first
SPSCK edge as a start transmission signal. The SS pin can remain low
between transmissions. This format may be preferable in systems
having only one master and only one slave driving the MISO data line.

Figure 20-6. Transmission Format (CPHA = 1)

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

LSB

MSB

SPSCK CYCLE #

FOR REFERENCE

SPSCK; CPOL = 0

SPSCK; CPOL =1

MOSI

FROM MASTER

MISO

FROM SLAVE

;

TO SLAVE

CAPTURE STROBE

Serial Peripheral Interface (SPI)

Transmission Formats

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When CPHA = 1 for a slave, the first edge of the SPSCK indicates the
beginning of the transmission. This causes the SPI to leave its idle state
and begin driving the MISO pin with the MSB of its data. Once the
transmission begins, no new data is allowed into the shift register from
the transmit data register. Therefore, the SPI data register of the slave
must be loaded with transmit data before the first edge of SPSCK. Any
data written after the first edge is stored in the transmit data register and
transferred to the shift register after the current transmission.

20.6.4 Transmission Initiation Latency

When the SPI is configured as a master (SPMSTR = 1), writing to the
SPDR starts a transmission. CPHA has no effect on the delay to the start
of the transmission, but it does affect the initial state of the SPSCK
signal. When CPHA = 0, the SPSCK signal remains inactive for the first
half of the first SPSCK cycle. When CPHA = 1, the first SPSCK cycle
begins with an edge on the SPSCK line from its inactive to its active
level. The SPI clock rate (selected by SPR1:SPR0) affects the delay
from the write to SPDR and the start of the SPI transmission. See

Figure

20-7

. The internal SPI clock in the master is a free-running derivative of

the internal MCU clock. To conserve power, it is enabled only when both
the SPE and SPMSTR bits are set. SPSCK edges occur halfway through
the low time of the internal MCU clock. Since the SPI clock is free-
running, it is uncertain where the write to the SPDR occurs relative to the
slower SPSCK. This uncertainty causes the variation in the initiation
delay shown in

Figure 20-7

. This delay is no longer than a single SPI bit

time. That is, the maximum delay is two MCU bus cycles for DIV2, eight
MCU bus cycles for DIV8, 32 MCU bus cycles for DIV32, and 128 MCU
bus cycles for DIV128.

Serial Peripheral Interface (SPI)

Queuing Transmission Data

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20.7 Queuing Transmission Data

The double-buffered transmit data register allows a data byte to be
queued and transmitted. For an SPI configured as a master, a queued
data byte is transmitted immediately after the previous transmission has
completed. The SPI transmitter empty flag (SPTE) indicates when the
transmit data buffer is ready to accept new data. Write to the transmit
data register only when the SPTE bit is high.

Figure 20-8

shows the

timing associated with doing back-to-back transmissions with the SPI
(SPSCK has CPHA: CPOL = 1:0).

Figure 20-8. .SPRF/SPTE CPU Interrupt Timing

The transmit data buffer allows back-to-back transmissions without the
slave precisely timing its writes between transmissions as in a system
with a single data buffer. Also, if no new data is written to the data buffer,
the last value contained in the shift register is the next data word to be
transmitted.

BIT

MOSI

SPSCK

SPTE

WRITE TO SPDR

CPU WRITES BYTE 2 TO SPDR, QUEUEING BYTE 2

CPU WRITES BYTE 1 TO SPDR, CLEARING SPTE BIT.

BYTE 1 TRANSFERS FROM TRANSMIT DATA

SPRF

READ SPSCR

MSB BIT

BIT

LSB MSB BIT

BIT

LSB MSB BIT

BYTE 2 TRANSFERS FROM TRANSMIT DATA

CPU WRITES BYTE 3 TO SPDR, QUEUEING BYTE

BYTE 3 TRANSFERS FROM TRANSMIT DATA

FIRST INCOMING BYTE TRANSFERS FROM SHIFT

CPU READS SPSCR WITH SPRF BIT SET.

SECOND INCOMING BYTE TRANSFERS FROM SHIFT

AND CLEARING SPTE BIT.

3 AND CLEARING SPTE BIT.

12 CPU READS SPDR, CLEARING SPRF BIT.

BIT

BYTE 1

BYTE 2

BYTE 3

READ SPDR

CPU READS SPDR, CLEARING SPRF BIT.

11 CPU READS SPSCR WITH SPRF BIT SET.

CPHA:CPOL = 1:0

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For an idle master or idle slave that has no data loaded into its transmit
buffer, the SPTE is set again no more than two bus cycles after the
transmit buffer empties into the shift register. This allows the user to
queue up a 16-bit value to send. For an already active slave, the load of
the shift register cannot occur until the transmission is completed. This
implies that a back-to-back write to the transmit data register is not
possible. The SPTE indicates when the next write can occur.

20.8 Error Conditions

The following flags signal SPI error conditions:

�

Overflow (OVRF) -- Failing to read the SPI data register before
the next full byte enters the shift register sets the OVRF bit. The
new byte does not transfer to the receive data register, and the
unread byte still can be read. OVRF is in the SPI status and control
register.

�

Mode fault error (MODF) -- The MODF bit indicates that the
voltage on the slave select pin (SS) is inconsistent with the mode
of the SPI. MODF is in the SPI status and control register.

20.8.1 Overflow Error

The overflow flag (OVRF) becomes set if the receive data register still
has unread data from a previous transmission when the capture strobe
of bit 1 of the next transmission occurs. The bit 1 capture strobe occurs
in the middle of SPSCK cycle 7. (See

Figure 20-4

and

Figure 20-6

.) If an

overflow occurs, all data received after the overflow and before the
OVRF bit is cleared does not transfer to the receive data register and
does not set the SPI receiver full bit (SPRF). The unread data that
transferred to the receive data register before the overflow occurred can
still be read. Therefore, an overflow error always indicates the loss of
data. Clear the overflow flag by reading the SPI status and control
register and then reading the SPI data register.

OVRF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF

Serial Peripheral Interface (SPI)

Error Conditions

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interrupts share the same CPU interrupt vector. See

Figure 20-11

. It is

not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.

If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition.

Figure 20-9

shows how it is possible to

miss an overflow. The first part of

Figure 20-9

shows how it is possible

to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.

Figure 20-9. Missed Read of Overflow Condition

In this case, an overflow can be missed easily. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it is not obvious
that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the
SPSCR following the read of the SPDR. This ensures that the OVRF
was not set before the SPRF was cleared and that future transmissions
can set the SPRF bit.

Figure 20-10

illustrates this process. Generally, to

avoid this second SPSCR read, enable the OVRF to the CPU by setting
the ERRIE bit.

READ

OVRF

SPRF

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 1 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

CPU READS BYTE 1 IN SPDR,

BYTE 2 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.

CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,

BYTE 4 FAILS TO SET SPRF BIT BECAUSE

CLEARING SPRF BIT.

BUT NOT OVRF BIT.

OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.

AND OVRF BIT CLEAR.

SPSCR

SPDR

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MOTOROLA

Figure 20-10. Clearing SPRF When OVRF Interrupt Is Not Enabled

20.8.2 Mode Fault Error

Setting the SPMSTR bit selects master mode and configures the
SPSCK and MOSI pins as outputs and the MISO pin as an input.
Clearing SPMSTR selects slave mode and configures the SPSCK and
MOSI pins as inputs and the MISO pin as an output. The mode fault bit,
MODF, becomes set any time the state of the slave select pin, SS, is
inconsistent with the mode selected by SPMSTR.

To prevent SPI pin contention and damage to the MCU, a mode fault
error occurs if:

�

The SS pin of a slave SPI goes high during a transmission

�

The SS pin of a master SPI goes low at any time

For the MODF flag to be set, the mode fault error enable bit (MODFEN)
must be set. Clearing the MODFEN bit does not clear the MODF flag but
does prevent MODF from being set again after MODF is cleared.

READ

OVRF

SPRF

BYTE 1

BYTE 2

BYTE 3

BYTE 4

BYTE 1 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

CPU READS BYTE 1 IN SPDR,

CPU READS SPSCR AGAIN

BYTE 2 SETS SPRF BIT.

CPU READS SPSCR WITH SPRF BIT SET

BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.

CPU READS BYTE 2 IN SPDR,

CPU READS SPSCR AGAIN

CPU READS BYTE 2 SPDR,

BYTE 4 SETS SPRF BIT.

CPU READS SPSCR.

CPU READS BYTE 4 IN SPDR,

CPU READS SPSCR AGAIN

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

CLEARING OVRF BIT.

CLEARING SPRF BIT.

TO CHECK OVRF BIT.

SPI RECEIVE

COMPLETE

AND OVRF BIT CLEAR.

SPSCR

SPDR

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MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE) is also set. The SPRF, MODF, and OVRF
interrupts share the same CPU interrupt vector. See

Figure 20-11

. It is

not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.

In a master SPI with the mode fault enable bit (MODFEN) set, the mode
fault flag (MODF) is set if SS goes to logic 0. A mode fault in a master
SPI causes the following events to occur:

�

If ERRIE = 1, the SPI generates an SPI receiver/error CPU
interrupt request.

�

The SPE bit is cleared.

�

The SPTE bit is set.

�

The SPI state counter is cleared.

�

The data direction register of the shared I/O port regains control of
port drivers.

NOTE:

To prevent bus contention with another master SPI after a mode fault
error, clear all SPI bits of the data direction register of the shared I/O port
before enabling the SPI.

When configured as a slave (SPMSTR = 0), the MODF flag is set if SS
goes high during a transmission. When CPHA = 0, a transmission begins
when SS goes low and ends once the incoming SPSCK goes back to its
idle level following the shift of the eighth data bit. When CPHA = 1, the
transmission begins when the SPSCK leaves its idle level and SS is
already low. The transmission continues until the SPSCK returns to its
idle level following the shift of the last data bit. See

Transmission

Formats

NOTE:

Setting the MODF flag does not clear the SPMSTR bit. The SPMSTR bit
has no function when SPE = 0. Reading SPMSTR when MODF = 1
shows the difference between a MODF occurring when the SPI is a
master and when it is a slave.

When CPHA = 0, a MODF occurs if a slave is selected (SS is at logic 0)
and later unselected (SS is at logic 1) even if no SPSCK is sent to that

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Serial Peripheral Interface (SPI)

MOTOROLA

slave. This happens because SS at logic 0 indicates the start of the
transmission (MISO driven out with the value of MSB) for CPHA = 0.
When CPHA = 1, a slave can be selected and then later unselected with
no transmission occurring. Therefore, MODF does not occur since a
transmission was never begun.

In a slave SPI (MSTR = 0), the MODF bit generates an SPI
receiver/error CPU interrupt request if the ERRIE bit is set. The MODF
bit does not clear the SPE bit or reset the SPI in any way. Software can
abort the SPI transmission by clearing the SPE bit of the slave.

NOTE:

A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high
impedance state. Also, the slave SPI ignores all incoming SPSCK
clocks, even if it was already in the middle of a transmission.

To clear the MODF flag, read the SPSCR with the MODF bit set and then
write to the SPCR register. This entire clearing mechanism must occur
with no MODF condition existing or else the flag is not cleared.

20.9 Interrupts

Four SPI status flags can be enabled to generate CPU interrupt
requests.

Table 20-2. SPI Interrupts

Flag

Request

SPTE

Transmitter empty

SPI transmitter CPU interrupt request

(DMAS = 0, SPTIE = 1, SPE = 1)

SPRF

Receiver full

SPI receiver CPU interrupt request

(DMAS = 0, SPRIE = 1)

OVRF

Overflow

SPI receiver/error interrupt request (ERRIE = 1)

MODF

Mode fault

SPI receiver/error interrupt request (ERRIE = 1)

Serial Peripheral Interface (SPI)

Interrupts

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Reading the SPI status and control register with SPRF set and then
reading the receive data register clears SPRF. The clearing mechanism
for the SPTE flag is always just a write to the transmit data register.

The SPI transmitter interrupt enable bit (SPTIE) enables the SPTE flag
to generate transmitter CPU interrupt requests, provided that the SPI is
enabled (SPE = 1).

The SPI receiver interrupt enable bit (SPRIE) enables the SPRF bit to
generate receiver CPU interrupt requests, regardless of the state of the
SPE bit. See

Figure 20-11

The error interrupt enable bit (ERRIE) enables both the MODF and
OVRF bits to generate a receiver/error CPU interrupt request.

The mode fault enable bit (MODFEN) can prevent the MODF flag from
being set so that only the OVRF bit is enabled by the ERRIE bit to
generate receiver/error CPU interrupt requests.

Figure 20-11. SPI Interrupt Request Generation

SPTE

SPTIE

SPRF

SPRIE

DMAS

ERRIE

MODF

OVRF

SPE

CPU INTERRUPT REQUEST

NOT AVAILABLE

SPI TRANSMITTER

NOT AVAILABLE

SPI RECEIVER/ERROR

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The following sources in the SPI status and control register can generate
CPU interrupt requests:

�

SPI receiver full bit (SPRF) -- The SPRF bit becomes set every
time a byte transfers from the shift register to the receive data
register. If the SPI receiver interrupt enable bit, SPRIE, is also set,
SPRF generates an SPI receiver/error CPU interrupt request.

�

SPI transmitter empty (SPTE) -- The SPTE bit becomes set every
time a byte transfers from the transmit data register to the shift
register. If the SPI transmit interrupt enable bit, SPTIE, is also set,
SPTE generates an SPTE CPU interrupt request.

20.10 Resetting the SPI

Any system reset completely resets the SPI. Partial resets occur
whenever the SPI enable bit (SPE) is low. Whenever SPE is low, the
following occurs:

�

The SPTE flag is set.

�

Any transmission currently in progress is aborted.

�

The shift register is cleared.

�

The SPI state counter is cleared, making it ready for a new
complete transmission.

�

All the SPI port logic is defaulted back to being general-purpose
I/O.

These items are reset only by a system reset:

�

All control bits in the SPCR register

�

All control bits in the SPSCR register (MODFEN, ERRIE, SPR1,
and SPR0)

�

The status flags SPRF, OVRF, and MODF

By not resetting the control bits when SPE is low, the user can clear SPE
between transmissions without having to set all control bits again when
SPE is set back high for the next transmission.

Serial Peripheral Interface (SPI)

Low-Power Modes

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By not resetting the SPRF, OVRF, and MODF flags, the user can still
service these interrupts after the SPI has been disabled. The user can
disable the SPI by writing 0 to the SPE bit. The SPI can also be disabled
by a mode fault occurring in an SPI that was configured as a master with
the MODFEN bit set.

20.11 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.

20.11.1 Wait Mode

The SPI module remains active after the execution of a WAIT instruction.
In wait mode the SPI module registers are not accessible by the CPU.
Any enabled CPU interrupt request from the SPI module can bring the
MCU out of wait mode.

If SPI module functions are not required during wait mode, reduce power
consumption by disabling the SPI module before executing the WAIT
instruction.

To exit wait mode when an overflow condition occurs, enable the OVRF
bit to generate CPU interrupt requests by setting the error interrupt
enable bit (ERRIE). See

Interrupts

20.11.2 Stop Mode

The SPI module is inactive after the execution of a STOP instruction.
The STOP instruction does not affect register conditions. SPI operation
resumes after an external interrupt. If stop mode is exited by reset, any
transfer in progress is aborted, and the SPI is reset.

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20.12 SPI During Break Interrupts

System Integration Module (SIM)

Since the SPTE bit cannot be cleared during a break with the BCFE bit
cleared, a write to the transmit data register in break mode does not
initiate a transmission nor is this data transferred into the shift register.
Therefore, a write to the SPDR in break mode with the BCFE bit cleared
has no effect.

20.13 I/O Signals

The SPI module has five I/O pins and shares four of them with a parallel
I/O port. They are:

�

MISO -- Data received

�

MOSI -- Data transmitted

�

SPSCK -- Serial clock

�

SS -- Slave select

�

CGND -- Clock ground (internally connected to V

)

The SPI has limited inter-integrated circuit (I

C) capability (requiring

software support) as a master in a single-master environment. To

Serial Peripheral Interface (SPI)

I/O Signals

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communicate with I

C peripherals, MOSI becomes an open-drain output

when the SPWOM bit in the SPI control register is set. In I

communication, the MOSI and MISO pins are connected to a
bidirectional pin from the I

C peripheral and through a pullup resistor to

20.13.1 MISO (Master In/Slave Out)

MISO is one of the two SPI module pins that transmits serial data. In full
duplex operation, the MISO pin of the master SPI module is connected
to the MISO pin of the slave SPI module. The master SPI simultaneously
receives data on its MISO pin and transmits data from its MOSI pin.

Slave output data on the MISO pin is enabled only when the SPI is
configured as a slave. The SPI is configured as a slave when its
SPMSTR bit is logic 0 and its SS pin is at logic 0. To support a multiple-
slave system, a logic 1 on the SS pin puts the MISO pin in a high-
impedance state.

When enabled, the SPI controls data direction of the MISO pin
regardless of the state of the data direction register of the shared I/O
port.

20.13.2 MOSI (Master Out/Slave In)

MOSI is one of the two SPI module pins that transmits serial data. In full-
duplex operation, the MOSI pin of the master SPI module is connected
to the MOSI pin of the slave SPI module. The master SPI simultaneously
transmits data from its MOSI pin and receives data on its MISO pin.

When enabled, the SPI controls data direction of the MOSI pin
regardless of the state of the data direction register of the shared I/O
port.

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Serial Peripheral Interface (SPI)

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20.13.3 SPSCK (Serial Clock)

The serial clock synchronizes data transmission between master and
slave devices. In a master MCU, the SPSCK pin is the clock output. In a
slave MCU, the SPSCK pin is the clock input. In full-duplex operation,
the master and slave MCUs exchange a byte of data in eight serial clock
cycles.

When enabled, the SPI controls data direction of the SPSCK pin
regardless of the state of the data direction register of the shared I/O
port.

20.13.4 SS (Slave Select)

The SS pin has various functions depending on the current state of the
SPI. For an SPI configured as a slave, the SS is used to select a slave.
For CPHA = 0, the SS is used to define the start of a transmission. See

Transmission Formats

. Since it is used to indicate the start of a

transmission, the SS must be toggled high and low between each byte
transmitted for the CPHA = 0 format. However, it can remain low
between transmissions for the CPHA = 1 format. See

Figure 20-12

Figure 20-12CPHA/SS Timing

When an SPI is configured as a slave, the SS pin is always configured
as an input. It cannot be used as a general-purpose I/O regardless of the
state of the MODFEN control bit. However, the MODFEN bit can still
prevent the state of the SS from creating a MODF error. See

SPI Status

and Control Register

NOTE:

A logic 1 voltage on the SS pin of a slave SPI puts the MISO pin in a high-
impedance state. The slave SPI ignores all incoming SPSCK clocks,
even if it was already in the middle of a transmission.

BYTE 1

BYTE 3

MISO/MOSI

BYTE 2

MASTER SS

SLAVE SS

CPHA = 0

SLAVE SS

CPHA = 1

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I/O Signals

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When an SPI is configured as a master, the SS input can be used in
conjunction with the MODF flag to prevent multiple masters from driving
MOSI and SPSCK. See

Mode Fault Error

. For the state of the SS pin to

set the MODF flag, the MODFEN bit in the SPSCK register must be set.
If the MODFEN bit is low for an SPI master, the SS pin can be used as
a general-purpose I/O under the control of the data direction register of
the shared I/O port. With MODFEN high, it is an input-only pin to the SPI
regardless of the state of the data direction register of the shared I/O
port.

The CPU can always read the state of the SS pin by configuring the
appropriate pin as an input and reading the port data register. See

Table

20-3

20.13.5 CGND (Clock Ground)

CGND is the ground return for the serial clock pin, SPSCK, and the
ground for the port output buffers. It is internally connected to V

shown in

Table 20-1

Table 20-3. SPI Configuration

SPE

SPMSTR

MODFEN

SPI Configuration

State of SS Logic

(1)

Not enabled

General-purpose I/O;

SS ignored by SPI

Slave

Input-only to SPI

Master without MODF

General-purpose I/O;

SS ignored by SPI

Master with MODF

Input-only to SPI

Note 1. X = Don't care

Serial Peripheral Interface (SPI)

I/O Registers

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323

SPRIE -- SPI Receiver Interrupt Enable Bit

This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.

1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled

DMAS --DMA Select Bit

This read only bit has no effect on this version of the SPI. This bit
always reads as a 0.

0 = SPRF DMA and SPTE DMA service requests disabled

(SPRF CPU and SPTE CPU interrupt requests enabled)

SPMSTR -- SPI Master Bit

This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.

1 = Master mode
0 = Slave mode

CPOL -- Clock Polarity Bit

This read/write bit determines the logic state of the SPSCK pin
between transmissions. (See

Figure 20-4

and

Figure 20-6

.) To

transmit data between SPI modules, the SPI modules must have
identical CPOL values. Reset clears the CPOL bit.

CPHA -- Clock Phase Bit

This read/write bit controls the timing relationship between the serial
clock and SPI data. (See

Figure 20-4

and

Figure 20-6

.) To transmit

data between SPI modules, the SPI modules must have identical
CPHA values. When CPHA = 0, the SS pin of the slave SPI module
must be set to logic 1 between bytes. See

Figure 20-12

. Reset sets

the CPHA bit.

SPWOM -- SPI Wired-OR Mode Bit

This read/write bit disables the pullup devices on pins SPSCK, MOSI,
and MISO so that those pins become open-drain outputs.

1 = Wired-OR SPSCK, MOSI, and MISO pins
0 = Normal push-pull SPSCK, MOSI, and MISO pins

Serial Peripheral Interface (SPI)

I/O Registers

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Serial Peripheral Interface (SPI)

325

SPRF -- SPI Receiver Full Bit

This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.

During an SPRF CPU interrupt, the CPU clears SPRF by reading the
SPI status and control register with SPRF set and then reading the
SPI data register.

Reset clears the SPRF bit.

1 = Receive data register full
0 = Receive data register not full

ERRIE -- Error Interrupt Enable Bit

This read/write bit enables the MODF and OVRF bits to generate
CPU interrupt requests. Reset clears the ERRIE bit.

1 = MODF and OVRF can generate CPU interrupt requests
0 = MODF and OVRF cannot generate CPU interrupt requests

OVRF -- Overflow Bit

This clearable, read-only flag is set if software does not read the byte
in the receive data register before the next full byte enters the shift
register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the
OVRF bit by reading the SPI status and control register with OVRF set
and then reading the receive data register. Reset clears the OVRF bit.

1 = Overflow
0 = No overflow

Address: $0011

Bit 7

Bit 0

Read:

SPRF

ERRIE

OVRF

MODF

SPTE

MODFEN

SPR1

SPR0

Write:

Reset:

= Unimplemented

Figure 20-14. SPI Status and Control Register (SPSCR)

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Serial Peripheral Interface (SPI)

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MODF -- Mode Fault Bit

This clearable, read-only flag is set in a slave SPI if the SS pin goes
high during a transmission with the MODFEN bit set. In a master SPI,
the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear the MODF bit by reading the SPI status and
control register (SPSCR) with MODF set and then writing to the SPI
control register (SPCR). Reset clears the MODF bit.

1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level

SPTE -- SPI Transmitter Empty Bit

This clearable, read-only flag is set each time the transmit data
register transfers a byte into the shift register. SPTE generates an
SPTE CPU interrupt request or an SPTE DMA service request if the
SPTIE bit in the SPI control register is set also.

NOTE:

Do not write to the SPI data register unless the SPTE bit is high.

During an SPTE CPU interrupt, the CPU clears the SPTE bit by
writing to the transmit data register.

Reset sets the SPTE bit.

1 = Transmit data register empty
0 = Transmit data register not empty

MODFEN -- Mode Fault Enable Bit

This read/write bit, when set to 1, allows the MODF flag to be set. If
the MODF flag is set, clearing the MODFEN does not clear the MODF
flag. If the SPI is enabled as a master and the MODFEN bit is low,
then the SS pin is available as a general-purpose I/O.

If the MODFEN bit is set, then this pin is not available as a general-
purpose I/O. When the SPI is enabled as a slave, the SS pin is not
available as a general-purpose I/O regardless of the value of
MODFEN. See

SS (Slave Select)

If the MODFEN bit is low, the level of the SS pin does not affect the
operation of an enabled SPI configured as a master. For an enabled
SPI configured as a slave, having MODFEN low only prevents the
MODF flag from being set. It does not affect any other part of SPI
operation. See

Mode Fault Error

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Timebase Module (TBM)

329

Technical Data -- MC68HC908GR8

Section 21. Timebase Module (TBM)

21.1 Contents

21.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

21.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

21.4

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330

21.5

Timebase Register Description. . . . . . . . . . . . . . . . . . . . . . . . 331

21.6

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

21.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333

21.2 Introduction

This section describes the timebase module (TBM). The TBM will
generate periodic interrupts at user selectable rates using a counter
clocked by the external crystal clock. This TBM version uses 15 divider
stages, eight of which are user selectable.

For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.

21.3 Features

Features of the TBM module include:

�

Software programmable 1 Hz, 4 Hz, 16 Hz, 256 Hz, 512 Hz, 1024
Hz, 2048 Hz, and 4096 Hz periodic interrupt using external 32.768
kHz crystal

�

User selectable oscillator clock source enable during stop mode to
allow periodic wakeup from stop

Timebase Module (TBM)

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Timebase Module (TBM)

MOTOROLA

21.4 Functional Description

NOTE:

This module is designed for a 32.768 kHz oscillator.

This module can generate a periodic interrupt by dividing the crystal
frequency, CGMXCLK. The counter is initialized to all 0s when TBON bit
is cleared. The counter, shown in

Figure 21-1

, starts counting when the

TBON bit is set. When the counter overflows at the tap selected by
TBR2:TBR0, the TBIF bit gets set. If the TBIE bit is set, an interrupt
request is sent to the CPU. The TBIF flag is cleared by writing a 1 to the
TACK bit. The first time the TBIF flag is set after enabling the timebase
module, the interrupt is generated at approximately half of the overflow
period. Subsequent events occur at the exact period.

Figure 21-1. Timebase Block Diagram

�

,
7

6
8

�

CGMXCLK

0 0 0

0 0 1

0 1 0

0 1 1

TBIF

TBR

TBIE

TBMINT

TBON

�

TAC

TBR

1 0 0

1 0 1

1 1 0

1 1 1

�

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Timebase Module (TBM)

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NOTE:

Do not change TBR2�TBR0 bits while the timebase is enabled
(TBON = 1).

TACK-- Timebase ACKnowledge

The TACK bit is a write-only bit and always reads as 0. Writing a logic
1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic
0 to this bit has no effect.

1 = Clear timebase interrupt flag
0 = No effect

TBIE -- Timebase Interrupt Enabled

This read/write bit enables the timebase interrupt when the TBIF bit
becomes set. Reset clears the TBIE bit.

1 = Timebase interrupt enabled
0 = Timebase interrupt disabled

TBON -- Timebase Enabled

This read/write bit enables the timebase. Timebase may be turned off
to reduce power consumption when its function is not necessary. The
counter can be initialized by clearing and then setting this bit. Reset
clears the TBON bit.

1 = Timebase enabled
0 = Timebase disabled and the counter initialized to 0s

21.6 Interrupts

The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2:TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

Timebase Module (TBM)

Low-Power Modes

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Timebase Module (TBM)

333

21.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.

21.7.1 Wait Mode

The timebase module remains active after execution of the WAIT
instruction. In wait mode, the timebase register is not accessible by the
CPU.

If the timebase functions are not required during wait mode, reduce the
power consumption by stopping the timebase before enabling the WAIT
instruction.

21.7.2 Stop Mode

If the oscillator has not been enabled to operate in stop mode, the
timebase module will not be active during STOP mode. In stop mode, the
timebase register is not accessible by the CPU.

If the timebase functions are not required during stop mode, reduce the
power consumption by stopping the timebase before enabling the STOP
instruction.

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Timer Interface Module (TIM)

335

Technical Data -- MC68HC908GR8

Section 22. Timer Interface Module (TIM)

22.1 Contents

22.2

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335

22.3

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

22.4

Pin Name Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336

22.5

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337

22.6

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346

22.7

Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347

22.8

TIM During Break Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 348

22.9

I/O Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348

22.10 I/O Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349

22.2 Introduction

This section describes the timer interface (TIM) module. The TIM on this
part is a 2-channel and a1-channel timer that provides a timing reference
with input capture, output compare, and pulse-width-modulation
functions.

Figure 22-1

is a block diagram of the TIM. This particular MCU

has two timer interface modules which are denoted as TIM1 and TIM2.

For further information regarding timers on M68HC08 family devices,
please consult the HC08 Timer Reference Manual, TIM08RM/AD.

Timer Interface Module (TIM)

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Timer Interface Module (TIM)

MOTOROLA

22.3 Features

Features of the TIM include:

�

Three input capture/output compare channels:

�

Rising-edge, falling-edge, or any-edge input capture trigger

�

Set, clear, or toggle output compare action

�

Buffered and unbuffered pulse-width-modulation (PWM) signal
generation

�

Programmable TIM clock input with 7-frequency internal bus clock
prescaler selection

�

Free-running or modulo up-count operation

�

Toggle any channel pin on overflow

�

TIM counter stop and reset bits

�

I/O port bit(s) software configurable with pullup device(s) if
configured as input port bit(s)

22.4 Pin Name Conventions

The text that follows describes both timers, TIM1 and TIM2. The TIM
input/output (I/O) pin names are T[1,2]CH0 (timer 1 channel 0, timer 2
channel 0) and T[1]CH1 (timer channel 1), where "1" is used to indicate
TIM1 and "2" is used to indicate TIM2. The two TIMs share three I/O pins
with three port D I/O port pins. The full names of the TIM I/O pins are
listed in

Table 22-1

The generic pin names appear in the text that

follows.

Table 22-1. Pin Name Conventions

TIM Generic Pin Names:

T[1,2]CH0

T[1,2]CH1

Full TIM

Pin Names:

TIM1

PTD4/ATD12/TBLCK

PTD5/T1CH1

TIM2

PTD6/ATD14/TACLK

Timer Interface Module (TIM)

Functional Description

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337

NOTE:

References to either timer 1 or timer 2 may be made in the following text
by omitting the timer number. For example, TCH0 may refer generically
to T1CH0 and T2CH0, and TCH1 will refer to T1CH1.

NOTE:

The Timer Interface Module in MC68HC908GR8 is constructed by TIM1
which is contained channel 0 and 1, and TIM2 which is contained
channel 0 only.

22.5 Functional Description

NOTE:

References to TCLK and external TIM clock input are only valid if the
MCU has an external TCLK pin. If the MCU has no external TCLK pin,
the TIM module must use the internal bus clock prescaler selections.

Figure 22-1

shows the structure of the TIM. The central component of

the TIM is the 16-bit TIM counter that can operate as a free-running
counter or a modulo up-counter. The TIM counter provides the timing
reference for the input capture and output compare functions. The TIM
counter modulo registers, TMODH:TMODL, control the modulo value of
the TIM counter. Software can read the TIM counter value at any time
without affecting the counting sequence.

The TIM channels (per timer) are programmable independently as input
capture or output compare channels. If a channel is configured as input
capture, then an internal pullup device may be enabled for that channel.
See

Port D Input Pullup Enable Register

Timer Interface Module (TIM)

Functional Description

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Timer Interface Module (TIM)

339

Figure 22-2

summarizes the timer registers.

Addr.

Register Name

Bit 7

Bit 0

$0020

Timer 1 Status and Control

Read:

TOF

TOIE

TSTOP

PS2

PS1

PS0

Write:

TRST

Reset:

$0021

Timer 1 Counter Register

High (T1CNTH)

Read:

Bit 15

Bit 8

Write:

Reset:

$0022

Timer 1 Counter Register

Low (T1CNTL)

Read:

Bit 7

Bit 0

Write:

Reset:

$0023

Timer 1 Counter Modulo

Read:

Bit 15

Bit 8

Write:

Reset:

$0024

Timer 1 Counter Modulo

Read:

Bit 7

Bit 0

Write:

Reset:

$0025

Timer 1 Channel 0 Status

and Control Register

(T1SC0)

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

$0026

Timer 1 Channel 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

$0027

Timer 1 Channel 0

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

$0028

Timer 1 Channel 1 Status

and Control Register

(T1SC1)

Read:

CH1F

CH1IE

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

Write:

Reset:

$0029

Timer 1 Channel 1

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

$002A

Timer 1 Channel 1

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

$002B

Timer 2 Status and Control

Read:

TOF

TOIE

TSTOP

PS2

PS1

PS0

Write:

TRST

Reset:

$002C

Timer 2 Counter Register

High (T2CNTH)

Read:

Bit 15

Bit 8

Write:

Reset:

= Unimplemented

Figure 22-2. TIM I/O Register Summary (Sheet 1 of 2)

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Timer Interface Module (TIM)

MOTOROLA

22.5.1 TIM Counter Prescaler

The TIM clock source can be one of the seven prescaler outputs or the
TIM clock pin, TCLK. The prescaler generates seven clock rates from
the internal bus clock. The prescaler select bits, PS[2:0], in the TIM
status and control register select the TIM clock source.

$002D

Timer 2 Counter Register

Low (T2CNTL)

Read:

Bit 7

Bit 0

Write:

Reset:

$002E

Timer 2 Counter Modulo

Read:

Bit 15

Bit 8

Write:

Reset:

$002F

Timer 2 Counter Modulo

Read:

Bit 7

Bit 0

Write:

Reset:

$0030

Timer 2 Channel 0 Status

and Control Register

(T2SC0)

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

$0031

Timer 2 Channel 0

Read:

Bit 15

Bit 8

Write:

Reset:

Indeterminate after reset

$0032

Timer 2 Channel 0

Read:

Bit 7

Bit 0

Write:

Reset:

Indeterminate after reset

$0033

Unimplemented

Read:

Write:

Reset:

$0034

Unimplemented

Read:

Write:

Reset:

Indeterminate after reset

$0035

Unimplemented

Read:

Write:

Reset:

Indeterminate after reset

Addr.

Register Name

Bit 7

Bit 0

= Unimplemented

Figure 22-2. TIM I/O Register Summary (Sheet 2 of 2)

Timer Interface Module (TIM)

Functional Description

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Timer Interface Module (TIM)

341

22.5.2 Input Capture

With the input capture function, the TIM can capture the time at which an
external event occurs. When an active edge occurs on the pin of an input
capture channel, the TIM latches the contents of the TIM counter into the
TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is
programmable. Input captures can generate TIM CPU interrupt
requests.

22.5.3 Output Compare

With the output compare function, the TIM can generate a periodic pulse
with a programmable polarity, duration, and frequency. When the
counter reaches the value in the registers of an output compare channel,
the TIM can set, clear, or toggle the channel pin. Output compares can
generate TIM CPU interrupt requests.

22.5.4 Unbuffered Output Compare

Any output compare channel can generate unbuffered output compare
pulses as described in

Output Compare

. The pulses are unbuffered

because changing the output compare value requires writing the new
value over the old value currently in the TIM channel registers.

An unsynchronized write to the TIM channel registers to change an
output compare value could cause incorrect operation for up to two
counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new
value prevents any compare during that counter overflow period. Also,
using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass
the new value before it is written.

Use the following methods to synchronize unbuffered changes in the
output compare value on channel x:

Timer Interface Module (TIM)

Technical Data

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342

Timer Interface Module (TIM)

MOTOROLA

�

When changing to a smaller value, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current output compare pulse. The interrupt routine has until
the end of the counter overflow period to write the new value.

�

When changing to a larger output compare value, enable TIM
overflow interrupts and write the new value in the TIM overflow
interrupt routine. The TIM overflow interrupt occurs at the end of
the current counter overflow period. Writing a larger value in an
output compare interrupt routine (at the end of the current pulse)
could cause two output compares to occur in the same counter
overflow period.

22.5.5 Buffered Output Compare

Channels 0 and 1 can be linked to form a buffered output compare
channel whose output appears on the TCH0 pin. The TIM channel
registers of the linked pair alternately control the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The output compare value in the TIM
channel 0 registers initially controls the output on the TCH0 pin. Writing
to the TIM channel 1 registers enables the TIM channel 1 registers to
synchronously control the output after the TIM overflows. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
output are the ones written to last. TSC0 controls and monitors the
buffered output compare function, and TIM channel 1 status and control
register (TSC1) is unused. While the MS0B bit is set, the channel 1 pin,
TCH1, is available as a general-purpose I/O pin.

NOTE:

In buffered output compare operation, do not write new output compare
values to the currently active channel registers. User software should
track the currently active channel to prevent writing a new value to the
active channel. Writing to the active channel registers is the same as
generating unbuffered output compares.

Timer Interface Module (TIM)

Functional Description

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Timer Interface Module (TIM)

343

22.5.6 Pulse Width Modulation (PWM)

By using the toggle-on-overflow feature with an output compare channel,
the TIM can generate a PWM signal. The value in the TIM counter
modulo registers determines the period of the PWM signal. The channel
pin toggles when the counter reaches the value in the TIM counter
modulo registers. The time between overflows is the period of the PWM
signal.

Figure 22-3

shows, the output compare value in the TIM channel

registers determines the pulse width of the PWM signal. The time
between overflow and output compare is the pulse width. Program the
TIM to clear the channel pin on output compare if the state of the PWM
pulse is logic 1. Program the TIM to set the pin if the state of the PWM
pulse is logic 0.

The value in the TIM counter modulo registers and the selected
prescaler output determines the frequency of the PWM output. The
frequency of an 8-bit PWM signal is variable in 256 increments. Writing
$00FF (255) to the TIM counter modulo registers produces a PWM
period of 256 times the internal bus clock period if the prescaler select
value is $000. See

TIM Status and Control Register

Figure 22-3. PWM Period and Pulse Width

The value in the TIM channel registers determines the pulse width of the
PWM output. The pulse width of an 8-bit PWM signal is variable in 256

PTEx/TCHx

PERIOD

PULSE
WIDTH

OVERFLOW

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

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Timer Interface Module (TIM)

MOTOROLA

increments. Writing $0080 (128) to the TIM channel registers produces
a duty cycle of 128/256 or 50%.

22.5.7 Unbuffered PWM Signal Generation

Any output compare channel can generate unbuffered PWM pulses as
described in

Pulse Width Modulation (PWM)

. The pulses are unbuffered

because changing the pulse width requires writing the new pulse width
value over the old value currently in the TIM channel registers.

An unsynchronized write to the TIM channel registers to change a pulse
width value could cause incorrect operation for up to two PWM periods.
For example, writing a new value before the counter reaches the old
value but after the counter reaches the new value prevents any compare
during that PWM period. Also, using a TIM overflow interrupt routine to
write a new, smaller pulse width value may cause the compare to be
missed. The TIM may pass the new value before it is written.

Use the following methods to synchronize unbuffered changes in the
PWM pulse width on channel x:

�

When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.

�

When changing to a longer pulse width, enable TIM overflow
interrupts and write the new value in the TIM overflow interrupt
routine. The TIM overflow interrupt occurs at the end of the current
PWM period. Writing a larger value in an output compare interrupt
routine (at the end of the current pulse) could cause two output
compares to occur in the same PWM period.

NOTE:

In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.

Timer Interface Module (TIM)

Functional Description

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345

22.5.8 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the TCH0 pin. The TIM channel registers of the linked
pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)
links channel 0 and channel 1. The TIM channel 0 registers initially
control the pulse width on the TCH0 pin. Writing to the TIM channel 1
registers enables the TIM channel 1 registers to synchronously control
the pulse width at the beginning of the next PWM period. At each
subsequent overflow, the TIM channel registers (0 or 1) that control the
pulse width are the ones written to last. TSC0 controls and monitors the
buffered PWM function, and TIM channel 1 status and control register
(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,
is available as a general-purpose I/O pin.

NOTE:

In buffered PWM signal generation, do not write new pulse width values
to the currently active channel registers. User software should track the
currently active channel to prevent writing a new value to the active
channel. Writing to the active channel registers is the same as
generating unbuffered PWM signals.

22.5.9 PWM Initialization

To ensure correct operation when generating unbuffered or buffered
PWM signals, use the following initialization procedure:

1. In the TIM status and control register (TSC):

a. Stop the TIM counter by setting the TIM stop bit, TSTOP.

b. Reset the TIM counter and prescaler by setting the TIM reset

bit, TRST.

2. In the TIM counter modulo registers (TMODH:TMODL), write the

value for the required PWM period.

3. In the TIM channel x registers (TCHxH:TCHxL), write the value for

the required pulse width.

4. In TIM channel x status and control register (TSCx):

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a. Write 0:1 (for unbuffered output compare or PWM signals) or

1:0 (for buffered output compare or PWM signals) to the
mode select bits, MSxB:MSxA. See

Table 22-3

b. Write 1 to the toggle-on-overflow bit, TOVx.

c. Write 1:0 (to clear output on compare) or 1:1 (to set output on

compare) to the edge/level select bits, ELSxB:ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See

Table 22-3

NOTE:

In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to self-
correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.

5. In the TIM status control register (TSC), clear the TIM stop bit,

TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels.

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM
overflows. Subsequent output compares try to force the output to a state
it is already in and have no effect. The result is a 0% duty cycle output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the
TOVx bit generates a 100% duty cycle output. (See

TIM Channel Status

and Control Registers

22.6 Interrupts

The following TIM sources can generate interrupt requests:

Timer Interface Module (TIM)

Low-Power Modes

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�

TIM overflow flag (TOF) -- The TOF bit is set when the TIM
counter value reaches the modulo value programmed in the TIM
counter modulo registers. The TIM overflow interrupt enable bit,
TOIE, enables TIM overflow CPU interrupt requests. TOF and
TOIE are in the TIM status and control register.

�

TIM channel flags (CH1F:CH0F) -- The CHxF bit is set when an
input capture or output compare occurs on channel x. Channel x
TIM CPU interrupt requests and TIM DMA service requests are
controlled by the channel x interrupt enable bit, CHxIE. Channel x
TIM CPU interrupt requests are enabled when CHxIE = 1. CHxF
and CHxIE are in the TIM channel x status and control register.
DMAxS is in the TIM DMA select register.

22.7 Low-Power Modes

The WAIT and STOP instructions put the MCU in low power-
consumption standby modes.

22.7.1 Wait Mode

The TIM remains active after the execution of a WAIT instruction. In wait
mode, the TIM registers are not accessible by the CPU. Any enabled
CPU interrupt request from the TIM can bring the MCU out of wait mode.

If TIM functions are not required during wait mode, reduce power
consumption by stopping the TIM before executing the WAIT instruction.

22.7.2 Stop Mode

The TIM is inactive after the execution of a STOP instruction. The STOP
instruction does not affect register conditions or the state of the TIM
counter. TIM operation resumes when the MCU exits stop mode after an
external interrupt.

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22.8 TIM During Break Interrupts

A break interrupt stops the TIM counter.

SIM Break Flag Control Register

22.9 I/O Signals

Port D shares three of its pins with the TIM. (There is an optional TCLK
which can be used as an external clock input to the TIM prescaler, but is
not available on this MCU.) The three TIM channel I/O pins are T1CH0,
T1CH1 and T2CH0 as described in

Pin Name Conventions

Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. T1CH0 and T2CH0 can be
configured as buffered output compare or buffered PWM pins.

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TOF -- TIM Overflow Flag Bit

This read/write flag is set when the TIM counter reaches the modulo
value programmed in the TIM counter modulo registers. Clear TOF by
reading the TIM status and control register when TOF is set and then
writing a logic 0 to TOF. If another TIM overflow occurs before the
clearing sequence is complete, then writing logic 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to
inadvertent clearing of TOF. Reset clears the TOF bit. Writing a logic
1 to TOF has no effect.

1 = TIM counter has reached modulo value
0 = TIM counter has not reached modulo value

TOIE -- TIM Overflow Interrupt Enable Bit

This read/write bit enables TIM overflow interrupts when the TOF bit
becomes set. Reset clears the TOIE bit.

1 = TIM overflow interrupts enabled
0 = TIM overflow interrupts disabled

TSTOP -- TIM Stop Bit

This read/write bit stops the TIM counter. Counting resumes when
TSTOP is cleared. Reset sets the TSTOP bit, stopping the TIM
counter until software clears the TSTOP bit.

1 = TIM counter stopped
0 = TIM counter active

NOTE:

Do not set the TSTOP bit before entering wait mode if the TIM is required
to exit wait mode.

TRST -- TIM Reset Bit

Setting this write-only bit resets the TIM counter and the TIM
prescaler. Setting TRST has no effect on any other registers.
Counting resumes from $0000. TRST is cleared automatically after
the TIM counter is reset and always reads as logic 0. Reset clears the
TRST bit.

1 = Prescaler and TIM counter cleared
0 = No effect

NOTE:

Setting the TSTOP and TRST bits simultaneously stops the TIM counter
at a value of $0000.

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CHxF -- Channel x Flag Bit

When channel x is an input capture channel, this read/write bit is set
when an active edge occurs on the channel x pin. When channel x is
an output compare channel, CHxF is set when the value in the TIM
counter registers matches the value in the TIM channel x registers.

When TIM CPU interrupt requests are enabled (CHxIE = 1), clear
CHxF by reading TIM channel x status and control register with CHxF
set and then writing a logic 0 to CHxF. If another interrupt request
occurs before the clearing sequence is complete, then writing logic 0
to CHxF has no effect. Therefore, an interrupt request cannot be lost
due to inadvertent clearing of CHxF.

Reset clears the CHxF bit. Writing a logic 1 to CHxF has no effect.

1 = Input capture or output compare on channel x
0 = No input capture or output compare on channel x

CHxIE -- Channel x Interrupt Enable Bit

This read/write bit enables TIM CPU interrupt service requests on
channel x.

Reset clears the CHxIE bit.

1 = Channel x CPU interrupt service requests enabled
0 = Channel x CPU interrupt service requests disabled

MSxB -- Mode Select Bit B

This read/write bit selects buffered output compare/PWM operation.
MSxB exists only in the TIM1 channel 0 and TIM2 channel 0 status
and control registers.

Setting MS0B disables the channel 1 status and control register and
reverts TCH1 to general-purpose I/O.

Reset clears the MSxB bit.

1 = Buffered output compare/PWM operation enabled
0 = Buffered output compare/PWM operation disabled

MSxA -- Mode Select Bit A

When ELSxB:A

00, this read/write bit selects either input capture

operation or unbuffered output compare/PWM operation. See

Table

22-3

1 = Unbuffered output compare/PWM operation

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Timer Interface Module (TIM)

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NOTE:

Before enabling a TIM channel register for input capture operation, make
sure that the PTD/TCHx pin is stable for at least two bus clocks.

TOVx -- Toggle On Overflow Bit

When channel x is an output compare channel, this read/write bit
controls the behavior of the channel x output when the TIM counter
overflows. When channel x is an input capture channel, TOVx has no
effect. Reset clears the TOVx bit.

1 = Channel x pin toggles on TIM counter overflow.
0 = Channel x pin does not toggle on TIM counter overflow.

NOTE:

When TOVx is set, a TIM counter overflow takes precedence over a
channel x output compare if both occur at the same time.

Table 22-3. Mode, Edge, and Level Selection

MSxB:MSxA

ELSxB:ELSxA

Mode

Configuration

Output preset

Pin under port control;
initial output level high

Pin under port control;

initial output level low

Input capture

Capture on rising edge only

Capture on falling edge only

Capture on rising or

falling edge

Output

compare or

PWM

Toggle output on compare

Clear output on compare

Set output on compare

Buffered

output

compare or

buffered PWM

Toggle output on compare

Clear output on compare

Set output on compare

Timer Interface Module (TIM)

I/O Registers

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CHxMAX -- Channel x Maximum Duty Cycle Bit

When the TOVx bit is at logic 1, setting the CHxMAX bit forces the
duty cycle of buffered and unbuffered PWM signals to 100%. As

CHxMAX Latency

shows, the CHxMAX bit takes effect in the cycle

after it is set or cleared. The output stays at the 100% duty cycle level
until the cycle after CHxMAX is cleared.

Figure 22-13. CHxMAX Latency

22.10.6 TIM Channel Registers

These read/write registers contain the captured TIM counter value of the
input capture function or the output compare value of the output
compare function. The state of the TIM channel registers after reset is
unknown.

In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the
TIM channel x registers (TCHxH) inhibits input captures until the low
byte (TCHxL) is read.

In output compare mode (MSxB:MSxA

0:0), writing to the high byte of

the TIM channel x registers (TCHxH) inhibits output compares until the
low byte (TCHxL) is written.

OUTPUT

OVERFLOW

PTEx/TCHx

PERIOD

CHxMAX

OVERFLOW

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

OUTPUT

COMPARE

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Section 23. Electrical Specifications

23.1 Contents