Document Outline

• List of Sections
• Table of Contents
• List of Figures
• List of Tables
• Section 1. General Description
  • 1.1 Contents
  • 1.2 Introduction
  • 1.3 Features
  • 1.4 MCU Block Diagram
  • 1.5 Pin Assignments
  • 1.6 Pin Functions
• Section 2. Memory
  • 2.1 Contents
  • 2.2 Introduction
  • 2.3 I/O Section
  • 2.4 Monitor ROM
• Section 3. Random-Access Memory (RAM)
  • 3.1 Contents
  • 3.2 Introduction
  • 3.3 Functional Description
• Section 4. FLASH Memory (FLASH)
  • 4.1 Contents
  • 4.2 Introduction
  • 4.3 Functional Description
  • 4.4 FLASH Control Register
  • 4.5 FLASH Block Erase Operation
  • 4.6 FLASH Mass Erase Operation
  • 4.7 FLASH Program Operation
  • 4.8 FLASH Protection
  • 4.9 FLASH Block Protect Register
• Section 5. Configuration Register (CONFIG)
  • 5.1 Contents
  • 5.2 Introduction
  • 5.3 Functional Description
• Section 6. Central Processor Unit (CPU)
  • 6.1 Contents
  • 6.2 Introduction
  • 6.3 Features
  • 6.4 CPU Registers
    • 6.4.1 Accumulator
    • 6.4.2 Index Register
    • 6.4.3 Stack Pointer
    • 6.4.4 Program Counter
    • 6.4.5 Condition Code Register
  • 6.5 Arithmetic/Logic Unit (ALU)
  • 6.6 Low-Power Modes
    • 6.6.1 Wait Mode
    • 6.6.2 Stop Mode
  • 6.7 CPU During Break Interrupts
  • 6.8 Instruction Set Summary
  • 6.9 Opcode Map
• Section 7. System Integration Module (SIM)
  • 7.1 Contents
  • 7.2 Introduction
  • 7.3 SIM Bus Clock Control and Generation
    • 7.3.1 Bus Timing
    • 7.3.2 Clock Start-Up from POR
    • 7.3.3 Clocks in Stop Mode and Wait Mode
  • 7.4 Reset and System Initialization
    • 7.4.1 External Pin Reset
    • 7.4.2 Active Resets from Internal Sources
      • 7.4.2.1 Power-On Reset
      • 7.4.2.2 Computer Operating Properly (COP) Reset
      • 7.4.2.3 Illegal Opcode Reset
      • 7.4.2.4 Illegal Address Reset
      • 7.4.2.5 LVI Reset
  • 7.5 SIM Counter
    • 7.5.1 SIM Counter During Power-On Reset
    • 7.5.2 SIM Counter During Stop Mode Recovery
    • 7.5.3 SIM Counter and Reset States
  • 7.6 Exception Control
    • 7.6.1 Interrupts
      • 7.6.1.1 Hardware Interrupts
      • 7.6.1.2 SWI Instruction
    • 7.6.2 Interrupt Status Registers
      • 7.6.2.1 Interrupt Status Register 1
      • 7.6.2.2 Interrupt Status Register 2
      • 7.6.2.3 Interrupt Status Register 3
    • 7.6.3 Reset
    • 7.6.4 Break Interrupts
    • 7.6.5 Status Flag Protection in Break Mode
  • 7.7 Low-Power Modes
    • 7.7.1 Wait Mode
    • 7.7.2 Stop Mode
  • 7.8 SIM Registers
    • 7.8.1 Break Status Register (BSR)
    • 7.8.2 Reset Status Register (RSR)
    • 7.8.3 Break Flag Control Register (BFCR)
• Section 8. Oscillator (OSC)
  • 8.1 Contents
  • 8.2 Introduction
  • 8.3 X-tal Oscillator (MC68HC908xxx)
  • 8.4 RC Oscillator (MC68HRC908xxx)
  • 8.5 I/O Signals
    • 8.5.1 Crystal Amplifier Input Pin (OSC1)
    • 8.5.2 Crystal Amplifier Output Pin (OSC2/PTA6/RCCLK)
    • 8.5.3 Oscillator Enable Signal (SIMOSCEN)
    • 8.5.4 X-tal Oscillator Clock (XTALCLK)
    • 8.5.5 RC Oscillator Clock (RCCLK)
    • 8.5.6 Oscillator Out 2 (2OSCOUT)
    • 8.5.7 Oscillator Out (OSCOUT)
  • 8.6 Low Power Modes
    • 8.6.1 Wait Mode
    • 8.6.2 Stop Mode
  • 8.7 Oscillator During Break Mode
• Section 9. Monitor ROM (MON)
  • 9.1 Contents
  • 9.2 Introduction
  • 9.3 Features
  • 9.4 Functional Description
    • 9.4.1 Entering Monitor Mode
    • 9.4.2 Baud Rate
    • 9.4.3 Data Format
    • 9.4.4 Echoing
    • 9.4.5 Break Signal
    • 9.4.6 Commands
  • 9.5 Security
• Section 10. Timer Interface Module (TIM)
  • 10.1 Contents
  • 10.2 Introduction
  • 10.3 Features
  • 10.4 Pin Name Conventions
  • 10.5 Functional Description
    • 10.5.1 TIM Counter Prescaler
    • 10.5.2 Input Capture
    • 10.5.3 Output Compare
      • 10.5.3.1 Unbuffered Output Compare
      • 10.5.3.2 Buffered Output Compare
    • 10.5.4 Pulse Width Modulation (PWM)
      • 10.5.4.1 Unbuffered PWM Signal Generation
      • 10.5.4.2 Buffered PWM Signal Generation
      • 10.5.4.3 PWM Initialization
  • 10.6 Interrupts
  • 10.7 Wait Mode
  • 10.8 TIM During Break Interrupts
  • 10.9 I/O Signals
  • 10.10 I/O Registers
    • 10.10.1 TIM Status and Control Register (TSC)
    • 10.10.2 TIM Counter Registers (TCNTH:TCNTL)
    • 10.10.3 TIM Counter Modulo Registers (TMODH:TMODL)
    • 10.10.4 TIM Channel Status and Control Registers (TSC0:TSC1)
    • 10.10.5 TIM Channel Registers (TCH0H/L:TCH1H/L)
• Section 11. Analog-to-Digital Converter (ADC)
  • 11.1 Contents
  • 11.2 Introduction
  • 11.3 Features
  • 11.4 Functional Description
    • 11.4.1 ADC Port I/O Pins
    • 11.4.2 Voltage Conversion
    • 11.4.3 Conversion Time
    • 11.4.4 Continuous Conversion
    • 11.4.5 Accuracy and Precision
  • 11.5 Interrupts
  • 11.6 Low-Power Modes
    • 11.6.1 Wait Mode
    • 11.6.2 Stop Mode
  • 11.7 I/O Signals
    • 11.7.1 ADC Voltage In (ADCVIN)
  • 11.8 I/O Registers
    • 11.8.1 ADC Status and Control Register
    • 11.8.2 ADC Data Register
    • 11.8.3 ADC Input Clock Register
• Section 12. I/O Ports
  • 12.1 Contents
  • 12.2 Introduction
  • 12.3 Port A
  • 12.4 Port A Data Register (PTA)
    • 12.4.1 Data Direction Register A (DDRA)
    • 12.4.2 Port A Input Pull-up Enable Register (PTAPUE)
  • 12.5 Port B
    • 12.5.1 Port B Data Register (PTB)
    • 12.5.2 Data Direction Register B (DDRB)
  • 12.6 Port D
    • 12.6.1 Port D Data Register (PTD)
    • 12.6.2 Data Direction Register D (DDRD)
    • 12.6.3 Port D Control Register (PDCR)
• Section 13. External Interrupt (IRQ)
  • 13.1 Contents
  • 13.2 Introduction
  • 13.3 Features
  • 13.4 Functional Description
    • 13.4.1 IRQ1 Pin
  • 13.5 IRQ Module During Break Interrupts
  • 13.6 IRQ Status and Control Register (ISCR)
• Section 14. Keyboard Interrupt Module (KBI)
  • 14.1 Contents
  • 14.2 Introduction
  • 14.3 Features
  • 14.4 Functional Description
    • 14.4.1 Keyboard Initialization
    • 14.4.2 Keyboard Status and Control Register
    • 14.4.3 Keyboard Interrupt Enable Register
  • 14.5 Wait Mode
  • 14.6 Stop Mode
  • 14.7 Keyboard Module During Break Interrupts
• Section 15. Computer Operating Properly (COP)
  • 15.1 Contents
  • 15.2 Introduction
  • 15.3 Functional Description
  • 15.4 I/O Signals
    • 15.4.1 2OSCOUT
    • 15.4.2 COPCTL Write
    • 15.4.3 Power-On Reset
    • 15.4.4 Internal Reset
    • 15.4.5 Reset Vector Fetch
    • 15.4.6 COPD (COP Disable)
    • 15.4.7 COPRS (COP Rate Select)
  • 15.5 COP Control Register
  • 15.6 Interrupts
  • 15.7 Monitor Mode
  • 15.8 Low-Power Modes
    • 15.8.1 Wait Mode
    • 15.8.2 Stop Mode
  • 15.9 COP Module During Break Mode
• Section 16. Low Voltage Inhibit (LVI)
  • 16.1 Contents
  • 16.2 Introduction
  • 16.3 Features
  • 16.4 Functional Description
  • 16.5 LVI Control Register (CONFIG2/CONFIG1)
  • 16.6 Low-Power Modes
    • 16.6.1 Wait Mode
    • 16.6.2 Stop Mode
• Section 17. Break Module (BREAK)
  • 17.1 Contents
  • 17.2 Introduction
  • 17.3 Features
  • 17.4 Functional Description
    • 17.4.1 Flag Protection During Break Interrupts
    • 17.4.2 CPU During Break Interrupts
    • 17.4.3 TIM During Break Interrupts
    • 17.4.4 COP During Break Interrupts
  • 17.5 Break Module Registers
    • 17.5.1 Break Status and Control Register (BRKSCR)
    • 17.5.2 Break Address Registers
    • 17.5.3 Break Status Register
    • 17.5.4 Break Flag Control Register (BFCR)
  • 17.6 Low-Power Modes
    • 17.6.1 Wait Mode
    • 17.6.2 Stop Mode
• Section 18. Electrical Specifications
  • 18.1 Contents
  • 18.2 Introduction
  • 18.3 Absolute Maximum Ratings
  • 18.4 Functional Operating Range
  • 18.5 Thermal Characteristics
  • 18.6 5V DC Electrical Characteristics
  • 18.7 5V Control Timing
  • 18.8 5V Oscillator Characteristics
  • 18.9 3V DC Electrical Characteristics
  • 18.10 3V Control Timing
  • 18.11 3V Oscillator Characteristics
  • 18.12 Typical Supply Currents
  • 18.13 ADC Characteristics
  • 18.14 Memory Characteristics
• Section 19. Mechanical Specifications
  • 19.1 Contents
  • 19.2 Introduction
  • 19.3 20-Pin PDIP
  • 19.4 20-Pin SOIC
  • 19.5 28-Pin PDIP
  • 19.6 28-Pin SOIC
• Section 20. Ordering Information
  • 20.1 Contents
  • 20.2 Introduction
  • 20.3 MC Order Numbers