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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
1
REV 0
Motorola, Inc. 1995
10/95
Product Preview
8-Bit Serial or Parallel-Input/
Serial-Output Shift Register
HighPerformance SiliconGate CMOS
The MC54/74HC165A is identical in pinout to the LS165. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device is an 8bit shift register with complementary outputs from the
last stage. Data may be loaded into the register either in parallel or in serial
form. When the Serial Shift/Parallel Load input is low, the data is loaded
asynchronously in parallel. When the Serial Shift/Parallel Load input is high,
the data is loaded serially on the rising edge of either Clock or Clock Inhibit
(see the Function Table).
The 2input NOR clock may be used either by combining two independent
clock sources or by designating one of the clock inputs to act as a clock
inhibit.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 286 FETs or 71.5 Equivalent Gates
FUNCTION TABLE
Inputs
Internal Stages
Output
Operation
Serial Shift/
Parallel Load
Clock
Clock
Inhibit
SA
A H
QA
QB
QH
Operation
L
X
X
X
a
...
h
a
b
h
Asynchronous Parallel Load
H
H
L
L
L
H
X
X
L
H
QAn
QAn
QGn
QGn
Serial Shift via Clock
H
H
L
L
L
H
X
X
L
H
QAn
QAn
QGn
QGn
Serial Shift via Clock Inhibit
H
H
X
H
H
X
X
X
X
X
No Change
Inhibited Clock
H
L
L
X
X
No Change
No Clock
X = don't care
QAn QGn = Data shifted from the preceding stage
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
MC54/74HC165A
PIN ASSIGNMENT
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
B
C
D
CLOCK INHIBIT
VCC
QH
SA
A
F
E
CLOCK
SERIAL SHIFT/
PARALLEL LOAD
GND
QH
H
G
D SUFFIX
SOIC PACKAGE
CASE 751B05
N SUFFIX
PLASTIC PACKAGE
CASE 64808
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
1
16
1
16
J SUFFIX
CERAMIC PACKAGE
CASE 62010
1
16
1
16
DT SUFFIX
TSSOP PACKAGE
CASE 948F01
LOGIC DIAGRAM
PIN 16 = VCC
PIN 8 = GND
11
12
13
14
3
4
5
6
10
A
B
C
D
E
F
G
H
SA
PARALLEL
DATA
INPUTS
SERIAL
DATA
INPUT
SERIAL SHIFT/
PARALLEL LOAD
1
2
15
CLOCK
CLOCK INHIBIT
9
7
QH
QH
SERIAL
DATA
OUTPUTS
MC54/74HC165A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
2
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
VCC
DC Supply Voltage (Referenced to GND)
0.5 to + 7.0
V
Vin
DC Input Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
20
mA
Iout
DC Output Current, per Pin
25
mA
ICC
DC Supply Current, VCC and GND Pins
50
mA
PD
Power Dissipation in Still Air, Plastic or Ceramic DIP
SOIC Package
TSSOP Package
750
500
450
mW
Tstg
Storage Temperature
65 to + 150
_
C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
(Ceramic DIP)
260
300
_
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
Derating -- Plastic DIP: 10 mW/
_
C from 65
_
to 125
_
C
Ceramic DIP: 10 mW/
_
C from 100
_
to 125
_
C
SOIC Package: 7 mW/
_
C from 65
_
to 125
_
C
TSSOP Package: 6.1 mW/
_
C from 65
_
to 125
_
C
For high frequency or heavy load considerations, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Max
Unit
VCC
DC Supply Voltage (Referenced to GND)
2.0
6.0
V
Vin, Vout
DC Input Voltage, Output Voltage (Referenced to GND)
0
VCC
V
TA
Operating Temperature, All Package Types
55
+ 125
_
C
tr, tf
Input Rise and Fall Time
VCC = 2.0 V
(Figure 1)
VCC = 3.0 V
VCC = 4.5 V
VCC = 6.0 V
0
0
0
1000
600
500
400
ns
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
Parameter
Test Conditions
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
Test Conditions
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
VIH
Minimum HighLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
VIL
Maximum LowLevel Input
Voltage
Vout = 0.1 V or VCC 0.1 V
|Iout|
v
20
A
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
0.5
0.9
1.35
1.80
V
VOH
Minimum HighLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
Vin = VIH or VIL |Iout|
v
2.4 mA
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.20
3.70
5.20
V
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND
v
(Vin or Vout)
v
VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
MC54/74HC165A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
3
MOTOROLA
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
Unit
Guaranteed Limit
VCC
V
Test Conditions
Parameter
Symbol
Unit
v
125
_
C
v
85
_
C
55 to
25
_
C
VCC
V
Test Conditions
Parameter
Symbol
VOL
Maximum LowLevel Output
Voltage
Vin = VIH or VIL
|Iout|
v
20
A
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
Vin = VIH or VIL |Iout|
v
2.4 mA
|Iout|
v
4.0 mA
|Iout|
v
5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
Iin
Maximum Input Leakage Current
Vin = VCC or GND
6.0
0.1
1.0
1.0
A
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0
A
6.0
4
40
160
A
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS
(CL = 50 pF, Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 8)
2.0
3.0
4.5
6.0
10
15
30
50
9
14
28
45
8
12
25
40
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock (or Clock Inhibit) to QH or QH
(Figures 1 and 8)
2.0
3.0
4.5
6.0
110
36
22
19
125
45
26
23
160
60
32
28
ns
tPLH,
tPHL
Maximum Propagation Delay, Serial Shift/Parallel Load to QH or QH
(Figures 2 and 8)
2.0
3.0
4.5
6.0
85
57
25
19
96
63
29
23
106
71
32
27
ns
tPLH,
tPHL
Maximum Propagation Delay, Input H to QH or QH
(Figures 3 and 8)
2.0
3.0
4.5
6.0
110
36
22
19
125
45
26
23
160
60
32
28
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 8)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
Cin
Maximum Input Capacitance
--
10
10
10
pF
NOTES:
1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
2. Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
CPD
Power Dissipation Capacitance (Per Package)*
Typical @ 25
C, VCC = 5.0 V
pF
CPD
Power Dissipation Capacitance (Per Package)*
40
pF
* Used to determine the noload dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of the
Motorola HighSpeed CMOS Data Book (DL129/D).
MC54/74HC165A
MOTOROLA
HighSpeed CMOS Logic Data
DL129 -- Rev 6
4
TIMING REQUIREMENTS
(Input tr = tf = 6 ns)
Symbol
Parameter
VCC
V
Guaranteed Limit
Unit
Symbol
Parameter
VCC
V
55 to
25
_
C
v
85
_
C
v
125
_
C
Unit
tsu
Minimum Setup Time, Parallel Data Inputs to Serial Shift/Parallel Load
(Figure 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
Minimum Setup Time, Input SA to Clock (or Clock Inhibit)
(Figure 5)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
Minimum Setup Time, Serial Shift/Parallel Load to Clock (or Clock Inhibit)
(Figure 6)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tsu
Minimum Setup Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
th
Minimum Hold Time, Serial Shift/Parallel Load to Parallel Data Inputs
(Figure 4)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
ns
th
Minimum Hold Time, Clock (or Clock Inhibit) to Input SA
(Figure 5)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
ns
th
Minimum Hold Time, Clock (or Clock Inhibit) to Serial Shift/Parallel Load
(Figure 6)
2.0
3.0
4.5
6.0
1
1
1
1
1
1
1
1
1
1
1
1
ns
trec
Minimum Recovery Time, Clock to Clock Inhibit
(Figure 7)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
tw
Minimum Pulse Width, Clock (or Clock Inhibit)
(Figure 1)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
tw
Minimum Pulse width, Serial Shift/Parallel Load
(Figure 2)
2.0
3.0
4.5
6.0
70
27
15
13
90
32
19
16
100
36
22
19
ns
tr, tf
Maximum Input Rise and Fall Times
(Figure 1)
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
ns
NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola HighSpeed CMOS Data Book (DL129/D).
MC54/74HC165A
HighSpeed CMOS Logic Data
DL129 -- Rev 6
5
MOTOROLA
PIN DESCRIPTIONS
INPUTS
A, B, C, D, E, F, G, H (Pins 11, 12, 13, 14, 3, 4, 5, 6)
Parallel Data inputs. Data on these inputs are asynchro-
nously entered in parallel into the internal flipflops when the
Serial Shift/Parallel Load input is low.
SA (Pin 10)
Serial Data input. When the Serial Shift/Parallel Load input
is high, data on this pin is serially entered into the first stage
of the shift register with the rising edge of the Clock.
CONTROL INPUTS
Serial Shift/Parallel Load (Pin 1)
Dataentry control input. When a high level is applied to
this pin, data at the Serial Data input (SA) are shifted into the
register with the rising edge of the Clock. When a low level is
applied to this pin, data at the Parallel Data inputs are
asynchronously loaded into each of the eight internal stages.
Clock, Clock Inhibit (Pins 2, 15)
Clock inputs. These two clock inputs function identically.
Either may be used as an activehigh clock inhibit. However,
to avoid double clocking, the inhibit input should go high only
while the clock input is high.
The shift register is completely static, allowing Clock rates
down to DC in a continuous or intermittent mode.
OUTPUTS
QH, QH (Pins 9, 7)
Complementary Shift Register outputs. These pins are the
noninverted and inverted outputs of the eighth stage of the
shift register.
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