MC141622EVK
1
MOTOROLA
ACF-II Evaluation Board Operating Manual
1. SUMMARY
The MC141622EVK is a development board for evaluation of the MC141622. In addition to the
MC141622, the MC141622EVK contains all the analog circuit that is necessary for buffering both the
input and output video signal and generation of the 4xfsc clock. By connecting an external signal source,
monitor, and power supply, it is possible to evaluate all the operating modes on the MC141622.
2. SPECIFICATION
Board Dimensions
100 mm (Length) x 150 mm (Width)
Y/C Separation LSI
MC141622FU Mount
Video Input Amplifier
MC14577 2SC2002 Use
Video Output Amplifier
MC14576 Use
Clamp Circuit
2SC2002 2SA953 Use
Clock Generator
MC1378P Use
Clock Buffer Amplifier
MC14576 Use
Analog Input/Output Interface
BNC Connector x3, S Terminal Output Mount
Digital Input/Output Interface
16 Pin Header Mount
Action Mode
MC141622 Supports All Operating Modes
Regulator
MC7805CT Use
Recommended Supply Voltage
+ 10 V
Operating Temperature
0 to 50
C
Supply Current
350 mA
Order this document
by MC141622EVK/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MC141622EVK
Motorola, Inc. 1997
REV 3
1/97 TN97012000
MC141622EVK
MOTOROLA
2
3. BOARD OPERATION
3.1 ACFII Operating Mode
AFCII has four operating modes. Any one of these modes can be selected using the digital code input
to MODE 0 and MODE 1 using ROTARY SW. The function of each mode is as follows.
(1) Normal fsc Mode
This is the mode for usual Y/C separation. It separates Y/C from the video signal that is input to the A/D
converter.
The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 C3
(block level parameter), C4 C7 (white level parameter), and D4 D7 (noise slice level parameter).
The clock is a 3.579545 MHz subcarrier input to the CLK connector; the builtin 4x PLL generates 4xfsc
clock.
(2) Normal 4xfsc Mode
This mode is used for Y/C separation. It separates Y/C from the video signal that is input to the A/D con-
verter.
The coring parameter of the vertical enhancer can be set up by the digital code that is input to C0 C3
(block level parameter), C4 C7 (white level parameter), and D4 D7 (noise slice level parameter).
The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector.
(3) Digital Input Comb Filter Mode
This mode uses the A/D converter, filter, and D/A converter as two independent blocks. The digital data
converted by the A/D converter is output on C0 C7. Data input on D0 D7 is processed by the ACFII.
Filtering is performed by the algorithm of ACFII and the Y/C video is output as analog signals from Yout
and Cout. These two blocks can operate with input clock signals that have different frequencies or phases
and can be operated independently by using the CLK(AD) for the A/D converter, and the CLK input for
the D/A converter.
The clock is 14.31818 MHz which is a 4x subcarrier input to the CLK connector and the CLK(AD) con-
nector.
(4) Digital Output Comb Filter Mode
In addition to the normal Y/C analog outputs, the MC141622EVK can provide the Y/C signals as digital
luminance and chrominance signals. The digital luminance data is output on C0 C7 and the digital
chrominance data is output on D0 D7. This digital data can be modified by other digital processing.
MC141622EVK
3
MOTOROLA
The following table is the assignment for the operating mode.
MODE Switching Function
Mode
MODE1
MODE0
Rotary SW
Normal fsc Mode
L
L
0
Normal 4xfsc Mode
L
H
1
Digital Input Comb Filtering Mode
H
L
2
Digital Output Comb Filtering Mode
H
H
3
4. BK FUNCTION
By setting the BK pin (toggle SW1) to the H level, composite video is output on the Yout pin and the chro-
minance signal on the Cout pin.
The following table is the function of the BK pin.
BK Function
BK Pin
Yout Pin
Cout Pin
L
Luminance
Chrominance
H
Composite
Chrominance
4.1 Vertical Enhancer Function
By setting the VH pin (toggle SW2) to the L level, the vertical enhancer feature is enabled. The coring
parameter of the vertical enhancer can be set up every 1 LSB by the digital code that are input to
C0 C3 (black level parameter), C4 C7 (white level parameter), and D4 D7 (noise slice level param-
eter.
The set up level of the coring parameter and characteristics are as follows.
Coring Characteristics
OUT
IN
WHITE
BLACK
OUT
IN
WHITE LEVEL
(C4 C7)
(0 15 STEP)
OUT
IN
BLACK LEVEL
(C0 C3)
(0 16 STEP)
OUT
IN
NOISE LEVEL
(D4 D7)
(0 15 STEP)
Vertical Enhancer Function
VH Pin
Vertical Enhancer
L
On
H
Off
Coring Parameter Set Up
C7
C6
C5
C4
L
l
C3
C2
C1
C0
Level
D7
D6
D5
D4
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
0
1
2
3
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
4
5
6
7
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
8
9
A
B
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
C
D
E
F
MC141622EVK
MOTOROLA
4
4.2 Clock Generator Compounding
The clock generator (MC1378P) provides the necessary reference oscillator and phase locks the clock to
the color subcarrier by inputting the composite video signal.
VC1 adjusts the horizontal VCO to synchronize the output of the burst gate (pin 5 on the MC1378P) with
the input video signal. VC2 adjusts the chroma VCO for maximum amplitude output from the clock buffer
(pin 1 on the MC14576).
VR3 adjusts pullin of the chroma PLL filter. This is usually fixed to the center position. VR4 selects the
dc bias for the clock buffer output and is usually 2.25 V.
4.3 Video Amplifier Adjustment
On the video amplifier (MC14577), the gain is adjusted by VR1. This sets the input range
(3.0 Vpp) of the A/D converter in MC141622FU.
VR2 is the clamp level adjustment. This adjusts the sync tip clamping of the input video signal to the
video amplifier.
4.4 Outside Interface
The outside interface should provide a composite video input signal to BNC1. The MC141622EVK pro-
vides Y/C separation and outputs the luminance from BNC2 and the color signal from BNC3. There is an
S output connector on this board for easy connection to instruments having an S input connector.
BNC4 and BNC5 are for the external input of each CLK and CLK(AD). However, when using these, it is
necessary to modify the board pattern; i.e., cut (J5, J6).
There is no filter for bandwidth limitations on this board beyond that imposed by the bandwidth limitations
of the MC14577 buffer amplifier. To minimize noise resulting from excessive bandwidth, the bandwidth of
input video signal should be limited to no more than one half of the clock frequency.
MC141622EVK
5
MOTOROLA
5. MC141622EVK CIRCUIT
CLK(AD)
BNCS
40
+
CLK
BNC4
+
+
+
+
+
+
+
+
1/2MC14678
+
2/2MC14678
+
+
+
+
+
+
+
+
+
+
+
+
+
+
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0.1
F
1.0
F
470 k
0.1
F
0.0047 F
160
30 pF
0.02 F
1.8 k
1
F
2.2 k
4 MHz
CER. RES.
680
14.3 MHz
17.7 MHz
MC1378P
MC14576
1
2
3
4
5
6
7
8
0.1
F
7.5 m
1 m
0.1
F
47
F
4.7
F
47
F
0.1
F
0.1
F
33
H
47 k
x 8
D4
D5
D6
D7
C0
C1
C2
C3
C4
C5
C6
C7
PCO
FL
IN
REF(DA)
I
GND(AD)
CC
BIAS
Y
out
C
out
GND(DA)
D3
D2
D1
D0
BK
GND (D)
V
CC(D)
VH
FSC
NC
NC
NC
10 k
x 2
47
F
0.1
F
33
H
TE1
TE0
MODE1
MODE0
CLK(AD)
GND(D)
V
CC(D)
CLC
CL
out
V
in
RBT
RTP
33
H
V
CC(A)
10 V
Y
out
BNC2
C
out
BNC3
1
2
3
4
5
6
7
8
8
4
7 k
7 k
9.1 k
47
F
47
F
47
F
0.1
F
0.1
F
47
F
0.1
F
10 k
47
F
0.1
F
33
H
33
H
0.1
F
10
F
0.33
F
1 m
750 k
0.1
F
4.7
F
MC7805CT
V
CC(A)
(5 V)
V
out
V
in
GND
MC141622
1
2
3
4
5
6
7
8
9
10 11
12
15
16
17
18
19
20
13
14
48
39
38
37
36 35 34
33 32 31
30
29 28 27 26 25
24
23
22
21
41
42
43
44
45
46
47
48
ADC GND
DAC GND
DIGITAL GND
TANTALUM CAPACITOR
MULTILAYER CERAMIC CAPACITOR
C2002
MC14677
1
2
3
4
8
47
F
0.1
F
0.1
F
47
F
33
H
160
VIDEO IN
BNC1
1.0
F
CLAMP
LEVEL
2.2
k
A953
C2002
2 k
10 k
x 8
ROTARY SW
47
F
0.1
F
V
CC(D)
5 V
V
CC(D)
5 V
GAIN ADJUST
1 k
610
47
F
30 pF
750 k
1 k
J6
V
CC(A)
10 V
SW
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
0.1
F
1.0
F
1.0
F
1.0
F
0.1
F
33
H
0.001 F
+
1.0
F
5
10 k
x 8
47 k
x 8
J5
V
CC(D)
5 V
33
H
33
H
0.1 F
0.1
F
10
F
V
CC(A)
(10 V)
0.1
F
4.7
F
1.0
F
2 k
2.2
k
2.2
k
33
H
V
CC(DA)
V
CC(AD)
47 k x 4
610 k
43 k
200
OV
bias
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