MCM6323A
1
MOTOROLA FAST SRAM
Product Preview
64K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6323A is a 1,048,576 bit static random access memory organized
as 65,536 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes; CMOS circuitry reduces power consumption and provides for
greater reliability.
The MCM6323A is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus contention
problems. Separate byte enable controls (LB and UB) allow individual bytes to be
written and read. LB controls the 8 DQa bits, while UB controls the 8 DQb bits.
The MCM6323A is available in a 400 mil smalloutline Jleaded (SOJ) pack-
age and a 44lead TSOP Type II package in copper leadframe for optimum
printed circuit board (PCB) reliability.
Single 3.3 V
0.3 V Power Supply
Fast Access Time: 10, 12, 15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 140/135/130 mA Maximum, Active AC
Industrial Temperature Option: 40 to + 85
C
Part Number: SCM6323AYJ10A
BLOCK DIAGRAM
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFERS
WRITE
ENABLE
BUFFER
BYTE
ENABLE
BUFFER
ROW
DECODER
COLUMN
DECODER
64K x 16
BIT
MEMORY
ARRAY
HIGH
BYTE
OUTPUT
BUFFER
8
HIGH
BYTE
WRITE
DRIVER
LOW
BYTE
OUTPUT
BUFFER
LOW
BYTE
WRITE
DRIVER
SENSE
AMPS
G
W
LB
8
8
8
8
8
8
8
9
A
CHIP
ENABLE
BUFFER
E
UB
7
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
16
16
8
DQb
8
DQa
This document contains information on a new product under development. Motorola reserves the right
to change or discontinue this product without notice.
Order this document
by MCM6323A/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM6323A
YJ PACKAGE
400 MIL SOJ
CASE 91901
PIN ASSIGNMENT
A
Address Input
. . . . . . . . . . . . . . . . . . . . . . . .
E
Chip Enable
. . . . . . . . . . . . . . . . . . . . . . . . .
W
Write Enable
. . . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable
. . . . . . . . . . . . . . . . . . . . . .
UB
Upper Byte
. . . . . . . . . . . . . . . . . . . . . . . .
LB
Lower Byte
. . . . . . . . . . . . . . . . . . . . . . . . .
DQa
Lower Data Input/Output
. . . . . . . . . . . .
DQb
Upper Data Input/Output
. . . . . . . . . . . .
VDD
+ 3.3 V Power Supply
. . . . . . . . . . . . . .
VSS
Ground
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
No Connection
. . . . . . . . . . . . . . . . . . . . .
PIN NAMES
5
4
3
2
1
10
9
8
7
6
11
36
37
38
39
40
41
42
35
43
44
34
E
A
A
A
A
DQa
DQa
A
VDD
DQa
DQa
UB
G
A
A
A
DQb
DQb
DQb
VSS
DQb
LB
25
26
27
28
29
30
31
24
32
33
23
12
13
14
15
16
17
18
19
20
21
22
DQb
DQb
DQb
DQb
VDD
A
A
A
NC
A
NC
W
DQa
DQa
DQa
VSS
A
A
DQa
NC
A
A
TS PACKAGE
44LEAD
TSOP TYPE II
CASE 924A01
REV 1
10/17/97
Motorola, Inc. 1997
MCM6323A
2
MOTOROLA FAST SRAM
TRUTH TABLE
(X = Don't Care)
E
G
W
LB
UB
Mode
VDD Current
DQa's
DQb's
H
X
X
X
X
Not Selected
ISB1, ISB2
HighZ
HighZ
L
H
H
X
X
Output Disabled
IDDA
HighZ
HighZ
L
X
X
H
H
Output Disabled
IDDA
HighZ
HighZ
L
L
H
L
H
Low Byte Read
IDDA
Dout
HighZ
L
L
H
H
L
High Byte Read
IDDA
HighZ
Dout
L
L
H
L
L
Word Read
IDDA
Dout
Dout
L
X
L
L
H
Low Byte Write
IDDA
Din
HighZ
L
X
L
H
L
High Byte Write
IDDA
HighZ
Din
L
X
L
L
L
Word Write
IDDA
Din
Din
ABSOLUTE MAXIMUM RATINGS
(See Notes)
Rating
Symbol
Value
Unit
Supply Voltage
VDD
0.5 to + 4.6
V
Voltage on Any Pin
Vin
0.5 to VDD + 0.5
V
Output Current per Pin
Iout
20
mA
Package Power Dissipation
PD
.75
W
Temperature Under Bias
Commerial
Industrial
Tbias
10 to + 85
45 to + 90
C
Operating Temperature
Commerial
Industrial
TA
0 to + 70
40 to + 85
C
Storage Temperature
Tstg
55 to + 150
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid appli-
cation of any voltage higher than maximum
rated voltages to these highimpedance cir-
cuits.
This CMOS memory circuit has been de-
signed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board
and transverse air flow of at least 500 linear feet
per minute is maintained.
MCM6323A
3
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
0.3 V, TA = 0 to 70
C, Unless Otherwise Noted)
(TA = 40 to + 85
C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.2
--
VDD + 0.3
**
V
Input Low Voltage
VIL
0.5
*
--
0.8
V
* VIL (min) = 0.5 V dc; VIL (min) = 2.0 V ac (pulse width
20 ns) for I
20.0 mA.
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width
20 ns) for I
20.0 mA.
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Ilkg(I)
--
1.0
A
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Ilkg(O)
--
1.0
A
Output Low Voltage
(IOL = + 4.0 mA)
(IOL = + 100
A)
VOL
--
0.4
VSS + 0.2
V
Output High Voltage
(IOH = 4.0 mA)
(IOH = 100
A)
VOH
2.4
VDD 0.2
--
V
POWER SUPPLY CURRENTS
(See Note 1)
Parameter
Symbol
6323A10
6323A12
6323A15
Unit
Notes
AC Active Supply Current (Iout = 0 mA)
Commerical
(VDD = max, f = fmax)
Industrial
IDDA
140
150
135
140
130
135
mA
2
AC Standby Current (E = VIH, VDD = max,
Commerical
f = fmax)
Industrial
ISB1
40
45
35
40
30
35
mA
2
CMOS Standby Current (VDD = max, f = 0 MHz,
Commerical
E
VDD 0.2 V, Vin
VSS + 0.2 V,
Industrial
or
VDD 0.2 V)
ISB2
5
5
5
5
5
5
mA
NOTES:
1. Typical current = 25
C @ 3.3 V.
2. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V, VIH = 3.0 V, VIL = 0 V).
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Address Input Capacitance
Cin
--
6
pF
Control Input Capacitance
Cin
--
6
pF
Input/Output Capacitance
CI/O
--
8
pF
MCM6323A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
0.3 V, TA = 0 to +70
C, Unless Otherwise Noted)
(TA = 40 to + 85
C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level
1.50 V
. . . . . . . .
Logic Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
2 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.50 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING
(See Notes 1, 2, 3, and 4)
P
S
b l
MCM6323A10
MCM6323A12
MCM6323A15
U i
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
10
--
12
--
15
--
ns
5
Address Access Time
tAVQV
--
10
--
12
--
15
ns
Enable Access Time
tELQV
--
10
--
12
--
15
ns
Output Enable Access Time
tGLQV
--
4
--
5
--
6
ns
6
Output Hold from Address Change
tAXQX
3
--
3
--
3
--
ns
Enable Low to Output Active
tELQX
3
--
3
--
3
--
ns
6, 7, 8
Output Enable Low to Output Active
tGLQX
0
--
0
--
0
--
ns
6, 7, 8
Enable High to Output HighZ
tEHQZ
--
4
--
5
--
6
ns
6, 7, 8
Output Enable High to Output HighZ
tGHQZ
--
4
--
5
--
6
ns
6, 7, 8
Byte Enable Access Time
tBLQV
--
4
--
5
--
6
ns
Byte Enable Low to Output Active
tBLQX
0
--
0
--
0
--
ns
6, 7, 8
Byte High to Output HighZ
tBHQZ
0
5
0
5
0
5
ns
6, 7, 8
NOTES:
1. W is high for read cycle.
2. For common I/O applications, minimization, or elimination of bus contention conditions is necessary during read and write cycles.
3. Device is continuously selected (E = VIL, G = VIL, and LB and/or UB = VIL).
4. Addresses valid prior to or coincident with E going low.
5. All read cycle timings are referenced from the last valid address to the first transitioning address.
6. Transition is measured 200 mV from steadystate voltage.
7. At any given voltage and temperature, tEHQZ (max) < tELQX (min), and tGHQZ (max) < tGLQX (min), both for a given device and from
device to device.
8. This parameter is sampled and not 100% tested.
MCM6323A
5
MOTOROLA FAST SRAM
OUTPUT
Z0 = 50
RL = 50
1.5 V
Figure 1. Equivalent AC Test Load
30 pF
Figure 2. Lumped Capacitive Load and Typical Derating Curve
1.5
1.0
0.5
0
0.5
LUMPED CAPACITANCE, CL (pF)
@ T = 25
C, VDD = 3.3 V
100
80
60
40
20
0
CL
DEL
T
A
TIME DELA
Y
(ns)
OUTPUT
2.0
Figure 3. Derating Across Temperature and Voltage
+0.2
+0.1
0
0.1
0.2
T (
C)
@ VDD = 3.3 V
75
50
25
0
25
50
30 pF
DEL
T
A
TIME DELA
Y
(ns)
OUTPUT
+0.3
+0.2
+0.1
0
0.2
0.3
VDD (V)
@ T = 25
C
3.5
3.4
3.3
3.2
3.1
3.0
DEL
T
A
TIME DELA
Y
(ns)
+0.3
0.1
3.6
100
MCM6323A
6
MOTOROLA FAST SRAM
READ CYCLE 1
(See Note 7)
Q (DATA OUT)
A (ADDRESS)
DATA VALID
PREVIOUS DATA VALID
tAVAV
tAXQX
tAVQV
READ CYCLE 2
(See Note 8)
tEHQZ
DATA VALID
tGHQZ
tAVAV
tELQX
tELQV
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
tAVQV
tBLQX
tGLQV
G (OUTPUT ENABLE)
tBHQZ
tBLQV
LB, UB (BYTE ENABLE)
tGLQX
MCM6323A
7
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled, See Notes 1 and 2)
P
S
b l
MCM6323A10
MCM6323A12
MCM6323A15
U i
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
10
--
12
--
15
--
ns
3
Address Setup Time
tAVWL
0
--
0
--
0
--
ns
Address Valid to End of Write
tAVWH
8
--
9
--
10
--
ns
Write Pulse Width
tWLWH,
tWLEH
8
--
9
--
10
--
ns
Byte Pulse Width
tBLWH,
tBLEH
8
--
9
--
10
--
ns
Data Valid to End of Write
tDVWH
4
--
5
--
6
--
ns
Data Hold Time
tWHDX
0
--
0
--
0
--
ns
Write Low to Data HighZ
tWLQZ
0
4
0
5
0
6
ns
4, 5, 6
Write High to Output Active
tWHQX
3
--
3
--
3
--
ns
4, 5, 6
Write Recovery Time
tWHAX
0
--
0
--
0
--
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steadystate voltage.
5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
6. This parameter is sampled and not 100% tested.
WRITE CYCLE 1
(W Controlled)
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGHZ
HIGHZ
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
tBLWH
LB, UB (BYTE ENABLE)
tBLEH
MCM6323A
8
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled, See Notes 1 and 2)
P
S
b l
MCM6323A10
MCM6323A12
MCM6323A15
U i
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
10
--
12
--
15
--
ns
3
Address Setup Time
tAVEL
0
--
0
--
0
--
ns
Address Valid to End of Write
tAVEH
8
--
9
--
10
--
ns
Enable to End of Write
tELEH,
tELWH
8
--
9
--
10
--
ns
4, 5
Data Valid to End of Write
tDVEH
4
--
5
--
6
--
ns
Data Hold Time
tEHDX
0
--
0
--
0
--
ns
Write Recovery Time
tEHAX
0
--
0
--
0
--
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.
5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.
WRITE CYCLE 2
(E Controlled)
tEHDX
tDVEH
tEHAX
tELWH
tELEH
tAVEL
tAVEH
DATA VALID
tAVAV
HIGHZ
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
LB, UB (BYTE ENABLE)
MCM6323A
9
MOTOROLA FAST SRAM
WRITE CYCLE 3
(B Controlled, See Notes 1 and 2)
P
S
b l
MCM6323A10
MCM6323A12
MCM6323A15
U i
N
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
10
--
12
--
15
--
ns
3
Address Setup Time
tAVBL
0
--
0
--
0
--
ns
Address Valid to End of Write
tAVBH
8
--
9
--
10
--
ns
Write Pulse Width
tWLWH,
tWLEH
8
--
9
--
10
--
ns
Byte Pulse Width
tBLWH,
tBLEH,
tBLBH
8
--
9
--
10
--
ns
Data Valid to End of Write
tDVBH
5
--
6
--
7
--
ns
Data Hold Time
tBHDX
0
--
0
--
0
--
ns
Write Low to Data HighZ
tWLQZ
0
4
0
5
0
6
ns
4, 5, 6
Write High to Output Active
tWHQX
3
--
3
--
3
--
ns
4, 5, 6
Write Recovery Time
tBHAX
0
--
0
--
0
--
ns
NOTES:
1. A write occurs during the overlap of E low, W low, and LB and/or UB low.
2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles.
3. All write cycle timings are referenced from the last valid address to the first transitioning address.
4. Transition is measured 200 mV from steadystate voltage.
5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
6. This parameter is sampled and not 100% tested.
WRITE CYCLE 3
(B Controlled)
DATA VALID
tDVBH
tAVBL
tAVBH
tAVAV
tBHAX
tBLWH
tBHDX
tWLQZ
tWHQX
HIGHZ
HIGHZ
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tBLEH
tWLWH
LB, UB (BYTE ENABLE)
tWLEH
tBLBH
MCM6323A
10
MOTOROLA FAST SRAM
Motorola Memory Prefix
Part Number
Package (YJ = 400 mil SOJ, TS = 44Lead
TSOP Type II)
Full Commercial Part Numbers -- MCM6323AYJ10
MCM6323AYJ12
MCM6323AYJ15
MCM6323AYJ10R
MCM6323AYJ12R
MCM6323AYJ15R
MCM6323ATS10
MCM6323ATS12
MCM6323ATS15
MCM6323ATS10R
MCM6323ATS12R
MCM6323ATS15R
Full Industrial Part Numbers --
SCM6323AYJ10A
SCM6323AYJ12A
SCM6323AYJ15A
SCM6323AYJ10AR
SCM6323AYJ12AR
SCM6323AYJ15AR
SCM6323ATS10A
SCM6323ATS12A
SCM6323ATS15A
SCM6323ATS10AR SCM6323ATS12AR
SCM6323ATS15AR
Shipping Method (R = Tape and Reel,
Blank = Rails for SOJ, Blank = Trays for TSOP)
Speed (10 = 10 ns, 12 = 12 ns, 15 = 15 ns)
MCM 6323A
YJ
XX
X
ORDERING INFORMATION
(Order by Full Part Number)
Temperature (Blank = Commercial, A = Industrial)
X
MCM6323A
11
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
YJ PACKAGE
400 MIL SOJ
CASE 91901
23
22
44
1
R1
A
E
VIEW AA
44X R
22 ZONES 2X
42X
b1
44X
SEATING
PLANE
D
B
E1
A
L
0.007
C A B
C
e
M
0.007
C A B
b
44X
e /2
A3
C
0.004
A
A
M
0.007
C A B
B
0.015
A2
A1
E2
E2 /2
DIM
MIN
MAX
INCHES
A
0.128
0.148
A1
0.025
A2
0.082
A3
0.035
0.045
b
0.015
0.020
b1
0.026
0.032
D
1.120
1.130
E
0.435
0.445
E1
0.395
0.405
E2
0.370 BSC
e
0.050 BSC
R1
0.030
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 PER END. DIMENSION
E1 DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010
PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005. THE DAMBAR INTRUSION(S)
SHALL NOT REDUCE THE SHOULDER WIDTH TO
LESS THAN 0.001 BELOW b1 MIN.
MCM6323A
12
MOTOROLA FAST SRAM
TS PACKAGE
44LEAD
TSOP TYPE II
CASE 924A01
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.050
1.270
A1
0.002
0.006
0.051
0.152
A2
0.038
0.042
0.965
1.067
b
0.012
0.018
0.305
0.457
b1
0.012
0.016
0.305
0.406
c
0.005
0.008
0.127
0.203
c1
0.004
0.006
0.101
0.152
D1
0.721
0.729
18.313
18.517
e
0.0315 BSC
0.800 BSC
E
0.456
0.470
11.582
11.938
E1
0.396
0.404
10.058
10.262
L
0.016
0.023
0.406
0.584
R1
0.004 REF
0.100 REF
R2
0.004 REF
0.100 REF
q
0
5
0
5
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.006 (0.015) PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSIONS SHALL
NOT ALLOW THE b DIMENSION TO EXCEED 0.023
(0.58).
_
_
_
_
A
M
0
.
0
0
8
(
0
.
2
)
C
B
A
e
C
4
4
2
3
1
22
A
A A
E1
D1
42X
e
4X
44X
0.004 (0.1) C
SEATING
PLANE
22X
E
A2
VIEW A
A1
L
b
(R1)
q
R
(R2)
R
ROTATED 90 CLOCKWISE
BASE METAL
DETAIL A
40 PLACES
SECTION AA
_
c
b1
c1
/2
Z
M
0.008 (0.2)
T
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