MCM6343
1
MOTOROLA FAST SRAM
Product Preview
256K x 16 Bit 3.3 V Asynchronous
Fast Static RAM
The MCM6343 is a 4,194,304bit static random access memory organized as
262,144 words of 16 bits. Static design eliminates the need for external clocks
or timing strobes.
The MCM6343 is equipped with chip enable (E), write enable (W), and output
enable (G) pins, allowing for greater system flexibility and eliminating bus con-
tention problems. Separate byte enable controls (LB and UB) allow individual
bytes to be written and read. LB controls the lower bits DQ0 to DQ7, while UB
controls the upper bits DQ8 to DQ15.
The MCM6343 is available in a 400 mil, 44lead smalloutline SOJ package
and a 44lead TSOP Type II package.
Single 3.3 V
0.3 V Power Supply
Fast Access Time: 12/15 ns
Equal Address and Chip Enable Access Time
All Inputs and Outputs are TTL Compatible
Data Byte Control
Fully Static Operation
Power Operation: 250/240/230 mA Maximum, Active AC
Commercial and Standard Industrial Temperature Option: 40 to + 85
C
BLOCK DIAGRAM
OUTPUT
ENABLE
BUFFER
ADDRESS
BUFFERS
WRITE
ENABLE
BUFFER
BYTE
ENABLE
BUFFER
ROW
DECODER
COLUMN
DECODER
256K x 16
BIT
MEMORY
ARRAY
HIGH
BYTE
OUTPUT
BUFFER
8
HIGH
BYTE
WRITE
DRIVER
LOW
BYTE
OUTPUT
BUFFER
LOW
BYTE
WRITE
DRIVER
SENSE
AMPS
G
W
LB
8
8
8
8
8
8
8
9
A
CHIP
ENABLE
BUFFER
E
UB
9
HIGH BYTE OUTPUT ENABLE
LOW BYTE OUTPUT ENABLE
HIGH BYTE WRITE ENABLE
LOW BYTE WRITE ENABLE
16
18
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
Order this document
by MCM6343/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MCM6343
YJ PACKAGE
400 MIL SOJ
CASE 91901
PIN ASSIGNMENT
A0 A17
Address Input
. . . . . . . . . . . . . . . . .
E
Chip Enable
. . . . . . . . . . . . . . . . . . . . . . . . .
W
Write Enable
. . . . . . . . . . . . . . . . . . . . . . .
G
Output Enable
. . . . . . . . . . . . . . . . . . . . . .
UB
Upper Byte
. . . . . . . . . . . . . . . . . . . . . . . .
LB
Lower Byte
. . . . . . . . . . . . . . . . . . . . . . . . .
DQ0 DQ15
Data Input/Output
. . . . . . . . . .
VDD
+ 3.3 V Power Supply
. . . . . . . . . . . . . .
VSS
Ground
. . . . . . . . . . . . . . . . . . . . . . . . . .
NC
No Connection
. . . . . . . . . . . . . . . . . . . . .
PIN NAMES
5
4
3
2
1
10
9
8
7
6
11
36
37
38
39
40
41
42
35
43
44
34
E
A
A
A
A
DQ1
DQ0
A
VDD
DQ3
DQ2
UB
G
A
A
A
DQ12
DQ13
DQ14
VSS
DQ15
LB
25
26
27
28
29
30
31
24
32
33
23
12
13
14
15
16
17
18
19
20
21
22
DQ8
DQ9
DQ10
DQ11
VDD
A
A
A
A
A
NC
W
DQ6
DQ5
DQ4
VSS
A
A
DQ7
A
A
A
TS PACKAGE
TSOP TYPE II
CASE 924A02
REV 2
2/10/98
Motorola, Inc. 1998
MCM6343
2
MOTOROLA FAST SRAM
TRUTH TABLE
(X = Don't Care)
E
G
W
LB
UB
Mode
VDD Current
DQ0 DQ7
DQ8 DQ15
H
X
X
X
X
Not Selected
ISB1, ISB2
HighZ
HighZ
L
H
H
X
X
Output Disabled
IDDA
HighZ
HighZ
L
X
X
H
H
Output Disabled
IDDA
HighZ
HighZ
L
L
H
L
H
Low Byte Read
IDDA
Dout
HighZ
L
L
H
H
L
High Byte Read
IDDA
HighZ
Dout
L
L
H
L
L
Word Read
IDDA
Dout
Dout
L
X
L
L
H
Low Byte Write
IDDA
Din
HighZ
L
X
L
H
L
High Byte Write
IDDA
HighZ
Din
L
X
L
L
L
Word Write
IDDA
Din
Din
ABSOLUTE MAXIMUM RATINGS
(See Notes)
Rating
Symbol
Value
Unit
Supply Voltage
VDD
0.5 to + 4.6
V
Voltage on Any Pin
Vin
0.5 to VDD + 0.5
V
Output Current per Pin
Iout
20
mA
Package Power Dissipation
PD
TBD
W
Temperature Under Bias
Commercial
Industrial
Tbias
10 to + 85
45 to + 90
C
Operating Temperature
Commercial
Industrial
TA
0 to + 70
45 to + 85
C
Storage Temperature
Tstg
55 to + 150
C
NOTES:
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability will be dependent upon package characteristics and use
environment.
This device contains circuitry to protect the
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid ap-
plication of any voltage higher than maximum
rated voltages to these highimpedance circuits.
This CMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established. The circuit is in a test
socket or mounted on a printed circuit board and
transverse air flow of at least 500 linear feet per
minute is maintained.
MCM6343
3
MOTOROLA FAST SRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
0.3 V, TA = 0 to 70
C, Unless Otherwise Noted)
(TA = 40 to + 85
C for Industrial Temperature Offering)
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Typ
Max
Unit
Power Supply Voltage
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.2
--
VDD + 0.3
**
V
Input Low Voltage
VIL
0.5
*
--
0.8
V
* VIL (min) = 0.5 V dc; VIL (min) = 2.0 V ac (pulse width
20 ns) for I
20.0 mA.
** VIH (max) = VDD + 0.3 V dc; VIH (max) = VDD + 2.0 V ac (pulse width
20 ns) for I
20.0 mA.
DC CHARACTERISTICS
Parameter
Symbol
Min
Max
Unit
Input Leakage Current (All Inputs, Vin = 0 to VDD)
Ilkg(I)
--
1.0
A
Output Leakage Current (E = VIH, Vout = 0 to VDD)
Ilkg(O)
--
1.0
A
Output Low Voltage
(IOL = + 4.0 mA)
(IOL = + 100
A)
VOL
--
0.4
VSS + 0.2
V
Output High Voltage
(IOH = 4.0 mA)
(IOH = 100
A)
VOH
2.4
VDD 0.2
--
V
POWER SUPPLY CURRENTS
Parameter
Symbol
0 to 70
C
40 to
+ 85
C
Unit
AC Active Supply Current
MCM634312: tAVAV = 12 ns
(Iout = 0 mA, VCC = max)
MCM634315: tAVAV = 15 ns
ICC
240
230
240
mA
AC Standby Current (VCC = max, E = VIH, MCM634312:
tAVAV = 12 ns
No other restrictions on other inputs)
MCM634315: tAVAV = 15 ns
ISB1
50
45
55
50
mA
CMOS Standby Current (E
VCC 0.2 V, Vin
VSS + 0.2 V or
VCC 0.2 V)
(VCC = max, f = 0 MHz)
ISB2
5
5
mA
CAPACITANCE
(f = 1.0 MHz, dV = 3.0 V, TA = 25
C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Typ
Max
Unit
Address Input Capacitance
Cin
--
6
pF
Control Input Capacitance
Cin
--
6
pF
Input/Output Capacitance
CI/O
--
8
pF
MCM6343
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 V
0.3 V, TA = 0 to + 70
C, Unless Otherwise Noted)
(TA = 40 to + 85
C for Industrial Temperature Offering)
Logic Input Timing Measurement Reference Level
1.50 V
. . . . . . . .
Logic Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
2 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.50 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
See Figure 1
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ CYCLE TIMING
(See Notes 1, 2, and 3)
P
S
b l
MCM634312
MCM634315
U i
N
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
12
--
15
--
ns
4
Address Access Time
tAVQV
--
12
--
15
ns
Enable Access Time
tELQV
--
12
--
15
ns
5
Output Enable Access Time
tGLQV
--
6
--
7
ns
Output Hold from Address Change
tAXQX
3
--
3
--
ns
Enable Low to Output Active
tELQX
3
--
3
--
ns
6, 7, 8
Output Enable Low to Output Active
tGLQX
0
--
0
--
ns
6, 7, 8
Enable High to Output HighZ
tEHQZ
0
6
0
7
ns
6, 7, 8
Output Enable High to Output HighZ
tGHQZ
0
6
0
7
ns
6, 7, 8
Byte Enable Access Time
tBLQV
--
6
--
7
ns
Byte Enable Low to Output Active
tBLQX
0
--
0
--
ns
6, 7, 8
Byte High to Output HighZ
tBHQZ
0
6
0
7
ns
6, 7, 8
NOTES:
1. W is high for read cycle.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. Device is continuously selected (E
VIL, G
VIL).
4. All read cycle timings are referenced from the last valid address to the first transitioning address.
5. Addresses valid prior to or coincident with E going low.
6. At any given voltage and temperature, tEHQZ max
t
tELQX min, and tGHQZ max
t
tGLQX min, both for a given device and from device
to device.
7. This parameter is sampled and not 100% tested.
8. Transition is measured
200 mV from steadystate voltage.
The table of timing values shows either a minimum
or a maximum limit for each parameter. Input require-
ments are specified from the external system point of
view. Thus, address setup time is shown as a minimum
since the system must supply at least that much time.
On the other hand, responses from the memory are
specified from the device point of view. Thus, the ac-
cess time is shown as a maximum since the device
never provides data later than that time.
TIMING LIMITS
OUTPUT
Z0 = 50
RL = 50
VL = 1.5 V
Figure 1. AC Test Load
MCM6343
5
MOTOROLA FAST SRAM
Q (DATA OUT)
A (ADDRESS)
DATA VALID
PREVIOUS DATA VALID
tAVAV
tAXQX
tAVQV
READ CYCLE 1
(See Note 8)
tEHQZ
DATA VALID
tGHQZ
tAVAV
tELQX
tELQV
E (CHIP ENABLE)
Q (DATA OUT)
A (ADDRESS)
tAVQV
tBLQX
tGLQV
G (OUTPUT ENABLE)
tBHQZ
tBLQV
LB, UB (BYTE ENABLE)
tGLQX
READ CYCLE 2
(See Note 4)
MCM6343
6
MOTOROLA FAST SRAM
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3)
P
S
b l
MCM634312
MCM634315
U i
N
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
12
--
15
--
ns
4
Address Setup Time
tAVWL
0
--
0
--
ns
Address Valid to End of Write
tAVWH
10
--
12
--
ns
Address Valid to End of Write (G High)
tAVWH
9
--
10
--
ns
Write Pulse Width
tWLWH
tWLEH
10
--
12
--
ns
Write Pulse Width (G High)
tWLWH
tWLEH
9
--
10
--
ns
Data Valid to End of Write
tDVWH
6
--
7
--
ns
Data Hold Time
tWHDX
0
--
0
--
ns
Write Low to Data HighZ
tWLQZ
0
6
0
7
ns
5, 6, 7
Write High to Output Active
tWHQX
3
--
3
--
ns
5, 6, 7
Write Recovery Time
tWHAX
0
--
0
--
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a highimpedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
5. This parameter is sampled and not 100% tested.
6. Transition is measured
200 mV from steadystate voltage.
7. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device.
DATA VALID
tDVWH
tAVWL
tAVWH
tAVAV
tWHAX
tWLWH
tWHDX
tWLQZ
tWHQX
HIGHZ
HIGHZ
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tWLEH
LB, UB (BYTE ENABLE)
WRITE CYCLE 1
(W Controlled; See Notes 1, 2, and 3)
MCM6343
7
MOTOROLA FAST SRAM
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, and 3)
P
S
b l
MCM634312
MCM634315
U i
N
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
12
--
15
--
ns
4
Address Setup Time
tAVEL
0
--
0
--
ns
Address Valid to End of Write
tAVEH
10
--
12
--
ns
Address Valid to End of Write (G High)
tAVEH
9
--
10
--
ns
Enable to End of Write
tELEH,
tELWH
10
--
12
--
ns
5, 6
Enable to End of Write (G High)
tELEH,
tELWH
9
--
10
--
ns
5, 6
Data Valid to End of Write
tDVEH
6
--
7
--
ns
Data Hold Time
tEHDX
0
--
0
--
ns
Write Recovery Time
tEHAX
0
--
0
--
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a highimpedance state.
4. All write cycle timing is referenced from the last valid address to the first transitioning address.
5. If E goes low coincident with or after W goes low, the output will remain in a highimpedance condition.
6. If E goes high coincident with or before W goes high, the output will remain in a highimpedance condition.
tEHDX
tDVEH
tEHAX
tELWH
tELEH
tAVEL
tAVEH
DATA VALID
tAVAV
HIGHZ
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
LB, UB (BYTE ENABLE)
WRITE CYCLE 2
(E Controlled; See Notes 1, 2, and 3)
MCM6343
8
MOTOROLA FAST SRAM
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
P
S
b l
MCM634312
MCM634315
U i
N
Parameter
Symbol
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
12
--
15
--
ns
4
Address Setup Time
tAVBL
0
--
0
--
ns
Address Valid to End of Write
tAVBH
10
--
12
--
ns
Address Valid to End of Write (G High)
tAVBH
9
--
10
--
ns
Byte Pulse Width
tBLWH
tBLEH
10
--
12
--
ns
Byte Pulse Width (G High)
tBLWH
tBLEH
9
--
10
--
ns
Data Valid to End of Write
tDVBH
6
--
7
--
ns
Data Hold Time
tBHDX
0
--
0
--
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a highimpedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
DATA VALID
tDVBH
tAVBL
tAVBH
tAVAV
tBLWH
tBHDX
HIGHZ
HIGHZ
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tBLEH
LB, UB (BYTE ENABLE)
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
MCM6343
9
MOTOROLA FAST SRAM
Motorola Memory Prefix
Part Number
Package (YJ = 400 mil SOJ, TS = TSOP Type II)
Full Commercial Part Numbers -- MCM6343YJ12
MCM6343YJ12R
MCM6343TS12
MCM6343YJ15
MCM6343YJ15R
MCM6343TS15
Shipping Method (R = Tape and Reel, Blank = Rails)
Speed (12 = 12 ns, 15 = 15 ns)
XCM
6943
XX
XX
X
ORDERING INFORMATION
(Order by Full Part Number)
Full Industrial Part Numbers -- SCM6343YJ12A
SCM6343YJ12AR
SCM6343TS12A*
SCM6343YJ15A
SCM6343YJ15AR
SCM6343TS15A*
* Not available in Tape and Reel.
PACKAGE DIMENSIONS
YJ PACKAGE
44LEAD
400 MIL SOJ
CASE 91901
23
22
44
1
R1
A
E
VIEW AA
44X R
22 ZONES 2X
42X
b1
44X
SEATING
PLANE
D
B
E1
A
L
0.007
C A B
C
e
M
0.007
C A B
b
44X
e /2
A3
C
0.004
A
A
M
0.007
C A B
B
0.015
A2
A1
E2
E2 /2
DIM
MIN
MAX
INCHES
A
0.128
0.148
A1
0.025
A2
0.082
A3
0.035
0.045
b
0.015
0.020
b1
0.026
0.032
D
1.120
1.130
E
0.435
0.445
E1
0.395
0.405
E2
0.370 BSC
e
0.050 BSC
R1
0.030
0.040
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION D DOES NOT INCLUDE MOLD FLASH,
TIE BAR BURRS AND GATE BURRS. MOLD
FLASH, TIE BAR BURRS AND GATE BURRS
SHALL NOT EXCEED 0.006 PER END. DIMENSION
E1 DOES NOT INCLUDE INTERLEAD FLASH.
INTERLEAD FLASH SHALL NOT EXCEED 0.010
PER SIDE.
4. THE PACKAGE TOP MAY BE SMALLER THAN THE
PACKAGE BOTTOM. DIMENSIONS D AND E1 AND,
HENCE, DATUMS A AND B, ARE DETERMINED AT
THE OUTERMOST EXTREMES OF THE PLASTIC
BODY EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD FLASH,
BUT INCLUDING ANY MISMATCH BETWEEN THE
TOP AND BOTTOM OF THE PLASTIC BODY.
5. DIMENSION b1 DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE
SHOULDER WIDTH TO EXCEED b1 MAX BY
MORE THAN 0.005. THE DAMBAR INTRUSION(S)
SHALL NOT REDUCE THE SHOULDER WIDTH TO
LESS THAN 0.001 BELOW b1 MIN.
MCM6343
10
MOTOROLA FAST SRAM
TS PACKAGE
44LEAD
TSOP TYPE II
CASE 924A02
NOTES:
1. DIMENSIONINS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS IN MILLIMETER.
3. DIMENSION D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.15 PER SIDE.
4. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSIONS. DAMBAR PROTRUSION SHALL
NOT CAUSE THE LEAD WIDTH TO EXCEED 0.58.
B
M
0.2
C
B
A
e
C
44
23
1
22
A2
A A
E1
D
42X
e
4X
44X
0.004 (0.1) C
SEATING
PLANE
22X
E
A
VIEW A
A1
L
b
q
ROTATED 90 CLOCKWISE
VIEW A
40 PLACES
SECTION AA
_
c
/2
B
M
0.2
C
DIM
MIN
MAX
MILLIMETERS
A
1.20
A1
0.05
0.15
A2
0.95
1.05
b
0.30
0.45
c
0.12
0.21
D
18.28
18.54
e
0.80 BSC
E
11.56
11.96
E1
10.03
10.29
L
0.40
0.60
q
0
5
_
_
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals"
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JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141,
P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447
4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
Mfax
TM
: RMFAX0@email.sps.mot.com TOUCHTONE 1-602-244-6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
Motorola Fax Back System
US & Canada ONLY 1-800-774-1848
51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
http://sps.motorola.com /mfax /
HOME PAGE : http://motorola.com /sps /
CUSTOMER FOCUS CENTER: 1-800-521-6274
MCM6343/D
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