1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
Medium Power Surface Mount Products
TMOS Dual P-Channel
Field Effect Transistors
MiniMOS
TM
devices are an advanced series of power MOSFETs
which utilize Motorola's TMOS process. These miniature surface
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
avalanche and commutation modes and the draintosource diode
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dcdc
converters, and power management in portable and battery
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive -- Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package -- Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
IDSS Specified at Elevated Temperatures
Avalanche Energy Specified
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS
(TJ = 25
C unless otherwise noted)(1)
Rating
Symbol
Value
Unit
DraintoSource Voltage
VDSS
25
Vdc
GatetoSource Voltage -- Continuous
VGS
20
Vdc
Drain Current -- Continuous @ TA = 25
C
Drain Current
-- Continuous @ TA = 100
C
Drain Current
-- Single Pulse (tp
10
s)
ID
ID
IDM
2.5
1.7
13
Adc
Apk
Total Power Dissipation @ TA = 25
C (2)
Derate above 25
C
PD
2.0
16
W
mW/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to 150
C
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25
)
EAS
245
mJ
Thermal Resistance, Junction to Ambient (2)
R
JA
62.5
C/W
Maximum Lead Temperature for Soldering Purposes, 0.0625
from case for 10 seconds
TL
260
C
DEVICE MARKING
F2P02
(1) Negative sign for PChannel device omitted for clarity.
(2) Mounted on 2" square FR4 board (1" sq. 2 oz. Cu 0.06" thick single sided) with one die operating, 10 sec. max.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF2P02ER2
13
12 mm embossed tape
2500
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
Designer's, EFET and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MMDF2P02E/D
Motorola, Inc. 1996
D
S
G
MMDF2P02E
DUAL TMOS MOSFET
2.5 AMPERES
25 VOLTS
RDS(on) = 0.250 OHM
CASE 75105, Style 11
SO8
Source1
1
2
3
4
8
7
6
5
Top View
Gate1
Source2
Gate2
Drain1
Drain1
Drain2
Drain2
REV 5
MMDF2P02E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TA = 25
C unless otherwise noted)(1)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250
Adc)
Temperature Coefficient (Positive)
V(BR)DSS
25
--
--
2.2
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125
C)
IDSS
--
--
--
--
1.0
10
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
100
nAdc
ON CHARACTERISTICS(2)
Gate Threshold Voltage
(VDS = VGS, ID = 250
Adc)
Temperature Coefficient (Negative)
VGS(th)
1.0
2.0
3.8
3.0
Vdc
Static DraintoSource OnResistance
(VGS = 10 Vdc, ID = 2.0 Adc)
(VGS = 4.5 Vdc, ID = 1.0 Adc)
RDS(on)
--
--
0.19
0.3
0.25
0.4
Ohm
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc)
gFS
1.0
2.8
--
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
--
340
475
pF
Output Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
--
220
300
Transfer Capacitance
f = 1.0 MHz)
Crss
--
75
150
SWITCHING CHARACTERISTICS(3)
TurnOn Delay Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 5.0 Vdc,
RG = 6.0
)
td(on)
--
20
40
ns
Rise Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 5.0 Vdc,
RG = 6.0
)
tr
--
40
80
TurnOff Delay Time
VGS = 5.0 Vdc,
RG = 6.0
)
td(off)
--
53
106
Fall Time
G = 6.0
)
tf
--
41
82
TurnOn Delay Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 6.0
)
td(on)
--
13
26
Rise Time
(VDD = 10 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc,
RG = 6.0
)
tr
--
29
58
TurnOff Delay Time
VGS = 10 Vdc,
RG = 6.0
)
td(off)
--
30
60
Fall Time
G = 6.0
)
tf
--
28
56
Gate Charge
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
QT
--
10
15
nC
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
Q1
--
1.0
--
(VDS = 16 Vdc, ID = 2.0 Adc,
VGS = 10 Vdc)
Q2
--
3.5
--
Q3
--
3.0
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage(2)
(IS = 2.0 Adc, VGS = 0 Vdc)
VSD
--
1.5
2.0
Vdc
Reverse Recovery Time
See Figure 11
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
trr
--
32
64
ns
See Figure 11
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
ta
--
19
--
(IS = 2.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
tb
--
12
--
Reverse Recovery Storage Charge
QRR
--
0.035
--
C
(1) Negative sign for PChannel device omitted for clarity.
(2) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(3) Switching characteristics are independent of operating junction temperature.
MMDF2P02E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
Figure 1. OnRegion Characteristics
Figure 2. Transfer Characteristics
Figure 3. OnResistance versus
GatetoSource Voltage
Figure 4. OnResistance versus Drain Current
and Gate Voltage
Figure 5. OnResistance Variation with
Temperature
Figure 6. DraintoSource Leakage Current
versus Voltage
3.5 V
10 V
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (NORMALIZED)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
0
0
0.4
0.8
1.2
1.6
2
0
2
3
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
I D
, DRAIN CURRENT
(AMPS)
I D
, DRAIN CURRENT
(AMPS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
3
4
5
10
0.3
0.4
0.6
0.1
VGS, GATETOSOURCE VOLTAGE (VOLTS)
ID, DRAIN CURRENT (AMPS)
1
TJ, JUNCTION TEMPERATURE (
C)
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
0.2
6
8
50
0
50
100
150
4
1
0
3.3 V
TJ = 25
C
VGS = 10
2
3
4
1
2.5
3
3.5
4
4.5
0.1
0.4
0.5
0.6
0.3
0.2
0
0.5
1
1.5
2
0
I DSS
, LEAKAGE (nA)
100
10
0
4
8
12
20
0.5
1.0
1.5
2.0
VGS = 10 V
ID = 2 A
125
75
25
25
VDS
10 V
25
C
100
C
TJ = 55
C
VGS = 4.5
TJ = 25
C
9
7
0.5
ID = 1 A
TJ = 25
C
16
3.7 V
3.9 V
4.1 V
4.3 V
4.5 V
5 V
4.7 V
7 V
VGS = 0 V
TJ = 125
C
100
C
MMDF2P02E
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
Figure 7. Capacitance Variation
C, CAP
ACIT
ANCE (pF)
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
V
GS
, GA
TET
OSOURCE VOL
T
AGE (VOL
TS)
Qg, TOTAL GATE CHARGE (nC)
t,
TIME (ns)
RG, GATE RESISTANCE (OHMS)
100
1
100
10
10
I S
, SOURCE CURRENT
(AMPS)
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
0.4
0.8
1.2
2
1.6
0.6
0.8
1.2
1.4
1.6
1
0
TJ = 25
C
VGS = 0 V
0
2
4
6
8
ID = 2 A
TJ = 25
C
VGS
6
3
0
12
9
16
12
8
4
0
VDS
QT
Q1
Q2
Q3
10
12
10
0
10
15
25
VGS
VDS
TJ = 25
C
VDS = 0 V
VGS = 0 V
1000
800
600
400
200
0
20
Ciss
Coss
Crss
5
5
Ciss
Crss
30
V
DS
, DRAINT
OSOURCE VOL
T
AGE (VOL
TS)
VDD = 10 V
ID = 2 A
VGS = 10 V
TJ = 25
C
tf
td(off)
td(on)
tr
Figure 8. GatetoSource and
DraintoSource Voltage versus Total Charge
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage
versus Current
MMDF2P02E
5
Motorola TMOS Power MOSFET Transistor Device Data
I S
, SOURCE CURRENT
t, TIME
Figure 11. Reverse Recovery Time (trr)
di/dt = 300 A/
s
Standard Cell Density
High Cell Density
tb
trr
ta
trr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25
C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal Resistance Gen-
eral Data and Its Use."
Switching between the offstate and the onstate may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10
s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R
JC).
A power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction tem-
perature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
Figure 12. Maximum Rated Forward Biased
Safe Operating Area
Figure 13. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
1
10
I D
, DRAIN CURRENT
(AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
VGS = 20 V
SINGLE PULSE
TC = 25
C
10
0.1
dc
10 ms
1
100
100
Mounted on 2" sq. FR4 board (1" sq. 2 oz. Cu 0.06"
thick single sided) with one die operating, 10s max.
100
s
10
s
TJ, STARTING JUNCTION TEMPERATURE (
C)
E
AS
, SINGLE PULSE DRAIN-T
O-SOURCE
A
V
ALANCHE ENERGY
(mJ)
0
25
50
75
100
125
120
I pk = 7 A
200
150
280
80
40
160
240
PDF 
ZIP