1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
Medium Power Surface Mount Products
Complementary TMOS
Field Effect Transistors
MiniMOS devices are an advanced series of power MOSFETs
which utilize Motorola's High Cell Density HDTMOS process.
These miniature surface mount MOSFETs feature ultra low RDS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.
Ultra Low RDS(on) Provides Higher Efficiency and
Extends Battery Life
Logic Level Gate Drive -- Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package --
Saves Board Space
Ideal for Synchronous Rectification
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS
(TJ = 25
C unless otherwise noted)
Rating
Symbol
Polarity
Value
Unit
DraintoSource Voltage
VDSS
--
30
Vdc
GatetoSource Voltage
VGS
--
20
Vdc
Drain Current -- Continuous
ID
NChannel
5.0
Adc
PChannel
3.0
Drain Current -- Pulsed
IDM
NChannel
25
Apk
PChannel
15
Operating and Storage Temperature Range
TJ, Tstg
--
55 to +150
C
Total Power Dissipation @ TA = 25
C (1)
PD
2.0
Watts
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 30 Vdc, VGS = 5.0 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25
W
)
EAS
NChannel
325
mJ
(VDD = 30 Vdc, VGS = 5.0 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25
W
)
PChannel
450
Thermal Resistance -- JunctiontoAmbient (1)
R
JA
62.5
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
from Case for 10 sec.
TL
260
C
DEVICE MARKING
D3C03HD
(1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint.
ORDERING INFORMATION
Device
Reel Size
Tape Width
Quantity
MMDF3C03HDR2
13
12 mm embossed tape
2500
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
Designer's, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MMDF3C03HD/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
NSource
1
2
3
4
8
7
6
5
Top View
NGate
PSource
PGate
Drain
Drain
Drain
Drain
PG
CASE 75105, Style 11
SO8
MMDF3C03HD
COMPLEMENTARY
DUAL TMOS POWER FET
30 VOLTS
NCH RDS(on) = 0.050
W
PCH RDS(on) = 0.100
W
Motorola Preferred Device
TM
NS
D
PS
NG
REV 1
MMDF3C03HD
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TA = 25
C unless otherwise noted)
Characteristic
Symbol
Polarity
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(VGS = 0 Vdc, ID = 0.25
mAdc)
V(BR)DSS
--
30
--
--
Vdc
Zero Gate Voltage Drain Current
(VDS = 30 Vdc, VGS = 0 Vdc)
IDSS
(N)
(P)
--
--
--
--
1.0
1.0
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
--
100
nAdc
ON CHARACTERISTICS(1)
Gate Threshold Voltage (VDS = VGS, ID = 250
Adc)
Threshold Temperature Coefficient (Negative)
VGS(th)
--
--
1.0
--
--
--
--
--
Vdc
mV/
C
DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.5 Adc)
(VGS = 10 Vdc, ID = 3.5 Adc)
RDS(on)1
(N)
(P)
--
--
0.037
0.075
0.05
0.10
Ohms
Static DraintoSource OnResistance
(VGS = 4.5 Vdc, ID = 2.5 Adc)
(VGS = 4.5 Vdc, ID = 2.0 Adc)
RDS(on)2
(N)
(P)
--
--
0.55
0.12
0.08
0.16
Ohms
Forward Transconductance
(VDS = 15 Vdc, ID = 3.5 Adc)
gFS
(N)
(P)
--
--
9.0
6.0
--
--
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
24 Vdc
Ciss
(N)
(P)
--
--
430
425
600
600
pF
Output Capacitance
(VDS = 24 Vdc,
VGS = 0 Vdc,
f = 1.0 MHz)
Coss
(N)
(P)
--
--
217
209
300
300
Transfer Capacitance
f = 1.0 MHz)
Crss
(N)
(P)
--
--
67.5
57.2
135
80
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
(V
15 Vd
td(on)
(N)
(P)
--
--
8.2
11.7
16.4
23.4
ns
Rise Time
(VDD = 15 Vdc,
ID = 1.0 Adc,
tr
(N)
(P)
--
--
8.48
15.8
16.9
31.6
TurnOff Delay Time
D
,
VGS = 10 Vdc,
RG = 6.0
)
td(off)
(N)
(P)
--
--
89.6
167.3
179
334.6
Fall Time
tf
(N)
(P)
--
--
61.1
102.6
122
205.2
Total Gate Charge
(See Figure 8)
(V
10 Vd
QT
(N)
(P)
--
--
15.7
14.8
31.4
29.6
nC
(VDS = 10 Vdc,
ID = 3 5 Adc
Q1
(N)
(P)
--
--
2.0
1.7
--
--
ID = 3.5 Adc,
VGS = 10 Vdc)
Q2
(N)
(P)
--
--
4.6
4.7
--
--
Q3
(N)
(P)
--
--
3.9
3.4
--
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage(2)
(IS = 1.7 Adc, VGS = 0 Vdc)
(IS = 1.7 Adc, VGS = 0 Vdc)
VSD
(N)
(P)
--
--
0.77
0.90
1.2
1.2
Vdc
Reverse Recovery Time
(N)
(ID = 3.5 Adc,
trr
(N)
(P)
--
--
54.5
77.4
--
--
ns
( D
,
VGS = 0 Vdc
dIS/dt = 100 A/
s)
ta
(N)
(P)
--
--
14.8
19.9
--
--
(P)
(ID = 3.5 Adc,
tb
(N)
(P)
--
--
39.7
57.5
--
--
Reverse Recovery Stored Charge
( D
,
VGS = 0 Vdc
dIS/dt = 100 A/
s)
QRR
(N)
(P)
--
--
0.048
0.088
--
--
C
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperature.
MMDF3C03HD
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
PChannel
Figure 1. OnRegion Characteristics
Figure 2. Transfer Characteristics
Figure 1. OnRegion Characteristics
Figure 2. Transfer Characteristics
Figure 3. OnResistance versus
GateToSource Voltage
Figure 3. OnResistance versus
GateToSource Voltage
2.9 V
1.2
2.0
0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
6.0
4.0
5.0
3.0
I D
, DRAIN CURRENT
(AMPS)
2.0
1.0
0
0.6
0.2
0.4
0.8
1.0
1.4
1.6
1.8
TJ = 25
C
2.7 V
3.1 V
3.3 V
3.5 V
3.7 V
3.9 V
VGS = 10 V
4.1 V
4.5 V
6.0 V
4.3 V
VGS, GATETOSOURCE VOLTAGE (VOLTS)
4.5
5.0
1.5
4.0
2.0
1.0
0
I
2.0
2.5
3.0
3.5
4.0
3.0
5.0
6.0
, DRAIN CURRENT
(AMPS)
D
VDS
10 V
TJ = 55
C
100
C
25
C
8.0
10
2.0
VGS, GATETOSOURCE VOLTAGE (VOLTS)
0.8
0.4
0.3
0.2
0.1
0
9.0
R
3.0
4.0
5.0
6.0
7.0
, DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
DS(on)
0.5
TJ = 25
C
ID = 3 A
0.6
0.7
1.2
2.0
0
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
12
8.0
10
6.0
I D
, DRAIN CURRENT
(AMPS)
4.0
2.0
0
0.6
0.2
0.4
0.8
1.0
1.4
1.6
1.8
TJ = 25
C
2.7 V
2.9 V
3.1 V
3.3 V
3.5 V
VGS = 2.5 V
10 V
6.0 V
4.5 V
4.3 V
4.1 V
3.7 V
3.9 V
VGS, GATETOSOURCE VOLTAGE (VOLTS)
4.5
5.0
1.5
8.0
4.0
2.0
0
I
2.0
2.5
3.0
3.5
4.0
6.0
10
12
, DRAIN CURRENT
(AMPS)
D
VDS
10 V
TJ = 55
C
100
C
25
C
8.0
10
2.0
VGS, GATETOSOURCE VOLTAGE (VOLTS)
0.30
0.20
0.15
0.10
0.05
0
9.0
R
3.0
4.0
5.0
6.0
7.0
, DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
DS(on)
0.25
TJ = 25
C
ID = 6 A
MMDF3C03HD
4
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
NChannel
PChannel
Figure 4. OnResistance versus Drain Current
and Gate Voltage
Figure 5. OnResistance Variation with
Temperature
Figure 6. DrainToSource Leakage
Current versus Voltage
Figure 4. OnResistance versus Drain Current
and Gate Voltage
Figure 5. OnResistance Variation with
Temperature
Figure 6. DrainToSource Leakage
Current versus Voltage
ID, DRAIN CURRENT (AMPS)
1.5
1.0
0.18
0.12
0.10
0.08
0.06
0.04
2.0
4.0
5.5
3.0
4.5
5.0
2.5
R
,
DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
DS(on)
TJ = 25
C
VGS = 4.5 V
10 V
3.5
0.16
0.14
25
25
50
TJ, JUNCTION TEMPERATURE (
C)
1.2
0.8
0.6
0.4
0.2
0
0
, DRAINT
OSOURCE
RESIST
ANCE
(NORMALIZED)
R
DS(on)
50
100
75
1.0
125
150
1.6
1.4
VGS = 10 V
ID = 1.5 A
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
5.0
30
0
100
1.0
15
10
20
25
10
I DSS
, LEAKAGE (nA)
VGS = 0 V
TJ = 125
C
100
C
ID, DRAIN CURRENT (AMPS)
2.0
1.0
0.050
0.045
0.040
0.035
0.030
0.025
3.0
4.0
5.0
6.0
7.0
8.0
9.0
R
,
DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
DS(on)
TJ = 25
C
VGS = 4.5 V
10 V
25
25
50
TJ, JUNCTION TEMPERATURE (
C)
1.2
0.8
0.6
0.4
0.2
0
0
, DRAINT
OSOURCE
RESIST
ANCE
(NORMALIZED)
R
DS(on)
50
100
75
1.0
125
150
1.6
1.4
1.8
VGS = 10 V
ID = 3 A
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
5.0
30
0
1000
100
1.0
0.1
15
10
20
25
10
I DSS
, LEAKAGE (nA)
VGS = 0 V
TJ = 125
C
100
C
25
C
MMDF3C03HD
5
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
NChannel
PChannel
Figure 7. Capacitance Variation
Figure 7. Capacitance Variation
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
20
30
10
800
400
200
0
5.0
0
5.0
10
15
600
1000
C, CAP
ACIT
ANCE
(pF)
25
VGS
VDS
TJ = 25
C
Ciss
Coss
Crss
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
20
30
10
800
400
200
0
5.0
0
5.0
10
15
600
1000
1200
C, CAP
ACIT
ANCE
(pF)
25
VGS
VDS
TJ = 25
C
Ciss
Coss
Crss
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