1
Motorola TMOS Power MOSFET Transistor Device Data
Advance Information
Medium Power Surface Mount Products
TMOS Dual N-Channel with
Monolithic Zener ESD Protected Gate
EZFETs
TM
are an advanced series of power MOSFETs which
utilize Motorola's High Cell Density TMOS process and contain
monolithic backtoback zener diodes. These zener diodes
provide protection against ESD and unexpected transients. These
miniature surface mount MOSFETs feature ultra low RDS(on) and
true logic level performance. They are capable of withstanding high
energy in the avalanche and commutation modes and the
draintosource diode has a very low reverse recovery time.
EZFET devices are designed for use in low voltage, high speed
switching applications where power efficiency is important. Typical
applications are dcdc converters, and power management in
portable and battery powered products such as computers,
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.
Zener Protected Gates Provide Electrostatic Discharge Protection
Designed to Withstand 200 V Machine Model and 2000 V Human Body Model
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive -- Can Be Driven by Logic ICs
Miniature SO8 Surface Mount Package -- Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
IDSS Specified at Elevated Temperature
Mounting Information for SO8 Package Provided
MAXIMUM RATINGS
(TJ = 25
C unless otherwise noted)
Parameter
Symbol
Max
Unit
DraintoSource Voltage
VDSS
20
Vdc
DraintoGate Voltage (RGS = 1.0 M
)
VDGR
20
Vdc
GatetoSource Voltage -- Continuous
VGS
12
Vdc
Drain Current -- Continuous @ TA = 25
C (1)
Drain Current
-- Continuous @ TA = 70
C (1)
Drain Current
-- Pulsed Drain Current (3)
ID
ID
IDM
7.0
4.6
35
Adc
Total Power Dissipation @ TA = 25
C (1)
Linear Derating Factor @ TA = 25
C (1)
PD
2.0
16
Watts
mW/
C
Total Power Dissipation @ TA = 25
C (2)
Linear Derating Factor @ TA = 25
C (2)
PD
1.39
11.11
Watts
mW/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to 150
C
THERMAL RESISTANCE
Parameter
Symbol
Typ
Max
Unit
JunctiontoAmbient (1)
JunctiontoAmbient (2)
R
q
JA
--
--
62.5
90
C/W
(1) When mounted on 1" square FR4 or G10 board (VGS = 10 V, @ 10 seconds).
(2) When mounted on minimum recommended FR4 or G10 board (VGS = 10 V, @ Steady State).
(3) Repetitive rating; pulse width limited by maximum junction temperature.
DEVICE MARKING
ORDERING INFORMATION
D7N02Z
Device
Reel Size
Tape Width
Quantity
D7N02Z
MMDF7N02ZR2
13
12 mm embossed tape
2500 units
This document contains information on a new product. Specifications and information herein are subject to change without notice.
HDTMOS is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MMDF7N02Z/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
Source1
1
2
3
4
8
7
6
5
Top View
Gate1
Source2
Gate2
Drain1
Drain1
Drain2
Drain2
D
S
G
CASE 75105, Style 11
SO8
MMDF7N02Z
DUAL TMOS
POWER MOSFET
7.0 AMPERES
20 VOLTS
RDS(on) = 27 m
W
Motorola Preferred Device
TM
MMDF7N02Z
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TC = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DraintoSource Breakdown Voltage
(Cpk
2.0) (1) (3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
20
--
--
15
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 20 Vdc, VGS = 0 Vdc)
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125
C)
IDSS
--
--
--
--
1.0
10
Adc
GateBody Leakage Current (VGS =
12 Vdc, VDS = 0 Vdc)
IGSS
--
--
3.0
Adc
ON CHARACTERISTICS(1)
Gate Threshold Voltage
(Cpk
2.0) (1) (3)
(VDS = VGS, ID = 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
VGS(th)
0.5
--
0.7
2.5
1.0
--
Vdc
mV/
C
Static DraintoSource OnResistance
(Cpk
2.0) (1) (3)
(VGS = 4.5 Vdc, ID = 7.0 Adc)
(VGS = 2.5 Vdc, ID = 3.5 Adc)
RDS(on)
--
--
23
30
27
35
m
Forward Transconductance (VDS = 10 Vdc, ID = 6.0 Adc) (1)
gFS
5.0
11
--
Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
16 Vdc V
0 Vdc
Ciss
--
450
630
pF
Output Capacitance
(VDS = 16 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
--
350
490
Transfer Capacitance
f = 1.0 MHz)
Crss
--
110
155
SWITCHING CHARACTERISTICS(2)
TurnOn Delay Time
(V
10 Vd
I
1 0 Ad
td(on)
--
31
62
ns
Rise Time
(VDD = 10 Vdc, ID = 1.0 Adc,
VGS = 4 5 Vdc
tr
--
230
460
TurnOff Delay Time
VGS = 4.5 Vdc,
RG = 6.0
) (1)
td(off)
--
725
1450
Fall Time
G
)
tf
--
780
1560
Gate Charge
See Figure 8
(V
12 Vd
I
5 0 Ad
QT
--
17
24
nC
See Figure 8
(VDS = 12 Vdc, ID = 5.0 Adc,
(1)
Q1
--
1.4
--
( DS
, D
,
VGS = 4.5 Vdc) (1)
Q2
--
6.7
--
Q3
--
6.5
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage
(IS = 7.0 Adc, VGS = 0 Vdc) (1)
(IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125
C)
VSD
--
--
0.90
0.84
1.1
--
Vdc
Reverse Recovery Time
(I
7 0 Ad
V
0 Vd
trr
--
780
--
ns
(IS = 7.0 Adc, VGS = 0 Vdc,
(1)
ta
--
190
--
( S
,
GS
,
dIS/dt = 100 A/
s) (1)
tb
--
590
--
Reverse Recovery Stored Charge
QRR
--
5.7
--
C
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperatures.
(3) Reflects typical values.
Cpk =
Max limit Typ
3 x SIGMA
MMDF7N02Z
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Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAINT
OSOURCE
RESIST
ANCE
(NORMALIZED)
R
DS(on)
, DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
0
6.0
12
15
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
I D
, DRAIN CURRENT
(AMPS)
0
0.5
1.0
0
6.0
12
15
I D
, DRAIN CURRENT
(AMPS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
0
2.0
4.0
10
0.01
0.04
0.06
0
2.0
4.0
6.0
8.0
12
0.05
0.04
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 3. OnResistance versus
Drain Current
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
1.5
2.0
0
4.0
20
1.0
100
10,000
TJ, JUNCTION TEMPERATURE (
C)
Figure 5. OnResistance Variation with
Temperature
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
I DSS
, LEAKAGE (nA)
VDS
10 V
TJ = 100
C
25
C
55
C
TJ = 25
C
VGS = 0 V
ID = 7.0 A
TJ = 25
C
VGS = 2.7 V
VGS = 4.5 V
ID = 3.5 A
1.5
2.0
2.5
6.0
8.0
10
4.5 V
50
25
0
25
50
75
100
125
150
TJ = 125
C
1.0
10
8.0
25
C
100
C
R
DS(on)
, DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
0
0.5
1.0
1.5
2.0
3.0
10 V
1.9 V
VGS = 1.7 V
2.3 V
4.5 V
TJ = 25
C
9.0
3.0
9.0
0.03
0.02
0.05
0.01
0.02
0.03
0
0.5
0
0.1
12
2.1 V
1000
16
MMDF7N02Z
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE
(pF)
1000
3000
Figure 7. Capacitance Variation
20
10
0
10
TJ = 25
C
Ciss
Coss
Crss
500
0
1500
2000
2500
Ciss
Crss
Coss
VDS = 0 V VGS = 0 V
5.0
5.0
15
MMDF7N02Z
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Motorola TMOS Power MOSFET Transistor Device Data
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
RG, GATE RESISTANCE (OHMS)
1.0
10
100
100
10
t, TIME
(ns)
VDD = 25 V
ID = 1.0 A
TJ = 25
C
tr
tf
td(off)
td(on)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
15
V
GS
, GA
TET
OSOURCE
VOL
T
AGE
(VOL
TS)
6.0
3.0
12
0
0
2.0
1.0
0
QG, TOTAL GATE CHARGE (nC)
V
DS
, DRAINT
OSOURCE
VOL
T
AGE
(VOL
TS)
5.0
3.0
5.0
10
TJ = 25
C
15
VDS
VGS
QT
Q2
Q3
Q1
20
1000
9.0
4.0
DRAINTOSOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier de-
vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 15. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high
di/dts. The diode's negative di/dt during ta is directly con-
trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac-
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.
Compared to Motorola standard cell density low voltage
MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re-
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.
0.4
0.5
0.6
0
2.0
4.0
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
I S
, SOURCE CURRENT
(AMPS)
3.0
0.7
1.0
5.0
7.0
TJ = 25
C
0.8
6.0
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