Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

TMOS E-FET

High Energy Power FET

D2PAK for Surface Mount

NChannel EnhancementMode Silicon Gate

The D2PAK package has the capability of housing a larger die

than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
TMOS EFET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient
design also offers a draintosource diode with a fast recovery
time. Designed for low voltage, high speed switching applications in
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
speed and commutating safe operating areas are critical and offer
additional safety margin against unexpected voltage transients.

Avalanche Energy Specified

SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode

Diode is Characterized for Use in Bridge Circuits

IDSS and VDS(on) Specified at Elevated Temperature

Short Heatsink Tab Manufactured -- Not Sheared

Specially Designed Leadframe for Maximum Power Dissipation

Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

200

Vdc

DrainGate Voltage (RGS = 1.0 M

)

VDGR

200

Vdc

GateSource Voltage -- Continuous

GateSource Voltage

-- NonRepetitive (tp

10 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous

Drain Current

-- Continuous @ 100

Drain Current

-- Single Pulse (tp

ID
ID

IDM

20
12
60

Adc

Apk

Total Power Dissipation

Derate above 25

Total Power Dissipation @ TA = 25

C, when mounted with the minimum recommended pad size

125

1.0
2.5

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 20 Apk, L = 3.0 mH, RG = 25

)

EAS

600

Thermal Resistance -- Junction to Case

Thermal Resistance

-- Junction to Ambient

Thermal Resistance

-- Junction to Ambient, when mounted with the minimum recommended pad size

1.0

62.5

C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

from case for 10 seconds

260

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 2

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MTB20N20E

TMOS POWER FET

20 AMPERES

200 VOLTS

RDS(on) = 0.16 OHM

Motorola Preferred Device

CASE 418B02, Style 2

D2PAK

Motorola, Inc. 1995

MTB20N20E

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DrainSource Breakdown Voltage

(VGS = 0 Vdc, ID = 250

Adc)

Temperature Coefficient (Positive)

V(BR)DSS

200

263

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 200 Vdc, VGS = 0 Vdc)
(VDS = 200 Vdc, VGS = 0 Vdc, TJ = 125

IDSS

--
--

100

Adc

GateBody Leakage Current (VGS =

20 Vdc, VDS = 0)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250

Adc)

Temperature Coefficient (Negative)

VGS(th)

2.0

7.0

4.0

Vdc

mV/

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 10 Adc)

RDS(on)

0.12

0.16

Ohm

DrainSource OnVoltage (VGS = 10 Vdc)

(ID = 20 Adc)
(ID = 10 Adc, TJ = 125

VDS(on)

--
--

3.84
3.36

Vdc

Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc)

gFS

8.0

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Ciss

1880

2700

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

378

535

Reverse Transfer Capacitance

f = 1.0 MHz)

Crss

100

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

(VDD = 100 Vdc, ID = 20 Adc,

VGS = 10 Vdc,

RG = 9.1

)

td(on)

Rise Time

(VDD = 100 Vdc, ID = 20 Adc,

VGS = 10 Vdc,

RG = 9.1

)

180

TurnOff Delay Time

VGS = 10 Vdc,

RG = 9.1

)

td(off)

100

Fall Time

G = 9.1

)

120

Gate Charge

(See Figure 8)

(VDS = 160 Vdc, ID = 20 Adc,

VGS = 10 Vdc)

(VDS = 160 Vdc, ID = 20 Adc,

VGS = 10 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1)

(IS = 20 Adc, VGS = 0 Vdc)

(IS = 20 Adc, VGS = 0 Vdc, TJ = 125

VSD

--
--

1.0

0.82

1.35

Vdc

Reverse Recovery Time

(See Figure 14)

(IS = 20 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

trr

239

(See Figure 14)

(IS = 20 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

136

(IS = 20 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

103

Reverse Recovery Stored Charge

QRR

2.09

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25

from package to center of die)

4.5

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.

MTB20N20E

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

DS(on)

, DRAINT

OSOURCE RESIST

ANCE

(NORMALIZED)

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

I D

, DRAIN CURRENT

(AMPS)

2.0

8.5

I D

, DRAIN CURRENT

(AMPS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0.05

0.10

0.25

0.30

0.35

0.10

0.11

0.13

0.15

0.17

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current

and Gate Voltage

0.4

1.2

1.6

2.0

2.4

200

100

1000

10000

TJ, JUNCTION TEMPERATURE (

Figure 5. OnResistance Variation with

Temperature

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage

Current versus Voltage

I DSS

, LEAKAGE (nA)

VGS = 10 V
ID = 10 A

100

125

150

TJ = 25

VGS = 10 V

VDS

10 V

TJ = 55

100

TJ = 25

VGS = 0 V

VGS = 10 V

9 V

6 V

7 V

8 V

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0

TJ = 100

0.15

0.20

0.16

0.14

0.12

0.8

100

150

TJ = 125

VGS = 10 V

15 V

5 V

MTB20N20E

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are deter-

mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

C, CAP

ACIT

ANCE (pF)

Figure 7. Capacitance Variation

5000

4000

3000

2000

1000

VGS

VDS

TJ = 25

VDS = 0 V

VGS = 0 V

Ciss

Coss

Ciss

Crss

MTB20N20E

Motorola TMOS Power MOSFET Transistor Device Data

DRAINTOSOURCE DIODE CHARACTERISTICS

0.5

0.6

0.7

0.8

0.9

1.0

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

I S

, SOURCE CURRENT

(AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

100

1000

100

TIME (ns)

VDD = 30 V
ID = 20 A
VGS = 10 V
TJ = 25

td(on)

VGS = 0 V
TJ = 25

Figure 10. Diode Forward Voltage versus Current

180

, GA

TET

OSOURCE VOL

T
AGE (VOL

TS)

150

120

QG, TOTAL GATE CHARGE (nC)

, DRAINT

OSOURCE VOL

T
AGE (VOL

TS)

ID = 20 A
TJ = 25

VDS

VGS

td(off)

0.85

0.75

0.65

0.55

0.95

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25

C. Peak

repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGener-
al Data and Its Use."

Switching between the offstate and the onstate may tra-

verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10

s. In addition the total power aver-

aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A Power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.

Although many EFETs can withstand the stress of drain

tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.

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