1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
TMOS E-FET
.
TM
High Energy Power FET
D2PAK for Surface Mount
NChannel EnhancementMode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltageblocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS EFET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured -- Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
1000
Vdc
DrainGate Voltage (RGS = 1.0 M
)
VDGR
1000
Vdc
GateSource Voltage -- Continuous
GateSource Voltage
-- NonRepetitive (tp
10 ms)
VGS
VGSM
20
40
Vdc
Vpk
Drain Current -- Continuous
Drain Current
-- Continuous @ 100
C
Drain Current
-- Single Pulse (tp
10
s)
ID
ID
IDM
3.0
2.4
9.0
Adc
Apk
Total Power Dissipation
Derate above 25
C
Total Power Dissipation @ TA = 25
C, when mounted with the minimum recommended pad size
PD
125
1.0
2.5
Watts
W/
C
Watts
Operating and Storage Temperature Range
TJ, Tstg
55 to 150
C
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 7.0 Apk, L = 10 mH, RG = 25
)
EAS
245
mJ
Thermal Resistance -- Junction to Case
Thermal Resistance
-- Junction to Ambient
Thermal Resistance
-- Junction to Ambient, when mounted with the minimum recommended pad size
R
JC
R
JA
R
JA
1.0
62.5
50
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
from case for 10 seconds
TL
260
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTB3N100E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MTB3N100E
TMOS POWER FET
3.0 AMPERES
1000 VOLTS
RDS(on) = 4.0 OHM
Motorola Preferred Device
CASE 418B02, Style 2
D2PAK
D
S
G
Motorola, Inc. 1995
REV 2
MTB3N100E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS (TJ = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250
Adc)
Temperature Coefficient (Positive)
V(BR)DSS
1000
--
--
1.23
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 1000 Vdc, VGS = 0 Vdc)
(VDS = 1000 Vdc, VGS = 0 Vdc, TJ = 125
C)
IDSS
--
--
--
--
10
100
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
Adc)
Temperature Coefficient (Negative)
VGS(th)
2.0
--
3.0
6.0
4.0
--
Vdc
mV/
C
Static DrainSource OnResistance (VGS = 10 Vdc, ID = 1.5 Adc)
RDS(on)
--
2.96
4.0
Ohm
DrainSource OnVoltage (VGS = 10 Vdc)
(ID = 3.0 Adc)
(ID = 1.5 Adc, TJ = 125
C)
VDS(on)
--
--
4.97
--
14.4
12.6
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 1.5 Adc)
gFS
2.0
3.56
--
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
--
1316
1800
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
--
117
260
Reverse Transfer Capacitance
f = 1.0 MHz)
Crss
--
26
75
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
(VDD = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc,
RG = 9.1
)
td(on)
--
13
25
ns
Rise Time
(VDD = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc,
RG = 9.1
)
tr
--
19
40
TurnOff Delay Time
VGS = 10 Vdc,
RG = 9.1
)
td(off)
--
42
90
Fall Time
G = 9.1
)
tf
--
33
55
Gate Charge
(See Figure 8)
(VDS = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
QT
--
32.5
45
nC
(See Figure 8)
(VDS = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
Q1
--
6.0
--
(VDS = 400 Vdc, ID = 3.0 Adc,
VGS = 10 Vdc)
Q2
--
14.6
--
Q3
--
13.5
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (1)
(IS = 3.0 Adc, VGS = 0 Vdc)
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125
C)
VSD
--
--
0.794
0.63
1.1
--
Vdc
Reverse Recovery Time
(See Figure 14)
(IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
trr
--
615
--
ns
(See Figure 14)
(IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
ta
--
104
--
(IS = 3.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
tb
--
511
--
Reverse Recovery Stored Charge
QRR
--
2.92
--
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25
from package to center of die)
LD
--
4.5
--
nH
Internal Source Inductance
(Measured from the source lead 0.25
from package to source bond pad)
LS
--
7.5
--
nH
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperature.
MTB3N100E
3
Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE
(NORMALIZED)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
I D
, DRAIN CURRENT
(AMPS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (
C)
Figure 5. OnResistance Variation with
Temperature
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
I DSS
, LEAKAGE (nA)
TJ = 25
C
0
4
8
12
16
20
2
6
10
14
18
3
5 V
6 V
VDS
10 V
2.0
2.8
3.6
4.4
5.2
2.4
3.2
4.0
4.8
TJ = 55
C
25
C
100
C
TJ = 25
C
VGS = 10 V
15 V
2.8
3.4
VGS = 0 V
0
200
400
1
100
100000
100
300
600
500
25
C
100
C
TJ = 125
C
1.0
3.0
5.5
1
3
5
6
4
2
4.5
25
C
55
C
VGS = 10 V
50
0.4
0.8
1.2
2.0
2.4
25
0
25
50
75
100
125
150
VGS = 10 V
ID = 1.5 A
4 V
5
1
1000
3.2
3.6
3.8
3.0
1.6
6
2
4
I D
, DRAIN CURRENT
(AMPS)
5.6
2.0
4.0
6.0
5.0
10
1000
800
0
1.0
3.0
5.0
2.0
4.0
6.0
5.5
3
5
1
6
2
4
0
6.0
2.5
1.5
3.5
1.5
2.5
3.5
4.5
700
900
10000
VGS = 10 V
TJ = 100
C
MTB3N100E
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance
Variation
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
10
100
1000
10000
100
10
1
C, CAP
ACIT
ANCE (pF)
10
0
10
15
20
25
2800
2000
1200
400
0
VGS
VDS
TJ = 25
C
VDS = 0 V
VGS = 0 V
1600
800
5
5
VGS = 0 V
TJ = 25
C
2400
1000
Ciss
Coss
Ciss
Crss
Crss
Ciss
Coss
Crss
MTB3N100E
5
Motorola TMOS Power MOSFET Transistor Device Data
16
QG, TOTAL GATE CHARGE (nC)
DRAINTOSOURCE DIODE CHARACTERISTICS
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1
10
100
1000
100
10
t,
TIME (ns)
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
V
GS
, GA
TET
OSOURCE VOL
T
AGE (VOL
TS)
V
DS
, DRAINT
OSOURCE VOL
T
AGE (VOL
TS)
0
12
ID = 3 A
TJ = 25
C
VDS
VGS
Q1
Q2
QT
30
16
8
2
0
14
4
400
300
200
100
VDD = 500 V
ID = 3 A
VGS = 10 V
TJ = 25
C
0.50
0.70
0.78
0
3.0
0.66
0.74
0
0.80
0.58
0.54
0.62
2.5
1.0
Q3
4
20
28
2.0
1.5
0.5
12
10
6
350
250
150
50
8
24
VGS = 0 V
TJ = 25
C
td(on)
tf
td(off)
tr
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25
C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."
Switching between the offstate and the onstate may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10
s. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R
JC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
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