Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

TMOS V

Power Field Effect Transistor

DPAK for Surface Mount

NChannel EnhancementMode Silicon Gate

TMOS V is a new technology designed to achieve an onresis-

tance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

New Features of TMOS V

Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology

Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS

Avalanche Energy Specified

IDSS and VDS(on) Specified at Elevated Temperature

Static Parameters are the Same for both TMOS V and TMOS EFET

Surface Mount Package Available in 16 mm 13inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

Vdc

DrainGate Voltage (RGS = 1.0 M

)

VDGR

Vdc

GateSource Voltage -- Continuous

GateSource Voltage

-- Single Pulse (tp

50 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous @ 25

Drain Current

-- Continuous @ 100

Drain Current

-- Single Pulse (tp

ID
ID

IDM

8.7

Adc

Apk

Total Power Dissipation @ 25

Derate above 25

Total Power Dissipation @ TA = 25

C, when mounted to minimum recommended pad size

0.36

2.1

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25

)

EAS

113

Thermal Resistance -- Junction to Case

Thermal Resistance

-- Junction to Ambient

Thermal Resistance

-- Junction to Ambient, when mounted to minimum recommended pad size

2.73

100

71.4

C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

from case for 10 seconds

260

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

EFET, Designer's and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.
REV 2

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

CASE 369A13, Style 2

DPAK Surface Mount

MTD15N06V

TMOS POWER FET

15 AMPERES

60 VOLTS

RDS(on) = 0.12 OHM

Motorola Preferred Device

Motorola, Inc. 1996

MTD15N06V

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DrainSource Breakdown Voltage

(VGS = 0 Vdc, ID = 250

Adc)

Temperature Coefficient (Positive)

V(BR)DSS

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150

IDSS

--
--

100

Adc

GateBody Leakage Current (VGS =

20 Vdc, VDS = 0)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250

Adc)

Temperature Coefficient (Negative)

VGS(th)

2.0

2.7
5.0

4.0

Vdc

mV/

Static DrainSource OnResistance (VGS = 10 Vdc, ID = 7.5 Adc)

RDS(on)

0.08

0.12

Ohm

DrainSource OnVoltage (VGS = 10 Vdc)

(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 150

VDS(on)

--
--

2.0

2.2
1.9

Vdc

Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc)

gFS

4.0

6.2

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Ciss

469

660

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

148

200

Reverse Transfer Capacitance

f = 1.0 MHz)

Crss

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

(VDD = 30 Vdc, ID = 15 Adc,

VGS = 10 Vdc,

RG = 9.1

)

td(on)

7.6

Rise Time

(VDD = 30 Vdc, ID = 15 Adc,

VGS = 10 Vdc,

RG = 9.1

)

100

TurnOff Delay Time

VGS = 10 Vdc,

RG = 9.1

)

td(off)

Fall Time

G = 9.1

)

Gate Charge

(See Figure 8)

(VDS = 48 Vdc, ID = 15 Adc,

VGS = 10 Vdc)

14.4

(See Figure 8)

(VDS = 48 Vdc, ID = 15 Adc,

VGS = 10 Vdc)

2.8

(VDS = 48 Vdc, ID = 15 Adc,

VGS = 10 Vdc)

6.4

6.1

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1)

(IS = 15 Adc, VGS = 0 Vdc)

(IS = 15 Adc, VGS = 0 Vdc, TJ = 150

VSD

--
--

1.05

1.5

1.6

Vdc

Reverse Recovery Time

(See Figure 14)

(IS = 15 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

trr

59.3

(See Figure 14)

(IS = 15 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

(IS = 15 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

13.3

Reverse Recovery Stored Charge

QRR

0.165

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25

from package to center of die)

4.5

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.

MTD15N06V

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

I D

, DRAIN CURRENT

(AMPS)

I D

, DRAIN CURRENT

(AMPS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

0.05

0.10

0.20

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

Figure 4. OnResistance versus Drain Current

and Gate Voltage

100

Figure 5. OnResistance Variation with

Temperature

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage

Current versus Voltage

I DSS

, LEAKAGE (nA)

TJ = 25

VGS = 10 V

9 V

8 V

6 V

5 V

7 V

VGS = 10 V

TJ = 100

TJ = 55

100

VGS = 0 V

TJ = 125

VDS

10 V

0.15

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

ID, DRAIN CURRENT (AMPS)

TJ = 25

0.13

0.11

0.09

0.07

0.05

VGS = 10 V

15 V

DS(on)

, DRAINT

OSOURCE RESIST

ANCE

(NORMALIZED)

TJ, JUNCTION TEMPERATURE (

VGS = 10 V
ID = 7.5 A

1.6

1.2

0.8

0.4

100

125

150

175

MTD15N06V

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are deter-

mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

C, CAP

ACIT

ANCE (pF)

Figure 7. Capacitance Variation

VGS

VDS

1500

1200

900

600

300

TJ = 25

VDS = 0 V

Ciss

Coss

Crss

VGS = 0 V

Ciss

Crss

MTD15N06V

Motorola TMOS Power MOSFET Transistor Device Data

, DRAINT

OSOURCE VOL

T
AGE (VOL

TS)

, GA

TET

OSOURCE VOL

T
AGE (VOL

TS)

DRAINTOSOURCE DIODE CHARACTERISTICS

0.5

0.7

0.9

1.1

1.3

1.5

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

I S

, SOURCE CURRENT

(AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

100

TIME (ns)

VDD = 30 V
ID = 15 A
VGS = 10 V
TJ = 25

VGS = 0 V
TJ = 25

Figure 10. Diode Forward Voltage versus Current

QT, TOTAL CHARGE (nC)

ID = 15 A
TJ = 25

1000

100

td(off)

td(on)

VGS

VDS

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25

C. Peak

repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."

Switching between the offstate and the onstate may tra-

verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10

s. In addition the total power aver-

aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A Power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.

Although many EFETs can withstand the stress of drain

tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.

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