Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

HDTMOS E-FET

High Density Power FET

DPAK for Surface Mount

PChannel EnhancementMode Silicon Gate

This advanced highcell density HDTMOS EFET is designed to

withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a draintosource
diode with a fast recovery time. Designed for lowvoltage,
highspeed switching applications in power supplies, converters
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
margin against unexpected voltage transients.

Ultra Low RDS(on), HighCell Density, HDTMOS

Diode is Characterized for Use in Bridge Circuits

IDSS and VDS(on) Specified at Elevated Temperature

Avalanche Energy Specified

Surface Mount Package Available in 16 mm, 13inch/2500
Unit, Tape & Reel, Add T4 Suffix to Part Number

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DrainSource Voltage

VDSS

Vdc

DrainGate Voltage (RGS = 1.0 M

)

VDGR

Vdc

GateSource Voltage -- Continuous

GateSource Voltage

-- NonRepetitive (tp

10 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous

Drain Current

-- Continuous @ 100

Drain Current

-- Single Pulse (tp

ID
ID

IDM

9.0

Adc

Apk

Total Power Dissipation

Derate above 25

Total Power Dissipation @ TC = 25

C (1)

0.58
1.75

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25

(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 15 Apk, L = 2.7 mH, RG = 25

)

EAS

300

Thermal Resistance -- Junction to Case

Thermal Resistance

-- Junction to Ambient

Thermal Resistance

-- Junction to Ambient (1)

1.73

100

71.4

C/W

Maximum Temperature for Soldering Purposes, 1/8

from case for 10 seconds

260

(1) When surface mounted to an FR4 board using the minimum recommended pad size.

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

Designer's, EFET and HDTMOS are trademarks of Motorola Inc.
TMOS is a registered trademark of Motorola Inc.
Thermal Clad is a trademark of the Bergquist Company.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 1

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by MTD20P06HDL/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1995

MTD20P06HDL

TMOS POWER FET

LOGIC LEVEL

15 AMPERES

60 VOLTS

RDS(on) = 175 M

Motorola Preferred Device

CASE 369A13, Style 2

DPAK

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DrainSource Breakdown Voltage

(VGS = 0 Vdc, ID = 250

Adc)

Temperature Coefficient (Positive)

V(BR)DSS

81.3

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125

IDSS

--
--

1.0

Adc

GateBody Leakage Current (VGS =

15 Vdc, VDS = 0)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250

Adc)

Temperature Coefficient (Negative)

VGS(th)

1.0

1.7
3.9

2.0

Vdc

mV/

Static DrainSource OnResistance

(VGS = 5.0 Vdc, ID = 7.5 Adc)

RDS(on)

143

175

DrainSource OnVoltage (VGS = 5.0 Vdc)

(ID = 15 Adc)
(ID = 7.5 Adc, TJ = 125

VDS(on)

--
--

2.3
1.6

3.0
2.0

Vdc

Forward Transconductance (VDS = 10 Vdc, ID = 7.5 Adc)

gFS

9.0

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Ciss

850

1190

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

210

290

Reverse Transfer Capacitance

f = 1.0 MHz)

Crss

130

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

(VDS = 30 Vdc, ID = 15 Adc,

VGS = 5.0 Vdc,

RG = 9.1

)

td(on)

Rise Time

(VDS = 30 Vdc, ID = 15 Adc,

VGS = 5.0 Vdc,

RG = 9.1

)

175

350

TurnOff Delay Time

VGS = 5.0 Vdc,

RG = 9.1

)

td(off)

Fall Time

G = 9.1

)

136

Gate Charge

(VDS = 48 Vdc, ID = 15 Adc,

VGS = 5.0 Vdc)

20.6

(VDS = 48 Vdc, ID = 15 Adc,

VGS = 5.0 Vdc)

3.7

(VDS = 48 Vdc, ID = 15 Adc,

VGS = 5.0 Vdc)

7.6

8.4

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage

(IS = 15 Adc, VGS = 0 Vdc)

(IS = 15 Adc, VGS = 0 Vdc, TJ = 125

VSD

--
--

2.5
1.9

3.0

Vdc

Reverse Recovery Time

(IS = 15 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

trr

(IS = 15 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

(IS = 15 Adc, VGS = 0 Vdc,

dIS/dt = 100 A/

Reverse Recovery Stored Charge

QRR

0.177

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from the drain lead 0.25

from package to center of die)

4.5

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

DS(on)

, DRAINT

OSOURCE RESIST

ANCE

(NORMALIZED)

DS(on)

, DRAINT

OSOURCE RESIST

ANCE (OHMS)

I DSS

, LEAKAGE (nA)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

TJ, JUNCTION TEMPERATURE (

ID, DRAIN CURRENT (AMPS)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

I D

, DRAIN CURRENT

(AMPS)

I D

, DRAIN CURRENT

(AMPS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

Figure 3. OnResistance versus Drain Current

and Temperature

Figure 4. OnResistance versus Drain Current

and Gate Voltage

100

Figure 5. OnResistance Variation with

Temperature

Figure 6. DrainToSource Leakage

Current versus Voltage

VDS

5 V

100

VGS = 5 V

100

125

150

VGS = 0 V

TJ = 125

TJ = 100

TJ = 25

VGS = 5 V

VGS = 5 V
ID = 7.5 A

VGS = 10 V

8 V

4 V

TJ = 25

100

10 V

6 V

7 V

9 V

TJ = 55

0.40

0.32

0.24

0.16

0.08

0.275

0.250

0.225

0.200

0.175

0.150

0.125

0.100

1.8

1.6

1.4

1.2

0.8

0.6

0.4

0.2

5 V

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are deter-

mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (Volts)

C, CAP

ACIT

ANCE (pF)

Figure 7. Capacitance Variation

2500

2000

500

VGS

VDS

1500

1000

VDS = 0 V

Ciss

Crss

VGS = 0 V

TJ = 25

Ciss

Coss

Crss

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

QG, TOTAL GATE CHARGE (nC)

RG, GATE RESISTANCE (Ohms)

TIME (ns)

, DRAINT

OSOURCE VOL

T
AGE (VOL

TS)

, GA

TET

OSOURCE VOL

T
AGE (VOL

TS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

100

1000

100

VDD = 30 V
ID = 15 A
VGS = 5.0 V
TJ = 25

td(on)

td(off)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

VGS

ID = 15 A
TJ = 25

VDS

DRAINTOSOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode

are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse re-
covery characteristics which play a major role in determining
switching losses, radiated noise, EMI and RFI.

System switching losses are largely due to the nature of

the body diode itself. The body diode is a minority carrier de-
vice, therefore it has a finite reverse recovery time, trr, due to
the storage of minority carrier charge, QRR, as shown in the
typical reverse recovery wave form of Figure 12. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further
increases switching losses. Therefore, one would like a
diode with short trr and low QRR specifications to minimize
these losses.

The abruptness of diode reverse recovery effects the

amount of radiated noise, voltage spikes, and current ring-
ing. The mechanisms at work are finite irremovable circuit
parasitic inductances and capacitances acted upon by high

di/dts. The diode's negative di/dt during ta is directly con-
trolled by the device clearing the stored charge. However,
the positive di/dt during tb is an uncontrollable diode charac-
teristic and is usually the culprit that induces current ringing.
Therefore, when comparing diodes, the ratio of tb/ta serves
as a good indicator of recovery abruptness and thus gives a
comparative estimate of probable noise generated. A ratio of
1 is considered ideal and values less than 0.5 are considered
snappy.

Compared to Motorola standard cell density low voltage

MOSFETs, high cell density MOSFET diodes are faster
(shorter trr), have less stored charge and a softer reverse re-
covery characteristic. The softness advantage of the high
cell density diode means they can be forced through reverse
recovery at a higher di/dt than a standard cell MOSFET
diode without increasing the current ringing or the noise gen-
erated. In addition, power dissipation incurred from switching
the diode will be less due to the shorter recovery time and
lower switching losses.

I S

, SOURCE CURRENT

(AMPS)

VSD, SOURCETODRAIN VOLTAGE (Volts)

0.5

1.5

Figure 10. Diode Forward Voltage versus Current

VGS = 0 V
TJ = 25

2.5

1.25

0.75

1.75

2.25

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

I S

, SOURCE CURRENT

t, TIME

Figure 11. Reverse Recovery Time (trr)

di/dt = 300 A/

Standard Cell Density

High Cell Density

trr

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25

C. Peak

repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal Resistance Gen-
eral Data and Its Use."

Switching between the offstate and the onstate may tra-

verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded, and that the transition
time (tr, tf) does not exceed 10

s. In addition the total power

averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and must be adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction tem-
perature.

Although many EFETs can withstand the stress of drain

tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 13). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I D

, DRAIN CURRENT

(AMPS)

, SINGLE PULSE DRAINT

OSOURCE

ALANCHE ENERGY

(mJ)

TJ, STARTING JUNCTION TEMPERATURE (

Figure 12. Maximum Rated Forward Biased

Safe Operating Area

100

125

180

300

120

150

240

0.1

1.0

100

1.0

0.1

Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature

100

1 ms

10 ms

ID = 15 A

VGS = 20 V
SINGLE PULSE
TC = 25

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE

RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS

Surface mount board layout is a critical portion of the total

design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface

between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.

0.190
4.826

inches

0.100

2.54

0.063

1.6

0.165
4.191

0.118

3.0

0.243
6.172

POWER DISSIPATION FOR A SURFACE MOUNT DEVICE

The power dissipation for a surface mount device is a

function of the drain pad size. These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, R

JA, the thermal resistance

from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:

PD =

TJ(max) TA

The values for the equation are found in the maximum

ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25

C, one can

calculate the power dissipation of the device. For a DPAK
device, PD is calculated as follows.

PD =

150

C 25

71.4

C/W

= 1.75 Watts

The 71.4

C/W for the DPAK package assumes the use of

the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 1.75 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power

dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R

JA versus drain pad area is shown in Figure 16.

Figure 16. Thermal Resistance versus Drain Pad

Area for the DPAK Package (Typical)

1.75 Watts

Board Material = 0.0625

G10/FR4, 2 oz Copper

100

3.0 Watts

5.0 Watts

TA = 25

A, AREA (SQUARE INCHES)

AMBIENT

(

C/W)

,
THERMAL

RESIST

ANCE, JUNCTION

Another alternative would be to use a ceramic substrate or

an aluminum core board such as Thermal Clad

. Using a

board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

SOLDER STENCIL GUIDELINES

Prior to placing surface mount components onto a printed

circuit board, solder paste must be applied to the pads. Solder
stencils are used to screen the optimum amount. These
stencils are typically 0.008 inches thick and may be made of
brass or stainless steel. For packages such as the SC59,
SC70/SOT323, SOD123, SOT23, SOT143, SOT223,
SO8, SO14, SO16, and SMB/SMC diode packages, the
stencil opening should be the same as the pad size or a 1:1
registration. This is not the case with the DPAK and D2PAK
packages. If one uses a 1:1 opening to screen solder onto the
drain pad, misalignment and/or "tombstoning" may occur due
to an excess of solder. For these two packages, the opening
in the stencil for the paste should be approximately 50% of the
tab area. The opening for the leads is still a 1:1 registration.
Figure 17 shows a typical stencil for the DPAK and D2PAK
packages. The pattern of the opening in the stencil for the
drain pad is not critical as long as it allows approximately 50%
of the pad to be covered with paste.

ÇÇÇ

ÇÇ

Figure 17. Typical Stencil for DPAK and

D2PAK Packages

SOLDER PASTE
OPENINGS

STENCIL

SOLDERING PRECAUTIONS

The melting temperature of solder is higher than the rated

temperature of the device. When the entire device is heated
to a high temperature, failure to complete soldering within a
short time could result in device failure. Therefore, the
following items should always be observed in order to
minimize the thermal stress to which the devices are
subjected.

Always preheat the device.

The delta temperature between the preheat and soldering

should be 100

C or less.*

When preheating and soldering, the temperature of the

leads and the case must not exceed the maximum
temperature ratings as shown on the data sheet. When
using infrared heating with the reflow soldering method,
the difference shall be a maximum of 10

The soldering temperature and time shall not exceed

260

C for more than 10 seconds.

When shifting from preheating to soldering, the maximum

temperature gradient shall be 5

C or less.

After soldering has been completed, the device should be

allowed to cool naturally for at least three minutes.
Gradual cooling should be used as the use of forced
cooling will increase the temperature gradient and result
in latent failure due to mechanical stress.

Mechanical stress or shock should not be applied during

cooling.

* Soldering a device without preheating can cause excessive
thermal shock and stress which can result in damage to the
device.

* Due to shadowing and the inability to set the wave height to
incorporate other surface mount components, the D2PAK is
not recommended for wave soldering.

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control

settings that will give the desired heat pattern. The operator
must set temperatures for several heating zones, and a figure
for belt speed. Taken together, these control settings make up
a heating "profile" for that particular circuit board. On
machines controlled by a computer, the computer remembers
these profiles from one operating session to the next. Figure
18 shows a typical heating profile for use when soldering a
surface mount device to a printed circuit board. This profile will
vary among soldering systems but it is a good starting point.
Factors that can affect the profile include the type of soldering
system in use, density and types of components on the board,
type of solder used, and the type of board or substrate material
being used. This profile shows temperature versus time. The

line on the graph shows the actual temperature that might be
experienced on the surface of a test board at or near a central
solder joint. The two profiles are based on a high density and
a low density board. The Vitronics SMD310 convection/in-
frared reflow soldering system was used to generate this
profile. The type of solder used was 62/36/2 Tin Lead Silver
with a melting point between 177 189

C. When this type of

furnace is used for solder reflow work, the circuit boards and
solder joints tend to heat first. The components on the board
are then heated by conduction. The circuit board, because it
has a large surface area, absorbs the thermal energy more
efficiently, then distributes this energy to the components.
Because of this effect, the main body of a component may be
up to 30 degrees cooler than the adjacent solder joints.

STEP 1

PREHEAT

ZONE 1
"RAMP"

STEP 2

VENT

"SOAK"

STEP 3

HEATING

ZONES 2 & 5

"RAMP"

STEP 4

HEATING

ZONES 3 & 6

"SOAK"

STEP 5

HEATING

ZONES 4 & 7

"SPIKE"

STEP 6

VENT

STEP 7

COOLING

200

150

100

TIME (3 TO 7 MINUTES TOTAL)

TMAX

SOLDER IS LIQUID FOR

40 TO 80 SECONDS

(DEPENDING ON

MASS OF ASSEMBLY)

205

TO 219

PEAK AT
SOLDER JOINT

DESIRED CURVE FOR LOW

MASS ASSEMBLIES

100

150

160

170

140

Figure 18. Typical Solder Heating Profile

DESIRED CURVE FOR HIGH

MASS ASSEMBLIES

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 369A13

ISSUE W

STYLE 2:

PIN 1. GATE

2. DRAIN
3. SOURCE
4. DRAIN

2 PL

0.13 (0.005)

T

SEATING
PLANE

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.235

0.250

5.97

6.35

0.250

0.265

6.35

6.73

0.086

0.094

2.19

2.38

0.027

0.035

0.69

0.88

0.033

0.040

0.84

1.01

0.037

0.047

0.94

1.19

0.180 BSC

4.58 BSC

0.034

0.040

0.87

1.01

0.018

0.023

0.46

0.58

0.102

0.114

2.60

2.89

0.090 BSC

2.29 BSC

0.175

0.215

4.45

5.46

0.020

0.050

0.51

1.27

0.020

0.51

0.030

0.050

0.77

1.27

0.138

3.51

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

MTD20P06HDL

Motorola TMOS Power MOSFET Transistor Device Data

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does
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MTD20P06HDL/D

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