1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
TMOS E-FET
.
TM
Power Field Effect Transistor
NChannel EnhancementMode Silicon Gate
This advanced TMOS EFET is designed to withstand high
energy in the avalanche and commutation modes. The new energy
efficient design also offers a draintosource diode with a fast
recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
SourcetoDrain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
250
Vdc
DrainGate Voltage (RGS = 1.0 M
)
VDGR
250
Vdc
GateSource Voltage -- Continuous
-- NonRepetitive (tp
10 ms)
VGS
VGSM
20
40
Vdc
Vpk
Drain Current -- Continuous
-- Continuous @ 100
C
-- Single Pulse (tp
10
s)
ID
ID
IDM
16
10
56
Adc
Apk
Total Power Dissipation @ TC = 25
C
Derate above 25
C
PD
125
1.0
Watts
W/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to 150
C
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25
)
EAS
384
mJ
Thermal Resistance -- Junction to Case
-- Junction to Ambient
R
JC
R
JA
1.0
62.5
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
from case for 10 seconds
TL
260
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTP16N25E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1995
MTP16N25E
TMOS POWER FET
16 AMPERES
250 VOLTS
RDS(on) = 0.25 OHM
Motorola Preferred Device
D
S
G
CASE 221A06, Style 5
TO220AB
MTP16N25E
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(VGS = 0 Vdc, ID = 250
Adc)
Temperature Coefficient (Positive)
V(BR)DSS
250
--
--
333
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 250 Vdc, VGS = 0 Vdc)
(VDS = 250 Vdc, VGS = 0 Vdc, TJ = 125
C)
IDSS
--
--
--
--
10
100
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250
Adc)
Temperature Coefficient (Negative)
VGS(th)
2.0
--
3.0
7.0
4.0
--
Vdc
mV/
C
Static DrainSource OnResistance (VGS = 10 Vdc, ID = 8.0 Adc)
RDS(on)
--
0.17
0.25
Ohm
DrainSource OnVoltage (VGS = 10 Vdc)
(ID = 16 Adc)
(ID = 8.0 Adc, TJ = 125
C)
VDS(on)
--
--
3.6
--
4.8
4.2
Vdc
Forward Transconductance (VDS = 15 Vdc, ID = 8.0 Adc)
gFS
3.0
7.0
--
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Ciss
--
1558
2180
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
--
281
390
Reverse Transfer Capacitance
f = 1.0 MHz)
Crss
--
130
260
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
(VDD = 125 Vdc, ID = 16 Adc,
VGS = 10 Vdc,
RG = 9.1
)
td(on)
--
15
30
ns
Rise Time
(VDD = 125 Vdc, ID = 16 Adc,
VGS = 10 Vdc,
RG = 9.1
)
tr
--
64
130
TurnOff Delay Time
VGS = 10 Vdc,
RG = 9.1
)
td(off)
--
56
110
Fall Time
G = 9.1
)
tf
--
44
90
Gate Charge
(See Figure 8)
(VDS = 200 Vdc, ID = 16 Adc,
VGS = 10 Vdc)
QT
--
53.4
70
nC
(See Figure 8)
(VDS = 200 Vdc, ID = 16 Adc,
VGS = 10 Vdc)
Q1
--
9.3
--
(VDS = 200 Vdc, ID = 16 Adc,
VGS = 10 Vdc)
Q2
--
27.5
--
Q3
--
17.1
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (1)
(IS = 16 Adc, VGS = 0 Vdc)
(IS = 16 Adc, VGS = 0 Vdc, TJ = 125
C)
VSD
--
--
0.915
1.39
1.5
--
Vdc
Reverse Recovery Time
(See Figure 14)
(IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
trr
--
234
--
ns
(See Figure 14)
(IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
ta
--
170
--
(IS = 16 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/
s)
tb
--
64
--
Reverse Recovery Stored Charge
QRR
--
2.165
--
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25
from package to center of die)
LD
--
--
3.5
4.5
--
--
nH
Internal Source Inductance
(Measured from the source lead 0.25
from package to source bond pad)
LS
--
7.5
--
nH
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperature.
MTP16N25E
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Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE
(NORMALIZED)
R
DS(on)
, DRAINT
OSOURCE RESIST
ANCE (OHMS)
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
I D
, DRAIN CURRENT
(AMPS)
I D
, DRAIN CURRENT
(AMPS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (
C)
Figure 5. OnResistance Variation with
Temperature
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
I DSS
, LEAKAGE (nA)
TJ = 25
C
VDS
10 V
TJ = 55
C
25
C
100
C
25
C
TJ = 25
C
VGS = 0 V
VGS = 10 V
VGS = 10 V
VGS = 10 V
VGS = 10 V
ID = 8 A
7 V
8 V
6 V
5 V
15 V
100
C
25
C
TJ = 100
C
55
C
32
24
16
8
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
32
24
16
8
0
32
24
16
8
0
0.26
40
0.22
0.18
0.14
0.1
0.6
0.5
0.4
0
20
15
10
5
0
35
30
25
0.3
0.2
0.1
TJ = 125
C
100
50
0
1000
100
10
1
150
200
250
300
0
50
50
1.0
0.5
0
150
100
125
25
25
75
2.0
1.5
3.0
2.5
MTP16N25E
4
Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are deter-
mined by how fast the FET input capacitance can be charged
by current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements com-
plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE (pF)
Figure 7. Capacitance Variation
5000
0
VGS
VDS
TJ = 25
C
VDS = 0 V
VGS = 0 V
Ciss
Coss
Crss
Crss
Ciss
4000
3000
2000
1000
25
20
15
10
5
0
5
10
MTP16N25E
5
Motorola TMOS Power MOSFET Transistor Device Data
DRAINTOSOURCE DIODE CHARACTERISTICS
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1
10
100
100
10
1
t,
TIME (ns)
VDD = 250 V
ID = 16 A
VGS = 10 V
TJ = 25
C
tr
td(off)
td(on)
VGS = 0 V
TJ = 25
C
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
200
V
GS
, GA
TET
OSOURCE VOL
T
AGE (VOL
TS)
150
100
50
0
0
6
0
QT, TOTAL CHARGE (nC)
V
DS
, DRAINT
OSOURCE VOL
T
AGE (VOL
TS)
12
9
3
10
20
30
ID = 16 A
TJ = 25
C
Q1
VGS
Q2
VDS
Q3
0.75
0.8
0.85
0.9
0.95
0.5
0.55
0.6
0.65
0.7
16
12
8
4
0
40
50
60
QT
1000
tf
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25
C. Peak
repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."
Switching between the offstate and the onstate may tra-
verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10
s. In addition the total power aver-
aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R
JC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For reli-
able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of drain
tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.
MTP16N25E
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Motorola TMOS Power MOSFET Transistor Device Data
SAFE OPERATING AREA
1.0E05
1.0E04
1.0E02
0.1
1.0
0.01
1.0E03
1.0E01
1.0E+00
1.0E+01
0.05
0.01
SINGLE PULSE
0.02
TJ, STARTING JUNCTION TEMPERATURE (
C)
E AS
, SINGLE PULSE DRAINT
OSOURCE
Figure 12. Maximum Avalanche Energy versus
Starting Junction Temperature
0.1
1000
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
1.0
100
A
V
ALANCHE ENERGY
(mJ)
I D
, DRAIN CURRENT
(AMPS)
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
0
25
50
75
100
125
10
VGS = 20 V
SINGLE PULSE
TC = 25
C
400
200
100
ID = 16 A
300
10
1.0
100
150
t,TIME (s)
Figure 13. Thermal Response
r(t)
, NORMALIZED EFFECTIVE
TRANSIENT
THERMAL
RESIST
ANCE
R
JC(t) = r(t) R
JC
D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) R
JC(t)
P(pk)
t1
t2
DUTY CYCLE, D = t1/t2
Figure 14. Diode Reverse Recovery Waveform
di/dt
trr
ta
tp
IS
0.25 IS
TIME
IS
tb
10 ms
1 ms
dc
100
s
10
s
0.1
D = 0.5
0.2
MTP16N25E
7
Motorola TMOS Power MOSFET Transistor Device Data
PACKAGE DIMENSIONS
CASE 221A06
ISSUE Y
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
DIM
MIN
MAX
MIN
MAX
MILLIMETERS
INCHES
A
0.570
0.620
14.48
15.75
B
0.380
0.405
9.66
10.28
C
0.160
0.190
4.07
4.82
D
0.025
0.035
0.64
0.88
F
0.142
0.147
3.61
3.73
G
0.095
0.105
2.42
2.66
H
0.110
0.155
2.80
3.93
J
0.018
0.025
0.46
0.64
K
0.500
0.562
12.70
14.27
L
0.045
0.060
1.15
1.52
N
0.190
0.210
4.83
5.33
Q
0.100
0.120
2.54
3.04
R
0.080
0.110
2.04
2.79
S
0.045
0.055
1.15
1.39
T
0.235
0.255
5.97
6.47
U
0.000
0.050
0.00
1.27
V
0.045
1.15
Z
0.080
2.04
B
Q
H
Z
L
V
G
N
A
K
F
1
2 3
4
D
SEATING
PLANE
T
C
S
T
U
R
J
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
MTP16N25E
8
Motorola TMOS Power MOSFET Transistor Device Data
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different
applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does
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associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
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are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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