1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's
TM
Data Sheet
TMOS V
TM
Power Field Effect Transistor
NChannel EnhancementMode Silicon Gate
TMOS V is a new technology designed to achieve an onresis-
tance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.
New Features of TMOS V
Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than EFET Predecessors
Features Common to TMOS V and TMOS EFETS
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and TMOS EFET
MAXIMUM RATINGS
(TC = 25
C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
60
Vdc
DrainGate Voltage (RGS = 1.0 M
)
VDGR
60
Vdc
GateSource Voltage -- Continuous
GateSource Voltage
-- NonRepetitive (tp
10 ms)
VGS
VGSM
20
25
Vdc
Vpk
Drain Current -- Continuous
Drain Current
-- Continuous @ 100
C
Drain Current
-- Single Pulse (tp
10
s)
ID
ID
IDM
52
41
182
Adc
Apk
Total Power Dissipation
Derate above 25
C
PD
188
1.25
Watts
W/
C
Operating and Storage Temperature Range
TJ, Tstg
55 to 175
C
Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25
C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 52 Apk, L = 0.3
mH, RG = 25
)
EAS
406
mJ
Thermal Resistance -- Junction to Case
Thermal Resistance
-- Junction to Ambient
R
JC
R
JA
0.8
62.5
C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
from case for 10 seconds
TL
260
C
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
EFET, Designer's, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 3
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MTP52N06V
TMOS POWER FET
52 AMPERES
60 VOLTS
RDS(on) = 0.022 OHM
Motorola Preferred Device
CASE 221A06, Style 5
TO220AB
TM
D
S
G
Motorola, Inc. 1996
MTP52N06V
2
Motorola TMOS Power MOSFET Transistor Device Data
ELECTRICAL CHARACTERISTICS
(TJ = 25
C unless otherwise noted)
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
DrainSource Breakdown Voltage
(Cpk
2.0) (3)
(VGS = 0 Vdc, ID = 0.25 mAdc)
Temperature Coefficient (Positive)
V(BR)DSS
60
--
--
66
--
--
Vdc
mV/
C
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150
C)
IDSS
--
--
--
--
10
100
Adc
GateBody Leakage Current (VGS =
20 Vdc, VDS = 0)
IGSS
--
--
100
nAdc
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(Cpk
2.0) (3)
(VDS = VGS, ID = 250
Adc)
Temperature Coefficient (Negative)
VGS(th)
2.0
--
2.7
6.4
4.0
--
Vdc
mV/
C
Static DrainSource OnResistance
(Cpk
2.0) (3)
(VGS = 10 Vdc, ID = 26 Adc)
RDS(on)
--
0.019
0.022
Ohm
DrainSource OnVoltage
(VGS = 10 Vdc, ID = 52 Adc)
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150
C)
VDS(on)
--
--
--
--
1.4
1.2
Vdc
Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)
gFS
17
24
--
mhos
DYNAMIC CHARACTERISTICS
Input Capacitance
(V
25 Vdc V
0 Vdc
Ciss
--
1900
2660
pF
Output Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
Coss
--
580
810
Reverse Transfer Capacitance
f = 1.0 MHz)
Crss
--
150
300
SWITCHING CHARACTERISTICS (2)
TurnOn Delay Time
(V
30 Vd
I
52 Ad
td(on)
--
12
20
ns
Rise Time
(VDD = 30 Vdc, ID = 52 Adc,
VGS = 10 Vdc
tr
--
298
600
TurnOff Delay Time
VGS = 10 Vdc,
RG = 9.1
)
td(off)
--
70
140
Fall Time
G
)
tf
--
110
220
Gate Charge
(See Figure 8)
(V
48 Vd
I
52 Ad
QT
--
125
175
nC
(See Figure 8)
(VDS = 48 Vdc, ID = 52 Adc,
Q1
--
10
--
( DS
, D
,
VGS = 10 Vdc)
Q2
--
30
--
Q3
--
40
--
SOURCEDRAIN DIODE CHARACTERISTICS
Forward OnVoltage (1)
(IS = 52 Adc, VGS = 0 Vdc)
(IS = 52 Adc, VGS = 0 Vdc, TJ = 150
C)
VSD
--
--
1.0
0.98
1.5
--
Vdc
Reverse Recovery Time
(See Figure 14)
(I
52 Ad
V
0 Vd
trr
--
100
--
ns
(See Figure 14)
(IS = 52 Adc, VGS = 0 Vdc,
ta
--
80
--
( S
,
GS
,
dIS/dt = 100 A/
s)
tb
--
20
--
Reverse Recovery Stored Charge
QRR
--
0.341
--
C
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25
from package to center of die)
LD
--
--
3.5
4.5
--
--
nH
Internal Source Inductance
(Measured from the source lead 0.25
from package to source bond pad)
LS
--
7.5
--
nH
(1) Pulse Test: Pulse Width
300
s, Duty Cycle
2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Cpk =
Max limit Typ
3 x SIGMA
MTP52N06V
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Motorola TMOS Power MOSFET Transistor Device Data
TYPICAL ELECTRICAL CHARACTERISTICS
R
DS(on)
, DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
R
DS(on)
, DRAINT
OSOURCE
RESIST
ANCE
(NORMALIZED)
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
I D
, DRAIN CURRENT
(AMPS)
I D
, DRAIN CURRENT
(AMPS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 2. Transfer Characteristics
R
DS(on)
, DRAINT
OSOURCE
RESIST
ANCE
(OHMS)
ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus Drain Current
and Temperature
ID, DRAIN CURRENT (AMPS)
Figure 4. OnResistance versus Drain Current
and Gate Voltage
TJ, JUNCTION TEMPERATURE (
C)
Figure 5. OnResistance Variation with
Temperature
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 6. DrainToSource Leakage
Current versus Voltage
I DSS
, LEAKAGE (nA)
TJ = 25
C
VGS = 10 V
9 V
8 V
7 V
6 V
5 V
100
80
60
40
20
0
2
0
7.5
7
5
3
2.5
VDS
10 V
TJ = 55
C
100
C
25
C
VGS = 10 V
0.035
20
0
0.03
0
40
60
80
100
TJ = 100
C
25
C
55
C
TJ = 25
C
0.023
0.015
5
VGS = 10 V
15 V
VGS = 10 V
ID = 26 A
1.75
1.5
1
0.5
0.25
50
25
0
25
50
75
100
125
150
VGS = 0 V
TJ = 125
C
1
0
10
20
30
40
50
60
4
6
8
10
100
80
60
40
20
0
2
4
6
8
0.02
0.015
0.01
0.021
0.019
0.017
25
45
65
85
105
100
10
100
C
175
2
110
90
70
50
30
10
1
3
5
7
9
90
70
50
30
10
110
3.5
4.5
5.5
6.5
0.025
0.005
30
10
50
70
90
110
0.022
0.020
0.018
0.016
15
35
55
75
95
1.25
0.75
MTP52N06V
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Motorola TMOS Power MOSFET Transistor Device Data
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (
t) are determined
by how fast the FET input capacitance can be charged by
current from the generator.
The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:
tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate resis-
tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.
GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
C, CAP
ACIT
ANCE
(pF)
Figure 7. Capacitance Variation
6000
VGS
VDS
VDS = 0 V
5000
4000
3000
2000
0
10
5
0
VGS = 0 V
TJ = 25
C
5
10
15
20
25
Ciss
Coss
Crss
Ciss
Crss
1000
7000
MTP52N06V
5
Motorola TMOS Power MOSFET Transistor Device Data
V
DS
, DRAINT
OSOURCE
VOL
T
AGE
(VOL
TS)
V
GS
, GA
TET
OSOURCE
VOL
T
AGE
(VOL
TS)
DRAINTOSOURCE DIODE CHARACTERISTICS
VSD, SOURCETODRAIN VOLTAGE (VOLTS)
Figure 8. GateToSource and DrainToSource
Voltage versus Total Charge
I S
, SOURCE CURRENT
(AMPS)
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
RG, GATE RESISTANCE (OHMS)
1
10
100
t, TIME
(ns)
VDD = 30 V
ID = 52 A
VGS = 10 V
TJ = 25
C
Figure 10. Diode Forward Voltage versus Current
0
QT, TOTAL CHARGE (nC)
20
40
60
80
140
ID = 52 A
TJ = 25
C
1000
100
10
1
12
6
2
0
8
4
36
33
27
24
6
3
0
QT
Q2
Q1
Q3
VGS
VDS
td(on)
td(off)
tf
tr
VGS = 0 V
TJ = 25
C
50
40
30
20
10
0
0.5
0.6
0.7
0.8
0.9
1
10
30
1.1
100
120
21
18
15
12
9
55
45
35
25
15
5
0.4
0.3
0.2
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25
C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."
Switching between the offstate and the onstate may
traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10
s. In addition the total power
averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R
JC).
A Power MOSFET designated EFET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many EFETs can withstand the stress of
draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.
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