Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

TMOS V

Power Field Effect Transistor

NChannel EnhancementMode Silicon Gate

TMOS V is a new technology designed to achieve an onresis-

tance area product about onehalf that of standard MOSFETs. This
new technology more than doubles the present cell density of our
50 and 60 volt TMOS devices. Just as with our TMOS EFET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
unexpected voltage transients.

New Features of TMOS V

Onresistance Area Product about Onehalf that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology

Faster Switching than EFET Predecessors

Features Common to TMOS V and TMOS EFETS

Avalanche Energy Specified

IDSS and VDS(on) Specified at Elevated Temperature

Static Parameters are the Same for both TMOS V and TMOS EFET

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

Vdc

DraintoGate Voltage (RGS = 1.0 M

)

VDGR

Vdc

GatetoSource Voltage -- Continuous

GatetoSource Voltage

-- Nonrepetitive (tp

10 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous

Drain Current

-- Continuous @ 100

Drain Current

-- Single Pulse (tp

ID
ID

IDM

52
41

182

Adc

Apk

Total Power Dissipation

Derate above 25

188

1.25

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 175

Single Pulse DraintoSource Avalanche Energy -- STARTING TJ = 25

(VDD = 25 Vdc, VGS = 5 Vdc, PEAK IL = 52 Apk, L = 0.3 mH, RG = 25

)

EAS

406

Thermal Resistance -- Junction to Case

Thermal Resistance

-- Junction to Ambient

0.8

62.5

C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

from Case for 10 seconds

260

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

EFET, Designer's, and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

MTP52N06VL

TMOS POWER FET

52 AMPERES

60 VOLTS

RDS(on) = 0.025 OHM

Motorola Preferred Device

CASE 221A06, Style 5

TO220AB

Motorola, Inc. 1996

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DraintoSource Breakdown Voltage

(Cpk

2.0) (3)

(VGS = 0 Vdc, ID = .25 mAdc)
Temperature Coefficient (Positive)

V(BR)DSS

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150

IDSS

--
--

100

Adc

GateBody Leakage Current (VGS =

15 Vdc, VDS = 0 Vdc)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(Cpk

2.0) (3)

(VDS = VGS, ID = 250

Adc)

Threshold Temperature Coefficient (Negative)

VGS(th)

1.0

1.5
4.5

2.0

Vdc

mV/

Static DraintoSource OnResistance

(Cpk

2.0) (3)

(VGS = 5 Vdc, ID = 26 Adc)

RDS(on)

0.022

0.025

Ohm

DraintoSource OnVoltage

(VGS = 5 Vdc, ID = 52 Adc)
(VGS = 5 Vdc, ID = 26 Adc, TJ = 150

VDS(on)

--
--

1.6
1.4

Vdc

Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc)

gFS

Mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

25 Vdc V

0 Vdc

Ciss

1900

2660

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

550

770

Transfer Capacitance

f = 1.0 MHz)

Crss

170

340

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

30 Vd

52 Ad

td(on)

Rise Time

(VDD = 30 Vdc, ID = 52 Adc,

VGS = 5 Vdc

500

1000

TurnOff Delay Time

VGS = 5 Vdc,

RG = 9.1

)

td(off)

100

200

Fall Time

)

200

400

Gate Charge

(See Figure 8)

48 Vd

52 Ad

(See Figure 8)

(VDS = 48 Vdc, ID = 52 Adc,

4.0

( DS

, D

VGS = 5 Vdc)

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage

(IS = 52 Adc, VGS = 0 Vdc)

(IS = 52 Adc, VGS = 0 Vdc, TJ = 150

VSD

--
--

1.03

0.9

1.5

Vdc

Reverse Recovery Time

52 Ad

0 Vd

trr

104

(IS = 52 Adc, VGS = 0 Vdc,

( S

dIS/dt = 100 A/

Reverse Recovery Stored Charge

QRR

0.28

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25

from package to center of die)

--
--

3.5
4.5

--
--

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.

Cpk =

Max limit Typ

3 x SIGMA

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(OHMS)

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(NORMALIZED)

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 1. OnRegion Characteristics

I D

, DRAIN CURRENT

(AMPS)

I D

, DRAIN CURRENT

(AMPS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

Figure 2. Transfer Characteristics

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(OHMS)

ID, DRAIN CURRENT (AMPS)

Figure 3. OnResistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current

and Gate Voltage

TJ, JUNCTION TEMPERATURE (

Figure 5. OnResistance Variation with

Temperature

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 6. DrainToSource Leakage

Current versus Voltage

I DSS

, LEAKAGE (nA)

TJ = 25

VGS = 10 V

7 V

8 V

5 V

4 V

3 V

100

1.0

2.5

VDS

10 V

TJ = 55

100

VGS = 5 V

.030

100

TJ = 100

TJ = 25

.040

VGS = 5 V

10 V

VGS = 5 V
ID = 26 A

1.6

1.4

0.6

0.4

100

125

150

VGS = 0 V

TJ = 125

100

1.5

.020

.010

.030

.020

.010

110

100

175

1.8

110

3.5

4.5

5.5

0.5

110

.035

.025

.015

.005

1.2

0.8

6 V

.060

.050

.040

100

0.2

1000

.070

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are determined

by how fast the FET input capacitance can be charged by
current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

At high switching speeds, parasitic circuit elements

complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate
drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
is complex. The MOSFET output capacitance also compli-
cates the mathematics. And finally, MOSFETs have finite
internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance is
difficult to measure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely
operated into an inductive load; however, snubbing reduces
switching losses.

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

C, CAP

ACIT

ANCE

(pF)

Figure 7. Capacitance Variation

6000

VGS

VDS

VDS = 0 V

5000

4000

3000

2000

VGS = 0 V

TJ = 25

Ciss

Coss

Crss

Ciss

Crss

1000

7000

8000

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

, DRAINT

OSOURCE

VOL

T
AGE

(VOL

TS)

, GA

TET

OSOURCE

VOL

T
AGE

(VOL

TS)

DRAINTOSOURCE DIODE CHARACTERISTICS

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

I S

, SOURCE CURRENT

(AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

RG, GATE RESISTANCE (OHMS)

100

t, TIME

(ns)

VDD = 30 V
ID = 52 A
VGS = 5 V
TJ = 25

Figure 10. Diode Forward Voltage versus Current

QT, TOTAL CHARGE (nC)

ID = 52 A
TJ = 25

1000

100

VGS

VDS

td(on)

td(off)

VGS = 0 V
TJ = 25

0.75

0.8 0.85

0.9 0.95

1.05

0.7

0.65

0.5

0.55

0.6

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (TC) of 25

Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGeneral
Data and Its Use."

Switching between the offstate and the onstate may

traverse any load line provided neither rated peak current
(IDM) nor rated voltage (VDSS) is exceeded and the transition
time (tr,tf) do not exceed 10

s. In addition the total power

averaged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A Power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For

reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is to
rate in terms of energy, avalanche energy capability is not a
constant. The energy rating decreases nonlinearly with an
increase of peak current in avalanche and peak junction
temperature.

Although many EFETs can withstand the stress of

draintosource avalanche at currents up to rated pulsed
current (IDM), the energy rating is specified at rated
continuous current (ID), in accordance with industry custom.
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
currents below rated continuous ID can safely be assumed to
equal the values indicated.

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

TJ, STARTING JUNCTION TEMPERATURE (

E AS

, SINGLE PULSE DRAINT

OSOURCE

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

0.1

100

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

ALANCHE ENERGY

(mJ)

I D

, DRAIN CURRENT

(AMPS)

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

100

125

VGS = 15 V
SINGLE PULSE
TC = 25

150

Figure 13. Thermal Response

Figure 14. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

1000

450

250

150

350

100

1 ms

10 ms

ID = 52 A

175

400

200

100

300

t, TIME (s)

r(t)

, NORMALIZED EFFECTIVE

TRANSIENT

THERMAL

RESIST

ANCE

JC(t) = r(t) R

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) R

JC(t)

P(pk)

DUTY CYCLE, D = t1/t2

0.1

0.01

1.0E05

1.0E04

1.0E03

1.0E02

1.0E01

1.0E+00

1.0E+01

D = 0.5

0.2

0.1

0.05

0.02

0.01

SINGLE PULSE

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A06

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

STYLE 5:

PIN 1. GATE

2. DRAIN
3. SOURCE
4. DRAIN

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.570

0.620

14.48

15.75

0.380

0.405

9.66

10.28

0.160

0.190

4.07

4.82

0.025

0.035

0.64

0.88

0.142

0.147

3.61

3.73

0.095

0.105

2.42

2.66

0.110

0.155

2.80

3.93

0.018

0.025

0.46

0.64

0.500

0.562

12.70

14.27

0.045

0.060

1.15

1.52

0.190

0.210

4.83

5.33

0.100

0.120

2.54

3.04

0.080

0.110

2.04

2.79

0.045

0.055

1.15

1.39

0.235

0.255

5.97

6.47

0.000

0.050

0.00

1.27

0.045

1.15

0.080

2.04

2 3

SEATING
PLANE

T

MTP52N06VL

Motorola TMOS Power MOSFET Transistor Device Data

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals"
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