Motorola TMOS Power MOSFET Transistor Device Data

Designer's

Data Sheet

TMOS E-FET

Power Field Effect Transistor

NChannel EnhancementMode Silicon Gate

This high voltage MOSFET uses an advanced termination

scheme to provide enhanced voltageblocking capability without
degrading performance over time. In addition, this advanced TMOS
EFET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a
draintosource diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.

Robust High Voltage Termination

Avalanche Energy Specified

SourcetoDrain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode

Diode is Characterized for Use in Bridge Circuits

IDSS and VDS(on) Specified at Elevated Temperature

MAXIMUM RATINGS

(TC = 25

C unless otherwise noted)

Rating

Symbol

Value

Unit

DraintoSource Voltage

VDSS

600

Vdc

DraintoGate Voltage (RGS = 1.0 M

)

VDGR

600

Vdc

GatetoSource Voltage -- Continuous

-- NonRepetitive (tp

10 ms)

VGS

VGSM

Vdc
Vpk

Drain Current -- Continuous

-- Continuous @ 100

-- Single Pulse (tp

ID
ID

IDM

6.0
4.6

Adc

Apk

Total Power Dissipation

Derate above 25

125

1.0

Watts

Operating and Storage Temperature Range

TJ, Tstg

55 to 150

Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25

(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25

)

EAS

405

Thermal Resistance -- Junction to Case

-- Junction to Ambient

1.0

62.5

C/W

Maximum Lead Temperature for Soldering Purposes, 1/8

from case for 10 seconds

260

Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.

EFET and Designer's are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

Preferred devices are Motorola recommended choices for future use and best overall value.

REV 3

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by MTP6N60E/D

MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Motorola, Inc. 1997

MTP6N60E

TMOS POWER FET

6.0 AMPERES

600 VOLTS

RDS(on) = 1.2 OHMS

Motorola Preferred Device

CASE 221A06, Style 5

TO220AB

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

ELECTRICAL CHARACTERISTICS

(TJ = 25

C unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

OFF CHARACTERISTICS

DraintoSource Breakdown Voltage

(VGS = 0 Vdc, ID = 0.25

Adc)

Temperature Coefficient (Positive)

V(BR)DSS

600

689

--
--

Vdc

mV/

Zero Gate Voltage Drain Current

(VDS = 600 Vdc, VGS = 0 Vdc)
(VDS = 600 Vdc, VGS = 0 Vdc, TJ = 125

IDSS

--
--

1.0

Adc

GateBody Leakage Current (VGS =

20 Vdc, VDS = 0 Vdc)

IGSS

100

nAdc

ON CHARACTERISTICS (1)

Gate Threshold Voltage

(VDS = VGS, ID = 250

Adc)

Temperature Coefficient (Negative)

VGS(th)

2.0

3.0
7.1

4.0

Vdc

mV/

Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc)

RDS(on)

0.94

1.2

Ohms

DraintoSource OnVoltage

(VGS = 10 Vdc, ID = 6.0 Adc)
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125

VDS(on)

--
--

6.0

8.6
7.6

Vdc

Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc)

gFS

2.0

5.5

mhos

DYNAMIC CHARACTERISTICS

Input Capacitance

25 Vdc V

0 Vdc

Ciss

1498

2100

Output Capacitance

(VDS = 25 Vdc, VGS = 0 Vdc,

f = 1.0 MHz)

Coss

158

220

Reverse Transfer Capacitance

f = 1.0 MHz)

Crss

SWITCHING CHARACTERISTICS (2)

TurnOn Delay Time

300 Vd

6 0 Ad

td(on)

Rise Time

(VDS = 300 Vdc, ID = 6.0 Adc,

VGS = 10 Vdc

TurnOff Delay Time

VGS = 10 Vdc,

RG = 9.1

)

td(off)

Fall Time

)

Gate Charge

300 Vd

6 0 Ad

35.5

(VDS = 300 Vdc, ID = 6.0 Adc,

8.1

( DS

, D

VGS = 10 Vdc)

14.1

15.8

SOURCEDRAIN DIODE CHARACTERISTICS

Forward OnVoltage (1)

(IS = 6.0 Adc, VGS = 0 Vdc)

(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125

VSD

--
--

0.83
0.72

1.2

Vdc

Reverse Recovery Time

6 0 Ad

0 Vd

trr

266

(IS = 6.0 Adc, VGS = 0 Vdc,

166

( S

dIS/dt = 100 A/

100

Reverse Recovery Stored Charge

QRR

2.5

INTERNAL PACKAGE INDUCTANCE

Internal Drain Inductance

(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25

from package to center of die)

--
--

3.5
4.5

--
--

Internal Source Inductance

(Measured from the source lead 0.25

from package to source bond pad)

7.5

(1) Pulse Test: Pulse Width

300

s, Duty Cycle

2%.

(2) Switching characteristics are independent of operating junction temperature.

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

TYPICAL ELECTRICAL CHARACTERISTICS

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(OHMS)

Figure 1. OnRegion Characteristics

Figure 2. Transfer Characteristics

Figure 3. OnResistance versus Drain Current

and Temperature

ID, DRAIN CURRENT (AMPS)

Figure 4. OnResistance versus Drain Current

and Gate Voltage

Figure 5. OnResistance Variation with

Temperature

Figure 6. DrainToSource Leakage

Current versus Voltage

TJ = 25

VGS = 10 V

15 V

1.1

1.3

1.4

1.2

1.0

0.9

0.8

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(NORMALIZED)

TJ, JUNCTION TEMPERATURE (

VGS = 10 V
ID = 3 A

100

150

125

2.5

1.5

0.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I D

, DRAIN CURRENT

(AMPS)

2.0

3.0

4.0

5.0

I D

, DRAIN CURRENT

(AMPS)

VGS, GATETOSOURCE VOLTAGE (VOLTS)

TJ = 25

VDS

10 V

TJ = 55

100

6 V

5 V

2.5

3.5

4.5

5.5

6.0

VGS = 10 V

7 V

1.0

2.0

DS(on)

, DRAINT

OSOURCE

RESIST

ANCE

(OHMS)

ID, DRAIN CURRENT (AMPS)

TJ = 100

VGS = 10 V

0.5

1.5

2.5

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I DSS

, LEAKAGE (nA)

VGS = 0 V

200

400

1000

100

300

600

500

TJ = 125

10000

100

4 V

8 V

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted

by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (

t) are deter-

mined by how fast the FET input capacitance can be charged
by current from the generator.

The published capacitance data is difficult to use for calculat-
ing rise and fall because draingate capacitance varies
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input
current (IG(AV)) can be made from a rudimentary analysis of
the drive circuit so that

t = Q/IG(AV)
During the rise and fall time interval when switching a resis-
tive load, VGS remains virtually constant at a level known as
the plateau voltage, VSGP. Therefore, rise and fall times may
be approximated by the following:

tr = Q2 x RG/(VGG VGSP)
tf = Q2 x RG/VGSP
where

VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turnon and turnoff delay times, gate current is
not constant. The simplest calculation uses appropriate val-
ues from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:

td(on) = RG Ciss In [VGG/(VGG VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the offstate condition when cal-
culating td(on) and is read at a voltage corresponding to the
onstate when calculating td(off).

At high switching speeds, parasitic circuit elements com-

plicate the analysis. The inductance of the MOSFET source
lead, inside the package and in the circuit wiring which is
common to both the drain and gate current paths, produces a
voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
mathematics. And finally, MOSFETs have finite internal gate
resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to mea-
sure and, consequently, is not specified.

The resistive switching time variation versus gate resis-

tance (Figure 9) shows how typical switching performance is
affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
value of unity regardless of the switching speed. The circuit
used to obtain the data is constructed to minimize common
inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
power electronic loads are inductive; the data in the figure is
taken with a resistive load, which approximates an optimally
snubbed inductive load. Power MOSFETs may be safely op-
erated into an inductive load; however, snubbing reduces
switching losses.

GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)

Figure 7a. Capacitance Variation

Figure 7b. High Voltage Capacitance Variation

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

C, CAP

ACIT

ANCE

(pF)

VGS

VDS

TJ = 25

VDS = 0 V

VGS = 0 V

2400

1600

800

Ciss

Coss

Crss

Ciss

Crss

3200

C, CAP

ACIT

ANCE

(pF)

Crss

Ciss

Coss

TJ = 25

VGS = 0 V

1000

100

1000

10000

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

DRAINTOSOURCE DIODE CHARACTERISTICS

VSD, SOURCETODRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

I S

, SOURCE CURRENT

(AMPS)

Figure 9. Resistive Switching Time

Variation versus Gate Resistance

Figure 8. GateToSource and DrainToSource

Voltage versus Total Charge

0.50

0.70

0.80

0.65

0.75

0.85

0.55

0.60

VGS = 0 V
TJ = 25

QT, TOTAL CHARGE (nC)

RG, GATE RESISTANCE (OHMS)

100

t, TIME

(ns)

VDD = 300 V
ID = 6 A
VGS = 10 V
TJ = 25

td(off)

td(on)

, GA

TET

OSOURCE

VOL

T
AGE

(VOL

TS)

300

200

100

, DRAINT

OSOURCE

VOL

T
AGE

(VOL

TS)

ID = 6 A
TJ = 25

VDS

VGS

1000

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define

the maximum simultaneous draintosource voltage and
drain current that a transistor can handle safely when it is for-
ward biased. Curves are based upon maximum peak junc-
tion temperature and a case temperature (TC) of 25

C. Peak

repetitive pulsed power limits are determined by using the
thermal response data in conjunction with the procedures
discussed in AN569, "Transient Thermal ResistanceGener-
al Data and Its Use."

Switching between the offstate and the onstate may tra-

verse any load line provided neither rated peak current (IDM)
nor rated voltage (VDSS) is exceeded and the transition time
(tr,tf) do not exceed 10

s. In addition the total power aver-

aged over a complete switching cycle must not exceed
(TJ(MAX) TC)/(R

JC).

A Power MOSFET designated EFET can be safely used

in switching circuits with unclamped inductive loads. For reli-

able operation, the stored energy from circuit inductance dis-
sipated in the transistor while in avalanche must be less than
the rated limit and adjusted for operating conditions differing
from those specified. Although industry practice is to rate in
terms of energy, avalanche energy capability is not a con-
stant. The energy rating decreases nonlinearly with an in-
crease of peak current in avalanche and peak junction
temperature.

Although many EFETs can withstand the stress of drain

tosource avalanche at currents up to rated pulsed current
(IDM), the energy rating is specified at rated continuous cur-
rent (ID), in accordance with industry custom. The energy rat-
ing must be derated for temperature as shown in the
accompanying graph (Figure 12). Maximum energy at cur-
rents below rated continuous ID can safely be assumed to
equal the values indicated.

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

SAFE OPERATING AREA

Figure 14. Diode Reverse Recovery Waveform

di/dt

trr

0.25 IS

TIME

Figure 12. Maximum Avalanche Energy versus

Starting Junction Temperature

Figure 11. Maximum Rated Forward Biased

Safe Operating Area

Figure 13. Thermal Response

100

1.0

0.1

100

1000

100

1 ms

10 ms

VDS, DRAINTOSOURCE VOLTAGE (VOLTS)

I D

, DRAIN CURRENT

(AMPS)

RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT

VGS = 20 V
SINGLE PULSE
TC = 25

TJ, STARTING JUNCTION TEMPERATURE (

E AS

, SINGLE PULSE DRAINNT

OSOURCE

ALANCHE ENERGY

(mJ)

100

125

450

ID = 6 A

150

400

150

100

200

250

300

350

r(t)

, NORMALIZED EFFECTIVE

TRANSIENT

THERMAL

RESIST

ANCE

0.1

0.01

0.00001

0.0001

0.001

0.01

0.1

t, TIME (SECONDS)

D = 0.5

0.2

0.1

0.05

0.02

0.01

JC(t) = r(t) R

D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
READ TIME AT t1
TJ(pk) TC = P(pk) R

JC(t)

P(pk)

DUTY CYCLE, D = t1/t2

SINGLE PULSE

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

PACKAGE DIMENSIONS

CASE 221A06

ISSUE Y

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL

BODY AND LEAD IRREGULARITIES ARE
ALLOWED.

DIM

MIN

MAX

MIN

MAX

MILLIMETERS

INCHES

0.570

0.620

14.48

15.75

0.380

0.405

9.66

10.28

0.160

0.190

4.07

4.82

0.025

0.035

0.64

0.88

0.142

0.147

3.61

3.73

0.095

0.105

2.42

2.66

0.110

0.155

2.80

3.93

0.018

0.025

0.46

0.64

0.500

0.562

12.70

14.27

0.045

0.060

1.15

1.52

0.190

0.210

4.83

5.33

0.100

0.120

2.54

3.04

0.080

0.110

2.04

2.79

0.045

0.055

1.15

1.39

0.235

0.255

5.97

6.47

0.000

0.050

0.00

1.27

0.045

1.15

0.080

2.04

2 3

SEATING
PLANE

T

STYLE 5:

PIN 1. GATE

2. DRAIN
3. SOURCE
4. DRAIN

MTP6N60E

Motorola TMOS Power MOSFET Transistor Device Data

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